Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7828075 |
1 |
|
|
T23 |
1 |
|
T24 |
109 |
|
T25 |
55380 |
| auto[1] |
5818488 |
1 |
|
|
T24 |
12 |
|
T25 |
48782 |
|
T26 |
1833 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12893958 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98604 |
| auto[1] |
752605 |
1 |
|
|
T24 |
1 |
|
T25 |
5558 |
|
T26 |
336 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7787981 |
1 |
|
|
T23 |
1 |
|
T24 |
105 |
|
T25 |
58554 |
| auto[1] |
5858582 |
1 |
|
|
T24 |
16 |
|
T25 |
45608 |
|
T26 |
1684 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2578496 |
1 |
|
|
T24 |
15 |
|
T25 |
19063 |
|
T26 |
609 |
| auto[1] |
auto[0] |
auto[1] |
380942 |
1 |
|
|
T24 |
1 |
|
T25 |
2626 |
|
T26 |
153 |
| auto[1] |
auto[1] |
auto[0] |
2527481 |
1 |
|
|
T25 |
20987 |
|
T26 |
739 |
|
T29 |
55354 |
| auto[1] |
auto[1] |
auto[1] |
371663 |
1 |
|
|
T25 |
2932 |
|
T26 |
183 |
|
T29 |
7985 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |