Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7831380 |
1 |
|
|
T23 |
1 |
|
T24 |
97 |
|
T25 |
61049 |
| auto[1] |
5815183 |
1 |
|
|
T24 |
24 |
|
T25 |
43113 |
|
T26 |
1699 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12891690 |
1 |
|
|
T23 |
1 |
|
T24 |
116 |
|
T25 |
98435 |
| auto[1] |
754873 |
1 |
|
|
T24 |
5 |
|
T25 |
5727 |
|
T26 |
369 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7768895 |
1 |
|
|
T23 |
1 |
|
T24 |
83 |
|
T25 |
57096 |
| auto[1] |
5877668 |
1 |
|
|
T24 |
38 |
|
T25 |
47066 |
|
T26 |
1871 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2578864 |
1 |
|
|
T24 |
25 |
|
T25 |
23004 |
|
T26 |
713 |
| auto[1] |
auto[0] |
auto[1] |
380197 |
1 |
|
|
T24 |
3 |
|
T25 |
3257 |
|
T26 |
179 |
| auto[1] |
auto[1] |
auto[0] |
2543931 |
1 |
|
|
T24 |
8 |
|
T25 |
18335 |
|
T26 |
789 |
| auto[1] |
auto[1] |
auto[1] |
374676 |
1 |
|
|
T24 |
2 |
|
T25 |
2470 |
|
T26 |
190 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |