Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7801540 |
1 |
|
|
T23 |
1 |
|
T24 |
99 |
|
T25 |
55442 |
| auto[1] |
5845023 |
1 |
|
|
T24 |
22 |
|
T25 |
48720 |
|
T26 |
1585 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12901514 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98659 |
| auto[1] |
745049 |
1 |
|
|
T24 |
2 |
|
T25 |
5503 |
|
T26 |
340 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7820921 |
1 |
|
|
T23 |
1 |
|
T24 |
79 |
|
T25 |
58130 |
| auto[1] |
5825642 |
1 |
|
|
T24 |
42 |
|
T25 |
46032 |
|
T26 |
1732 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2549346 |
1 |
|
|
T24 |
36 |
|
T25 |
20352 |
|
T26 |
633 |
| auto[1] |
auto[0] |
auto[1] |
373611 |
1 |
|
|
T24 |
2 |
|
T25 |
2802 |
|
T26 |
156 |
| auto[1] |
auto[1] |
auto[0] |
2531247 |
1 |
|
|
T24 |
4 |
|
T25 |
20177 |
|
T26 |
759 |
| auto[1] |
auto[1] |
auto[1] |
371438 |
1 |
|
|
T25 |
2701 |
|
T26 |
184 |
|
T29 |
7873 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |