Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7838980 |
1 |
|
|
T23 |
1 |
|
T24 |
113 |
|
T25 |
57872 |
| auto[1] |
5807583 |
1 |
|
|
T24 |
8 |
|
T25 |
46290 |
|
T26 |
1571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11209839 |
1 |
|
|
T23 |
1 |
|
T24 |
114 |
|
T25 |
75432 |
| auto[1] |
2436724 |
1 |
|
|
T24 |
7 |
|
T25 |
28730 |
|
T26 |
541 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7802205 |
1 |
|
|
T23 |
1 |
|
T24 |
96 |
|
T25 |
57465 |
| auto[1] |
5844358 |
1 |
|
|
T24 |
25 |
|
T25 |
46697 |
|
T26 |
1089 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1706053 |
1 |
|
|
T24 |
18 |
|
T25 |
9416 |
|
T26 |
213 |
| auto[1] |
auto[0] |
auto[1] |
1222756 |
1 |
|
|
T24 |
7 |
|
T25 |
14722 |
|
T26 |
213 |
| auto[1] |
auto[1] |
auto[0] |
1701581 |
1 |
|
|
T25 |
8551 |
|
T26 |
335 |
|
T29 |
38415 |
| auto[1] |
auto[1] |
auto[1] |
1213968 |
1 |
|
|
T25 |
14008 |
|
T26 |
328 |
|
T29 |
23149 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |