Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7798349 |
1 |
|
|
T23 |
1 |
|
T24 |
93 |
|
T25 |
57759 |
| auto[1] |
5848214 |
1 |
|
|
T24 |
28 |
|
T25 |
46403 |
|
T26 |
1391 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11213178 |
1 |
|
|
T23 |
1 |
|
T24 |
108 |
|
T25 |
75082 |
| auto[1] |
2433385 |
1 |
|
|
T24 |
13 |
|
T25 |
29080 |
|
T26 |
816 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7811531 |
1 |
|
|
T23 |
1 |
|
T24 |
92 |
|
T25 |
56689 |
| auto[1] |
5835032 |
1 |
|
|
T24 |
29 |
|
T25 |
47473 |
|
T26 |
1702 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1707079 |
1 |
|
|
T24 |
5 |
|
T25 |
9242 |
|
T26 |
448 |
| auto[1] |
auto[0] |
auto[1] |
1219108 |
1 |
|
|
T24 |
7 |
|
T25 |
14658 |
|
T26 |
398 |
| auto[1] |
auto[1] |
auto[0] |
1694568 |
1 |
|
|
T24 |
11 |
|
T25 |
9151 |
|
T26 |
438 |
| auto[1] |
auto[1] |
auto[1] |
1214277 |
1 |
|
|
T24 |
6 |
|
T25 |
14422 |
|
T26 |
418 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |