Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2560290 |
1 |
|
|
T24 |
26 |
|
T25 |
20796 |
|
T26 |
685 |
| auto[1] |
auto[0] |
auto[1] |
375997 |
1 |
|
|
T24 |
2 |
|
T25 |
2907 |
|
T26 |
167 |
| auto[1] |
auto[1] |
auto[0] |
2524940 |
1 |
|
|
T24 |
2 |
|
T25 |
20483 |
|
T26 |
521 |
| auto[1] |
auto[1] |
auto[1] |
372419 |
1 |
|
|
T24 |
1 |
|
T25 |
2827 |
|
T26 |
133 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |