Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7798916 |
1 |
|
|
T23 |
1 |
|
T24 |
103 |
|
T25 |
56655 |
| auto[1] |
5847647 |
1 |
|
|
T24 |
18 |
|
T25 |
47507 |
|
T26 |
1765 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11203744 |
1 |
|
|
T23 |
1 |
|
T24 |
112 |
|
T25 |
74021 |
| auto[1] |
2442819 |
1 |
|
|
T24 |
9 |
|
T25 |
30141 |
|
T26 |
928 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7792944 |
1 |
|
|
T23 |
1 |
|
T24 |
106 |
|
T25 |
55423 |
| auto[1] |
5853619 |
1 |
|
|
T24 |
15 |
|
T25 |
48739 |
|
T26 |
1790 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1721131 |
1 |
|
|
T24 |
6 |
|
T25 |
9058 |
|
T26 |
378 |
| auto[1] |
auto[0] |
auto[1] |
1224359 |
1 |
|
|
T24 |
9 |
|
T25 |
15009 |
|
T26 |
444 |
| auto[1] |
auto[1] |
auto[0] |
1689669 |
1 |
|
|
T25 |
9540 |
|
T26 |
484 |
|
T29 |
33916 |
| auto[1] |
auto[1] |
auto[1] |
1218460 |
1 |
|
|
T25 |
15132 |
|
T26 |
484 |
|
T29 |
20120 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |