Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7811856 |
1 |
|
|
T23 |
1 |
|
T24 |
103 |
|
T25 |
57824 |
| auto[1] |
5834707 |
1 |
|
|
T24 |
18 |
|
T25 |
46338 |
|
T26 |
1625 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11202947 |
1 |
|
|
T23 |
1 |
|
T24 |
118 |
|
T25 |
74086 |
| auto[1] |
2443616 |
1 |
|
|
T24 |
3 |
|
T25 |
30076 |
|
T26 |
698 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7795871 |
1 |
|
|
T23 |
1 |
|
T24 |
101 |
|
T25 |
55508 |
| auto[1] |
5850692 |
1 |
|
|
T24 |
20 |
|
T25 |
48654 |
|
T26 |
1343 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1699428 |
1 |
|
|
T24 |
7 |
|
T25 |
9243 |
|
T26 |
347 |
| auto[1] |
auto[0] |
auto[1] |
1220693 |
1 |
|
|
T24 |
3 |
|
T25 |
14580 |
|
T26 |
371 |
| auto[1] |
auto[1] |
auto[0] |
1707648 |
1 |
|
|
T24 |
10 |
|
T25 |
9335 |
|
T26 |
298 |
| auto[1] |
auto[1] |
auto[1] |
1222923 |
1 |
|
|
T25 |
15496 |
|
T26 |
327 |
|
T29 |
23828 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |