Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7811430 |
1 |
|
|
T23 |
1 |
|
T24 |
91 |
|
T25 |
57792 |
| auto[1] |
5835133 |
1 |
|
|
T24 |
30 |
|
T25 |
46370 |
|
T26 |
1782 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11196372 |
1 |
|
|
T23 |
1 |
|
T24 |
111 |
|
T25 |
74154 |
| auto[1] |
2450191 |
1 |
|
|
T24 |
10 |
|
T25 |
30008 |
|
T26 |
755 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7771230 |
1 |
|
|
T23 |
1 |
|
T24 |
101 |
|
T25 |
55203 |
| auto[1] |
5875333 |
1 |
|
|
T24 |
20 |
|
T25 |
48959 |
|
T26 |
1518 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1718154 |
1 |
|
|
T24 |
10 |
|
T25 |
9762 |
|
T26 |
300 |
| auto[1] |
auto[0] |
auto[1] |
1231184 |
1 |
|
|
T24 |
4 |
|
T25 |
15388 |
|
T26 |
262 |
| auto[1] |
auto[1] |
auto[0] |
1706988 |
1 |
|
|
T25 |
9189 |
|
T26 |
463 |
|
T29 |
39549 |
| auto[1] |
auto[1] |
auto[1] |
1219007 |
1 |
|
|
T24 |
6 |
|
T25 |
14620 |
|
T26 |
493 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |