Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7816171 |
1 |
|
|
T23 |
1 |
|
T24 |
115 |
|
T25 |
57905 |
| auto[1] |
5830392 |
1 |
|
|
T24 |
6 |
|
T25 |
46257 |
|
T26 |
1427 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11207698 |
1 |
|
|
T23 |
1 |
|
T24 |
111 |
|
T25 |
76295 |
| auto[1] |
2438865 |
1 |
|
|
T24 |
10 |
|
T25 |
27867 |
|
T26 |
856 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7789212 |
1 |
|
|
T23 |
1 |
|
T24 |
106 |
|
T25 |
58779 |
| auto[1] |
5857351 |
1 |
|
|
T24 |
15 |
|
T25 |
45383 |
|
T26 |
1719 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1720080 |
1 |
|
|
T24 |
5 |
|
T25 |
8367 |
|
T26 |
400 |
| auto[1] |
auto[0] |
auto[1] |
1228910 |
1 |
|
|
T24 |
4 |
|
T25 |
13231 |
|
T26 |
424 |
| auto[1] |
auto[1] |
auto[0] |
1698406 |
1 |
|
|
T25 |
9149 |
|
T26 |
463 |
|
T29 |
37865 |
| auto[1] |
auto[1] |
auto[1] |
1209955 |
1 |
|
|
T24 |
6 |
|
T25 |
14636 |
|
T26 |
432 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |