Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7790924 |
1 |
|
|
T23 |
1 |
|
T24 |
89 |
|
T25 |
58865 |
| auto[1] |
5855639 |
1 |
|
|
T24 |
32 |
|
T25 |
45297 |
|
T26 |
1479 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11207595 |
1 |
|
|
T23 |
1 |
|
T24 |
112 |
|
T25 |
73142 |
| auto[1] |
2438968 |
1 |
|
|
T24 |
9 |
|
T25 |
31020 |
|
T26 |
693 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7788960 |
1 |
|
|
T23 |
1 |
|
T24 |
93 |
|
T25 |
53748 |
| auto[1] |
5857603 |
1 |
|
|
T24 |
28 |
|
T25 |
50414 |
|
T26 |
1423 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1706610 |
1 |
|
|
T24 |
11 |
|
T25 |
10108 |
|
T26 |
391 |
| auto[1] |
auto[0] |
auto[1] |
1217152 |
1 |
|
|
T24 |
2 |
|
T25 |
16901 |
|
T26 |
348 |
| auto[1] |
auto[1] |
auto[0] |
1712025 |
1 |
|
|
T24 |
8 |
|
T25 |
9286 |
|
T26 |
339 |
| auto[1] |
auto[1] |
auto[1] |
1221816 |
1 |
|
|
T24 |
7 |
|
T25 |
14119 |
|
T26 |
345 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |