Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7787130 |
1 |
|
|
T23 |
1 |
|
T24 |
107 |
|
T25 |
56180 |
| auto[1] |
5859433 |
1 |
|
|
T24 |
14 |
|
T25 |
47982 |
|
T26 |
1959 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11213002 |
1 |
|
|
T23 |
1 |
|
T24 |
113 |
|
T25 |
75810 |
| auto[1] |
2433561 |
1 |
|
|
T24 |
8 |
|
T25 |
28352 |
|
T26 |
782 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7817908 |
1 |
|
|
T23 |
1 |
|
T24 |
88 |
|
T25 |
58047 |
| auto[1] |
5828655 |
1 |
|
|
T24 |
33 |
|
T25 |
46115 |
|
T26 |
1514 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1695805 |
1 |
|
|
T24 |
19 |
|
T25 |
8418 |
|
T26 |
288 |
| auto[1] |
auto[0] |
auto[1] |
1225404 |
1 |
|
|
T24 |
8 |
|
T25 |
14091 |
|
T26 |
285 |
| auto[1] |
auto[1] |
auto[0] |
1699289 |
1 |
|
|
T24 |
6 |
|
T25 |
9345 |
|
T26 |
444 |
| auto[1] |
auto[1] |
auto[1] |
1208157 |
1 |
|
|
T25 |
14261 |
|
T26 |
497 |
|
T29 |
23767 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |