Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7824296 |
1 |
|
|
T23 |
1 |
|
T24 |
105 |
|
T25 |
59233 |
| auto[1] |
5822267 |
1 |
|
|
T24 |
16 |
|
T25 |
44929 |
|
T26 |
1884 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11205908 |
1 |
|
|
T23 |
1 |
|
T24 |
106 |
|
T25 |
75355 |
| auto[1] |
2440655 |
1 |
|
|
T24 |
15 |
|
T25 |
28807 |
|
T26 |
900 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7804111 |
1 |
|
|
T23 |
1 |
|
T24 |
88 |
|
T25 |
57502 |
| auto[1] |
5842452 |
1 |
|
|
T24 |
33 |
|
T25 |
46660 |
|
T26 |
1803 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1714237 |
1 |
|
|
T24 |
16 |
|
T25 |
9109 |
|
T26 |
395 |
| auto[1] |
auto[0] |
auto[1] |
1232931 |
1 |
|
|
T24 |
9 |
|
T25 |
14811 |
|
T26 |
379 |
| auto[1] |
auto[1] |
auto[0] |
1687560 |
1 |
|
|
T24 |
2 |
|
T25 |
8744 |
|
T26 |
508 |
| auto[1] |
auto[1] |
auto[1] |
1207724 |
1 |
|
|
T24 |
6 |
|
T25 |
13996 |
|
T26 |
521 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |