Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7808239 |
1 |
|
|
T23 |
1 |
|
T24 |
103 |
|
T25 |
55696 |
| auto[1] |
5838324 |
1 |
|
|
T24 |
18 |
|
T25 |
48466 |
|
T26 |
1481 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11210942 |
1 |
|
|
T23 |
1 |
|
T24 |
118 |
|
T25 |
74955 |
| auto[1] |
2435621 |
1 |
|
|
T24 |
3 |
|
T25 |
29207 |
|
T26 |
884 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7814607 |
1 |
|
|
T23 |
1 |
|
T24 |
106 |
|
T25 |
56870 |
| auto[1] |
5831956 |
1 |
|
|
T24 |
15 |
|
T25 |
47292 |
|
T26 |
1798 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1703816 |
1 |
|
|
T24 |
10 |
|
T25 |
8618 |
|
T26 |
480 |
| auto[1] |
auto[0] |
auto[1] |
1222411 |
1 |
|
|
T24 |
3 |
|
T25 |
13785 |
|
T26 |
471 |
| auto[1] |
auto[1] |
auto[0] |
1692519 |
1 |
|
|
T24 |
2 |
|
T25 |
9467 |
|
T26 |
434 |
| auto[1] |
auto[1] |
auto[1] |
1213210 |
1 |
|
|
T25 |
15422 |
|
T26 |
413 |
|
T29 |
21742 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |