Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7823280 |
1 |
|
|
T23 |
1 |
|
T24 |
97 |
|
T25 |
55773 |
| auto[1] |
5823283 |
1 |
|
|
T24 |
24 |
|
T25 |
48389 |
|
T26 |
1237 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897023 |
1 |
|
|
T23 |
1 |
|
T24 |
118 |
|
T25 |
98724 |
| auto[1] |
749540 |
1 |
|
|
T24 |
3 |
|
T25 |
5438 |
|
T26 |
188 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7802955 |
1 |
|
|
T23 |
1 |
|
T24 |
83 |
|
T25 |
58991 |
| auto[1] |
5843608 |
1 |
|
|
T24 |
38 |
|
T25 |
45171 |
|
T26 |
1013 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2544951 |
1 |
|
|
T24 |
29 |
|
T25 |
19111 |
|
T26 |
545 |
| auto[1] |
auto[0] |
auto[1] |
373687 |
1 |
|
|
T24 |
2 |
|
T25 |
2563 |
|
T26 |
122 |
| auto[1] |
auto[1] |
auto[0] |
2549117 |
1 |
|
|
T24 |
6 |
|
T25 |
20622 |
|
T26 |
280 |
| auto[1] |
auto[1] |
auto[1] |
375853 |
1 |
|
|
T24 |
1 |
|
T25 |
2875 |
|
T26 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |