Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7809387 |
1 |
|
|
T23 |
1 |
|
T24 |
113 |
|
T25 |
55976 |
| auto[1] |
5837176 |
1 |
|
|
T24 |
8 |
|
T25 |
48186 |
|
T26 |
1639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11199197 |
1 |
|
|
T23 |
1 |
|
T24 |
109 |
|
T25 |
74554 |
| auto[1] |
2447366 |
1 |
|
|
T24 |
12 |
|
T25 |
29608 |
|
T26 |
631 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7768320 |
1 |
|
|
T23 |
1 |
|
T24 |
97 |
|
T25 |
56705 |
| auto[1] |
5878243 |
1 |
|
|
T24 |
24 |
|
T25 |
47457 |
|
T26 |
1270 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1711931 |
1 |
|
|
T24 |
12 |
|
T25 |
8747 |
|
T26 |
307 |
| auto[1] |
auto[0] |
auto[1] |
1220118 |
1 |
|
|
T24 |
12 |
|
T25 |
14113 |
|
T26 |
289 |
| auto[1] |
auto[1] |
auto[0] |
1718946 |
1 |
|
|
T25 |
9102 |
|
T26 |
332 |
|
T29 |
39608 |
| auto[1] |
auto[1] |
auto[1] |
1227248 |
1 |
|
|
T25 |
15495 |
|
T26 |
342 |
|
T29 |
23391 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |