Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7796456 |
1 |
|
|
T23 |
1 |
|
T24 |
109 |
|
T25 |
55762 |
| auto[1] |
5850107 |
1 |
|
|
T24 |
12 |
|
T25 |
48400 |
|
T26 |
1571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11210446 |
1 |
|
|
T23 |
1 |
|
T24 |
101 |
|
T25 |
75271 |
| auto[1] |
2436117 |
1 |
|
|
T24 |
20 |
|
T25 |
28891 |
|
T26 |
617 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7813464 |
1 |
|
|
T23 |
1 |
|
T24 |
89 |
|
T25 |
57489 |
| auto[1] |
5833099 |
1 |
|
|
T24 |
32 |
|
T25 |
46673 |
|
T26 |
1334 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1691742 |
1 |
|
|
T24 |
10 |
|
T25 |
8706 |
|
T26 |
314 |
| auto[1] |
auto[0] |
auto[1] |
1215908 |
1 |
|
|
T24 |
14 |
|
T25 |
14262 |
|
T26 |
278 |
| auto[1] |
auto[1] |
auto[0] |
1705240 |
1 |
|
|
T24 |
2 |
|
T25 |
9076 |
|
T26 |
403 |
| auto[1] |
auto[1] |
auto[1] |
1220209 |
1 |
|
|
T24 |
6 |
|
T25 |
14629 |
|
T26 |
339 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |