Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7830016 |
1 |
|
|
T23 |
1 |
|
T24 |
97 |
|
T25 |
58397 |
| auto[1] |
5816547 |
1 |
|
|
T24 |
24 |
|
T25 |
45765 |
|
T26 |
1610 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11223782 |
1 |
|
|
T23 |
1 |
|
T24 |
107 |
|
T25 |
74783 |
| auto[1] |
2422781 |
1 |
|
|
T24 |
14 |
|
T25 |
29379 |
|
T26 |
771 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7846045 |
1 |
|
|
T23 |
1 |
|
T24 |
94 |
|
T25 |
55725 |
| auto[1] |
5800518 |
1 |
|
|
T24 |
27 |
|
T25 |
48437 |
|
T26 |
1476 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1692288 |
1 |
|
|
T24 |
13 |
|
T25 |
9653 |
|
T26 |
307 |
| auto[1] |
auto[0] |
auto[1] |
1211245 |
1 |
|
|
T24 |
8 |
|
T25 |
14933 |
|
T26 |
353 |
| auto[1] |
auto[1] |
auto[0] |
1685449 |
1 |
|
|
T25 |
9405 |
|
T26 |
398 |
|
T29 |
37224 |
| auto[1] |
auto[1] |
auto[1] |
1211536 |
1 |
|
|
T24 |
6 |
|
T25 |
14446 |
|
T26 |
418 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |