Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7798633 |
1 |
|
|
T23 |
1 |
|
T24 |
85 |
|
T25 |
58332 |
| auto[1] |
5847930 |
1 |
|
|
T24 |
36 |
|
T25 |
45830 |
|
T26 |
1684 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12898031 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98258 |
| auto[1] |
748532 |
1 |
|
|
T24 |
1 |
|
T25 |
5904 |
|
T26 |
261 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7806254 |
1 |
|
|
T23 |
1 |
|
T24 |
79 |
|
T25 |
54936 |
| auto[1] |
5840309 |
1 |
|
|
T24 |
42 |
|
T25 |
49226 |
|
T26 |
1410 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2546963 |
1 |
|
|
T24 |
25 |
|
T25 |
22612 |
|
T26 |
504 |
| auto[1] |
auto[0] |
auto[1] |
374330 |
1 |
|
|
T24 |
1 |
|
T25 |
3134 |
|
T26 |
108 |
| auto[1] |
auto[1] |
auto[0] |
2544814 |
1 |
|
|
T24 |
16 |
|
T25 |
20710 |
|
T26 |
645 |
| auto[1] |
auto[1] |
auto[1] |
374202 |
1 |
|
|
T25 |
2770 |
|
T26 |
153 |
|
T29 |
7461 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |