Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7787881 |
1 |
|
|
T23 |
1 |
|
T24 |
105 |
|
T25 |
59111 |
| auto[1] |
5858682 |
1 |
|
|
T24 |
16 |
|
T25 |
45051 |
|
T26 |
1822 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897886 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98336 |
| auto[1] |
748677 |
1 |
|
|
T24 |
2 |
|
T25 |
5826 |
|
T26 |
369 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7808081 |
1 |
|
|
T23 |
1 |
|
T24 |
93 |
|
T25 |
56793 |
| auto[1] |
5838482 |
1 |
|
|
T24 |
28 |
|
T25 |
47369 |
|
T26 |
1883 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2545149 |
1 |
|
|
T24 |
26 |
|
T25 |
22201 |
|
T26 |
771 |
| auto[1] |
auto[0] |
auto[1] |
374094 |
1 |
|
|
T24 |
2 |
|
T25 |
3106 |
|
T26 |
189 |
| auto[1] |
auto[1] |
auto[0] |
2544656 |
1 |
|
|
T25 |
19342 |
|
T26 |
743 |
|
T29 |
54523 |
| auto[1] |
auto[1] |
auto[1] |
374583 |
1 |
|
|
T25 |
2720 |
|
T26 |
180 |
|
T29 |
8125 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |