Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7834574 |
1 |
|
|
T23 |
1 |
|
T24 |
103 |
|
T25 |
59071 |
| auto[1] |
5811989 |
1 |
|
|
T24 |
18 |
|
T25 |
45091 |
|
T26 |
1404 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12897656 |
1 |
|
|
T23 |
1 |
|
T24 |
119 |
|
T25 |
98359 |
| auto[1] |
748907 |
1 |
|
|
T24 |
2 |
|
T25 |
5803 |
|
T26 |
240 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7800572 |
1 |
|
|
T23 |
1 |
|
T24 |
98 |
|
T25 |
56716 |
| auto[1] |
5845991 |
1 |
|
|
T24 |
23 |
|
T25 |
47446 |
|
T26 |
1255 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2561025 |
1 |
|
|
T24 |
16 |
|
T25 |
21933 |
|
T26 |
593 |
| auto[1] |
auto[0] |
auto[1] |
376172 |
1 |
|
|
T24 |
2 |
|
T25 |
3074 |
|
T26 |
136 |
| auto[1] |
auto[1] |
auto[0] |
2536059 |
1 |
|
|
T24 |
5 |
|
T25 |
19710 |
|
T26 |
422 |
| auto[1] |
auto[1] |
auto[1] |
372735 |
1 |
|
|
T25 |
2729 |
|
T26 |
104 |
|
T29 |
8230 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |