Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7806060 |
1 |
|
|
T23 |
1 |
|
T24 |
97 |
|
T25 |
57791 |
| auto[1] |
5840503 |
1 |
|
|
T24 |
24 |
|
T25 |
46371 |
|
T26 |
1519 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12901344 |
1 |
|
|
T23 |
1 |
|
T24 |
120 |
|
T25 |
98539 |
| auto[1] |
745219 |
1 |
|
|
T24 |
1 |
|
T25 |
5623 |
|
T26 |
258 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7826867 |
1 |
|
|
T23 |
1 |
|
T24 |
98 |
|
T25 |
57544 |
| auto[1] |
5819696 |
1 |
|
|
T24 |
23 |
|
T25 |
46618 |
|
T26 |
1407 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2548934 |
1 |
|
|
T24 |
18 |
|
T25 |
21153 |
|
T26 |
648 |
| auto[1] |
auto[0] |
auto[1] |
374471 |
1 |
|
|
T24 |
1 |
|
T25 |
3000 |
|
T26 |
142 |
| auto[1] |
auto[1] |
auto[0] |
2525543 |
1 |
|
|
T24 |
4 |
|
T25 |
19842 |
|
T26 |
501 |
| auto[1] |
auto[1] |
auto[1] |
370748 |
1 |
|
|
T25 |
2623 |
|
T26 |
116 |
|
T29 |
7686 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |