Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 943
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T764 /workspace/coverage/cover_reg_top/21.gpio_intr_test.4076087396 May 12 12:41:24 PM PDT 24 May 12 12:41:25 PM PDT 24 67202780 ps
T765 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3796930225 May 12 12:41:25 PM PDT 24 May 12 12:41:27 PM PDT 24 117398416 ps
T766 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2508764458 May 12 12:41:46 PM PDT 24 May 12 12:41:48 PM PDT 24 13147143 ps
T767 /workspace/coverage/cover_reg_top/40.gpio_intr_test.1047844749 May 12 12:41:19 PM PDT 24 May 12 12:41:20 PM PDT 24 42899917 ps
T768 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.777940481 May 12 12:41:22 PM PDT 24 May 12 12:41:23 PM PDT 24 58032954 ps
T769 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3098041393 May 12 12:41:13 PM PDT 24 May 12 12:41:14 PM PDT 24 21627076 ps
T770 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2527293301 May 12 12:41:47 PM PDT 24 May 12 12:41:48 PM PDT 24 17449736 ps
T771 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1150397571 May 12 12:41:23 PM PDT 24 May 12 12:41:25 PM PDT 24 24375687 ps
T772 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2946061329 May 12 12:41:25 PM PDT 24 May 12 12:41:27 PM PDT 24 17472404 ps
T773 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.130200318 May 12 12:41:10 PM PDT 24 May 12 12:41:11 PM PDT 24 38195695 ps
T774 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1112582214 May 12 12:41:17 PM PDT 24 May 12 12:41:19 PM PDT 24 23717209 ps
T81 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1907926692 May 12 12:41:09 PM PDT 24 May 12 12:41:10 PM PDT 24 68503092 ps
T775 /workspace/coverage/cover_reg_top/24.gpio_intr_test.313858600 May 12 12:41:33 PM PDT 24 May 12 12:41:34 PM PDT 24 41326196 ps
T776 /workspace/coverage/cover_reg_top/44.gpio_intr_test.480133131 May 12 12:41:31 PM PDT 24 May 12 12:41:32 PM PDT 24 24971023 ps
T777 /workspace/coverage/cover_reg_top/38.gpio_intr_test.485278825 May 12 12:41:27 PM PDT 24 May 12 12:41:29 PM PDT 24 16024305 ps
T778 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4027121097 May 12 12:41:22 PM PDT 24 May 12 12:41:24 PM PDT 24 61424458 ps
T779 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2179486345 May 12 12:41:19 PM PDT 24 May 12 12:41:21 PM PDT 24 20671969 ps
T70 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1070303645 May 12 12:41:12 PM PDT 24 May 12 12:41:13 PM PDT 24 58993758 ps
T780 /workspace/coverage/cover_reg_top/5.gpio_intr_test.879251069 May 12 12:41:15 PM PDT 24 May 12 12:41:17 PM PDT 24 81732205 ps
T71 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3195662020 May 12 12:41:24 PM PDT 24 May 12 12:41:25 PM PDT 24 41748065 ps
T82 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2946933671 May 12 12:41:46 PM PDT 24 May 12 12:41:47 PM PDT 24 16429583 ps
T83 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1185326797 May 12 12:41:17 PM PDT 24 May 12 12:41:19 PM PDT 24 98875329 ps
T781 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1397102438 May 12 12:41:21 PM PDT 24 May 12 12:41:22 PM PDT 24 21029481 ps
T782 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2010763265 May 12 12:41:12 PM PDT 24 May 12 12:41:14 PM PDT 24 237590045 ps
T783 /workspace/coverage/cover_reg_top/2.gpio_intr_test.609092416 May 12 12:41:11 PM PDT 24 May 12 12:41:13 PM PDT 24 12375227 ps
T784 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3124405602 May 12 12:41:29 PM PDT 24 May 12 12:41:30 PM PDT 24 14592360 ps
T785 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1736336065 May 12 12:41:23 PM PDT 24 May 12 12:41:25 PM PDT 24 70672467 ps
T786 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3378976303 May 12 12:41:27 PM PDT 24 May 12 12:41:29 PM PDT 24 47537438 ps
T787 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3351838624 May 12 12:41:21 PM PDT 24 May 12 12:41:23 PM PDT 24 66307823 ps
T788 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1415301937 May 12 12:41:25 PM PDT 24 May 12 12:41:29 PM PDT 24 430247045 ps
T72 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3536464611 May 12 12:40:55 PM PDT 24 May 12 12:40:58 PM PDT 24 81498031 ps
T789 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3106955839 May 12 12:41:47 PM PDT 24 May 12 12:41:48 PM PDT 24 21497218 ps
T790 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2289515413 May 12 12:41:24 PM PDT 24 May 12 12:41:26 PM PDT 24 117458670 ps
T791 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2838202132 May 12 12:40:55 PM PDT 24 May 12 12:40:56 PM PDT 24 34578778 ps
T792 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2107647832 May 12 12:41:03 PM PDT 24 May 12 12:41:06 PM PDT 24 135188777 ps
T793 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2085166202 May 12 12:41:16 PM PDT 24 May 12 12:41:18 PM PDT 24 39435937 ps
T794 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2230831523 May 12 12:41:26 PM PDT 24 May 12 12:41:28 PM PDT 24 85465971 ps
T795 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.775408478 May 12 12:41:42 PM PDT 24 May 12 12:41:43 PM PDT 24 37939169 ps
T796 /workspace/coverage/cover_reg_top/35.gpio_intr_test.739224773 May 12 12:41:30 PM PDT 24 May 12 12:41:32 PM PDT 24 43843899 ps
T797 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3163493756 May 12 12:41:16 PM PDT 24 May 12 12:41:18 PM PDT 24 36405467 ps
T798 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1608986328 May 12 12:41:34 PM PDT 24 May 12 12:41:35 PM PDT 24 155726048 ps
T799 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2496121199 May 12 12:41:20 PM PDT 24 May 12 12:41:22 PM PDT 24 64166902 ps
T800 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2285359227 May 12 12:41:25 PM PDT 24 May 12 12:41:26 PM PDT 24 13988229 ps
T801 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.665764353 May 12 12:41:18 PM PDT 24 May 12 12:41:21 PM PDT 24 318832671 ps
T802 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.997903029 May 12 12:41:29 PM PDT 24 May 12 12:41:31 PM PDT 24 57698907 ps
T803 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3379832673 May 12 12:40:57 PM PDT 24 May 12 12:40:58 PM PDT 24 42710408 ps
T74 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3167855843 May 12 12:41:15 PM PDT 24 May 12 12:41:17 PM PDT 24 47167854 ps
T804 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3959887625 May 12 12:41:24 PM PDT 24 May 12 12:41:25 PM PDT 24 11168050 ps
T95 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1732637611 May 12 12:41:15 PM PDT 24 May 12 12:41:17 PM PDT 24 165842504 ps
T805 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1883949641 May 12 12:41:13 PM PDT 24 May 12 12:41:14 PM PDT 24 16430167 ps
T806 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1731946735 May 12 12:41:17 PM PDT 24 May 12 12:41:19 PM PDT 24 15190763 ps
T807 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2935261977 May 12 12:41:16 PM PDT 24 May 12 12:41:18 PM PDT 24 18876872 ps
T808 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2920202916 May 12 12:41:29 PM PDT 24 May 12 12:41:32 PM PDT 24 184070036 ps
T809 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1203566195 May 12 12:41:11 PM PDT 24 May 12 12:41:13 PM PDT 24 30445966 ps
T810 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.649501494 May 12 12:41:19 PM PDT 24 May 12 12:41:20 PM PDT 24 39226661 ps
T46 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.807081376 May 12 12:41:15 PM PDT 24 May 12 12:41:18 PM PDT 24 108062216 ps
T811 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1823188050 May 12 12:41:21 PM PDT 24 May 12 12:41:24 PM PDT 24 37920311 ps
T812 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1802453007 May 12 12:41:14 PM PDT 24 May 12 12:41:16 PM PDT 24 128784037 ps
T813 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1978046560 May 12 12:41:47 PM PDT 24 May 12 12:41:49 PM PDT 24 29214265 ps
T814 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3741651361 May 12 12:41:24 PM PDT 24 May 12 12:41:26 PM PDT 24 44151725 ps
T44 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2452885233 May 12 12:41:17 PM PDT 24 May 12 12:41:19 PM PDT 24 38005616 ps
T815 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2080763010 May 12 12:40:57 PM PDT 24 May 12 12:40:58 PM PDT 24 58684709 ps
T816 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1726257523 May 12 12:41:14 PM PDT 24 May 12 12:41:17 PM PDT 24 430516902 ps
T817 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.4146474351 May 12 12:42:05 PM PDT 24 May 12 12:42:06 PM PDT 24 28119431 ps
T818 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3253511209 May 12 12:41:23 PM PDT 24 May 12 12:41:24 PM PDT 24 12941321 ps
T819 /workspace/coverage/cover_reg_top/12.gpio_intr_test.96718784 May 12 12:41:19 PM PDT 24 May 12 12:41:20 PM PDT 24 43372905 ps
T820 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3955073037 May 12 12:41:38 PM PDT 24 May 12 12:41:40 PM PDT 24 119065321 ps
T821 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3864273292 May 12 12:41:12 PM PDT 24 May 12 12:41:16 PM PDT 24 143579311 ps
T75 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.848450253 May 12 12:41:17 PM PDT 24 May 12 12:41:19 PM PDT 24 51884333 ps
T822 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.502480968 May 12 12:41:23 PM PDT 24 May 12 12:41:26 PM PDT 24 42008475 ps
T823 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4106083863 May 12 12:41:29 PM PDT 24 May 12 12:41:31 PM PDT 24 57463615 ps
T824 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4137338144 May 12 12:41:55 PM PDT 24 May 12 12:41:56 PM PDT 24 45339871 ps
T825 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2218940890 May 12 12:41:14 PM PDT 24 May 12 12:41:15 PM PDT 24 15210182 ps
T826 /workspace/coverage/cover_reg_top/20.gpio_intr_test.4121517947 May 12 12:41:29 PM PDT 24 May 12 12:41:30 PM PDT 24 25730180 ps
T73 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1516531289 May 12 12:41:25 PM PDT 24 May 12 12:41:27 PM PDT 24 19106187 ps
T827 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3252962861 May 12 12:41:48 PM PDT 24 May 12 12:41:49 PM PDT 24 17137183 ps
T47 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4035294060 May 12 12:41:43 PM PDT 24 May 12 12:41:44 PM PDT 24 42904115 ps
T828 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1788285120 May 12 12:41:19 PM PDT 24 May 12 12:41:21 PM PDT 24 47500978 ps
T829 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1253549385 May 12 12:40:57 PM PDT 24 May 12 12:40:59 PM PDT 24 19366543 ps
T830 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3783635236 May 12 12:41:56 PM PDT 24 May 12 12:41:57 PM PDT 24 65643779 ps
T831 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2121639858 May 12 12:41:14 PM PDT 24 May 12 12:41:15 PM PDT 24 19278768 ps
T832 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2385665348 May 12 12:41:22 PM PDT 24 May 12 12:41:24 PM PDT 24 78098653 ps
T833 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2227192108 May 12 12:41:13 PM PDT 24 May 12 12:41:25 PM PDT 24 12402961 ps
T834 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2152521624 May 12 12:41:19 PM PDT 24 May 12 12:41:20 PM PDT 24 29005416 ps
T835 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4121048440 May 12 12:41:52 PM PDT 24 May 12 12:41:54 PM PDT 24 345655491 ps
T836 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3863861108 May 12 12:41:46 PM PDT 24 May 12 12:41:47 PM PDT 24 71552508 ps
T837 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1820217294 May 12 12:41:30 PM PDT 24 May 12 12:41:32 PM PDT 24 41241140 ps
T838 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2646353481 May 12 12:41:07 PM PDT 24 May 12 12:41:09 PM PDT 24 57737153 ps
T839 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3148265356 May 12 12:41:48 PM PDT 24 May 12 12:41:49 PM PDT 24 21280751 ps
T840 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.673810429 May 12 12:41:38 PM PDT 24 May 12 12:41:39 PM PDT 24 14735938 ps
T841 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1971194769 May 12 12:41:15 PM PDT 24 May 12 12:41:17 PM PDT 24 32259119 ps
T842 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3363944170 May 12 12:41:16 PM PDT 24 May 12 12:41:18 PM PDT 24 14113242 ps
T843 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2667047570 May 12 12:41:15 PM PDT 24 May 12 12:41:18 PM PDT 24 71748836 ps
T844 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3720813455 May 12 12:41:41 PM PDT 24 May 12 12:41:43 PM PDT 24 73334133 ps
T845 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2400644750 May 12 12:41:29 PM PDT 24 May 12 12:41:31 PM PDT 24 51066075 ps
T846 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2439043770 May 12 12:41:23 PM PDT 24 May 12 12:41:25 PM PDT 24 233419407 ps
T847 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1442142272 May 12 12:41:15 PM PDT 24 May 12 12:41:18 PM PDT 24 106725006 ps
T848 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3185499516 May 12 12:41:34 PM PDT 24 May 12 12:41:36 PM PDT 24 87425309 ps
T849 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.326000252 May 12 12:41:52 PM PDT 24 May 12 12:41:53 PM PDT 24 64210861 ps
T850 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2458921037 May 12 12:41:47 PM PDT 24 May 12 12:41:49 PM PDT 24 37160943 ps
T851 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2096086673 May 12 12:41:30 PM PDT 24 May 12 12:41:32 PM PDT 24 94949929 ps
T852 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1638421339 May 12 12:41:30 PM PDT 24 May 12 12:41:33 PM PDT 24 155531721 ps
T853 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.354460891 May 12 12:41:47 PM PDT 24 May 12 12:41:49 PM PDT 24 134261258 ps
T854 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3021214196 May 12 12:41:49 PM PDT 24 May 12 12:41:56 PM PDT 24 198588876 ps
T855 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1120729817 May 12 12:41:52 PM PDT 24 May 12 12:41:54 PM PDT 24 275370072 ps
T856 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1965567927 May 12 12:41:29 PM PDT 24 May 12 12:41:31 PM PDT 24 348911073 ps
T857 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.600494792 May 12 12:41:29 PM PDT 24 May 12 12:41:31 PM PDT 24 129029705 ps
T858 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2337337032 May 12 12:41:45 PM PDT 24 May 12 12:41:46 PM PDT 24 148999374 ps
T859 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4167517283 May 12 12:41:49 PM PDT 24 May 12 12:41:50 PM PDT 24 47654237 ps
T860 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1710267822 May 12 12:41:26 PM PDT 24 May 12 12:41:28 PM PDT 24 177200899 ps
T861 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2498536286 May 12 12:41:42 PM PDT 24 May 12 12:41:43 PM PDT 24 178263897 ps
T862 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4074559819 May 12 12:41:46 PM PDT 24 May 12 12:41:48 PM PDT 24 260776266 ps
T863 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3416891083 May 12 12:41:36 PM PDT 24 May 12 12:41:37 PM PDT 24 60102846 ps
T864 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2349974047 May 12 12:41:46 PM PDT 24 May 12 12:41:48 PM PDT 24 141194538 ps
T865 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1808814034 May 12 12:41:27 PM PDT 24 May 12 12:41:30 PM PDT 24 76459513 ps
T866 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3553191109 May 12 12:41:47 PM PDT 24 May 12 12:41:49 PM PDT 24 114922116 ps
T867 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1867374403 May 12 12:41:54 PM PDT 24 May 12 12:41:55 PM PDT 24 125052417 ps
T868 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1166236737 May 12 12:41:26 PM PDT 24 May 12 12:41:28 PM PDT 24 282736757 ps
T869 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.352869302 May 12 12:41:27 PM PDT 24 May 12 12:41:29 PM PDT 24 31123899 ps
T870 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3356082246 May 12 12:41:29 PM PDT 24 May 12 12:41:32 PM PDT 24 113612862 ps
T871 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2742722770 May 12 12:41:30 PM PDT 24 May 12 12:41:32 PM PDT 24 34221924 ps
T872 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3965072294 May 12 12:41:46 PM PDT 24 May 12 12:41:48 PM PDT 24 39996664 ps
T873 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2419337622 May 12 12:41:29 PM PDT 24 May 12 12:41:31 PM PDT 24 46535945 ps
T874 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2413469744 May 12 12:41:22 PM PDT 24 May 12 12:41:24 PM PDT 24 36764392 ps
T875 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4162459416 May 12 12:41:25 PM PDT 24 May 12 12:41:27 PM PDT 24 59418043 ps
T876 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3303824702 May 12 12:41:43 PM PDT 24 May 12 12:41:44 PM PDT 24 625939430 ps
T877 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.461299594 May 12 12:41:24 PM PDT 24 May 12 12:41:26 PM PDT 24 30970765 ps
T878 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4253413138 May 12 12:41:18 PM PDT 24 May 12 12:41:20 PM PDT 24 230874176 ps
T879 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2566399016 May 12 12:41:55 PM PDT 24 May 12 12:41:56 PM PDT 24 97340488 ps
T880 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1846559658 May 12 12:41:31 PM PDT 24 May 12 12:41:33 PM PDT 24 35512665 ps
T881 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1835336475 May 12 12:41:15 PM PDT 24 May 12 12:41:17 PM PDT 24 120827221 ps
T882 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2343036227 May 12 12:41:34 PM PDT 24 May 12 12:41:35 PM PDT 24 290492176 ps
T883 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.330750701 May 12 12:41:59 PM PDT 24 May 12 12:42:00 PM PDT 24 135514683 ps
T884 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3786466102 May 12 12:41:26 PM PDT 24 May 12 12:41:29 PM PDT 24 56495948 ps
T885 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1637246616 May 12 12:41:26 PM PDT 24 May 12 12:41:29 PM PDT 24 42824277 ps
T886 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249268987 May 12 12:41:39 PM PDT 24 May 12 12:41:41 PM PDT 24 99656210 ps
T887 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1772706246 May 12 12:41:32 PM PDT 24 May 12 12:41:34 PM PDT 24 697058414 ps
T888 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2633752257 May 12 12:41:46 PM PDT 24 May 12 12:41:48 PM PDT 24 158264170 ps
T889 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2414979640 May 12 12:41:26 PM PDT 24 May 12 12:41:28 PM PDT 24 191960642 ps
T890 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2474472081 May 12 12:41:41 PM PDT 24 May 12 12:41:42 PM PDT 24 68191014 ps
T891 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3766430793 May 12 12:41:34 PM PDT 24 May 12 12:41:36 PM PDT 24 40819402 ps
T892 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2332164349 May 12 12:41:38 PM PDT 24 May 12 12:41:40 PM PDT 24 158646595 ps
T893 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1676928759 May 12 12:41:22 PM PDT 24 May 12 12:41:24 PM PDT 24 87846563 ps
T894 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1703582512 May 12 12:41:56 PM PDT 24 May 12 12:41:57 PM PDT 24 62485155 ps
T895 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.574065377 May 12 12:41:42 PM PDT 24 May 12 12:41:43 PM PDT 24 181347215 ps
T896 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4239893420 May 12 12:41:27 PM PDT 24 May 12 12:41:29 PM PDT 24 48229883 ps
T897 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2716720509 May 12 12:41:30 PM PDT 24 May 12 12:41:32 PM PDT 24 244350742 ps
T898 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2863974979 May 12 12:41:27 PM PDT 24 May 12 12:41:29 PM PDT 24 42873561 ps
T899 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1364192563 May 12 12:41:29 PM PDT 24 May 12 12:41:31 PM PDT 24 142939402 ps
T900 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2707290887 May 12 12:41:42 PM PDT 24 May 12 12:41:44 PM PDT 24 156420117 ps
T901 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1406128657 May 12 12:41:27 PM PDT 24 May 12 12:41:29 PM PDT 24 266992437 ps
T902 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.447019439 May 12 12:41:30 PM PDT 24 May 12 12:41:32 PM PDT 24 187567401 ps
T903 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3503515381 May 12 12:41:16 PM PDT 24 May 12 12:41:18 PM PDT 24 118172603 ps
T904 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.20661681 May 12 12:41:29 PM PDT 24 May 12 12:41:31 PM PDT 24 258609683 ps
T905 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2968772411 May 12 12:41:20 PM PDT 24 May 12 12:41:22 PM PDT 24 337277645 ps
T906 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.928943944 May 12 12:41:31 PM PDT 24 May 12 12:41:33 PM PDT 24 20160161 ps
T907 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2266661003 May 12 12:41:48 PM PDT 24 May 12 12:41:50 PM PDT 24 656955906 ps
T908 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1425461847 May 12 12:41:38 PM PDT 24 May 12 12:41:40 PM PDT 24 166272420 ps
T909 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3410423249 May 12 12:41:38 PM PDT 24 May 12 12:41:39 PM PDT 24 149682343 ps
T910 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2755541260 May 12 12:41:22 PM PDT 24 May 12 12:41:24 PM PDT 24 40105565 ps
T911 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2921935201 May 12 12:41:48 PM PDT 24 May 12 12:41:50 PM PDT 24 56696814 ps
T912 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1086463932 May 12 12:41:26 PM PDT 24 May 12 12:41:28 PM PDT 24 112706028 ps
T913 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.209285655 May 12 12:41:26 PM PDT 24 May 12 12:41:28 PM PDT 24 130272303 ps
T914 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.991370073 May 12 12:41:40 PM PDT 24 May 12 12:41:42 PM PDT 24 350332071 ps
T915 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.46534320 May 12 12:41:51 PM PDT 24 May 12 12:41:57 PM PDT 24 63734033 ps
T916 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3005677863 May 12 12:41:25 PM PDT 24 May 12 12:41:27 PM PDT 24 38479531 ps
T917 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4120645902 May 12 12:41:24 PM PDT 24 May 12 12:41:25 PM PDT 24 213221346 ps
T918 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2312247131 May 12 12:41:32 PM PDT 24 May 12 12:41:34 PM PDT 24 100065017 ps
T919 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3034680623 May 12 12:41:25 PM PDT 24 May 12 12:41:28 PM PDT 24 45057745 ps
T920 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3317965708 May 12 12:41:25 PM PDT 24 May 12 12:41:27 PM PDT 24 126762971 ps
T921 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3185824455 May 12 12:41:20 PM PDT 24 May 12 12:41:22 PM PDT 24 77489473 ps
T922 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.132551633 May 12 12:41:22 PM PDT 24 May 12 12:41:24 PM PDT 24 74929096 ps
T923 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2501849535 May 12 12:41:30 PM PDT 24 May 12 12:41:32 PM PDT 24 75036490 ps
T924 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.476760060 May 12 12:41:23 PM PDT 24 May 12 12:41:25 PM PDT 24 70651766 ps
T925 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1071709355 May 12 12:41:14 PM PDT 24 May 12 12:41:16 PM PDT 24 61649288 ps
T926 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.488659947 May 12 12:41:26 PM PDT 24 May 12 12:41:28 PM PDT 24 142650708 ps
T927 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.591763600 May 12 12:41:28 PM PDT 24 May 12 12:41:30 PM PDT 24 58738543 ps
T928 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.80455208 May 12 12:41:23 PM PDT 24 May 12 12:41:26 PM PDT 24 144830641 ps
T929 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1316220609 May 12 12:42:04 PM PDT 24 May 12 12:42:06 PM PDT 24 132320796 ps
T930 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3470348532 May 12 12:41:25 PM PDT 24 May 12 12:41:27 PM PDT 24 119603664 ps
T931 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3755637160 May 12 12:41:28 PM PDT 24 May 12 12:41:30 PM PDT 24 35211509 ps
T932 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.265628244 May 12 12:41:28 PM PDT 24 May 12 12:41:30 PM PDT 24 290215006 ps
T933 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2110622441 May 12 12:41:26 PM PDT 24 May 12 12:41:28 PM PDT 24 44379511 ps
T934 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3511892307 May 12 12:41:48 PM PDT 24 May 12 12:41:50 PM PDT 24 232255136 ps
T935 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1344452517 May 12 12:41:15 PM PDT 24 May 12 12:41:17 PM PDT 24 43565770 ps
T936 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.529161370 May 12 12:41:39 PM PDT 24 May 12 12:41:41 PM PDT 24 79383133 ps
T937 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2520509593 May 12 12:41:53 PM PDT 24 May 12 12:41:54 PM PDT 24 91667291 ps
T938 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3928211551 May 12 12:41:27 PM PDT 24 May 12 12:41:34 PM PDT 24 113964872 ps
T939 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2233607378 May 12 12:41:23 PM PDT 24 May 12 12:41:25 PM PDT 24 129217296 ps
T940 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1561939456 May 12 12:41:43 PM PDT 24 May 12 12:41:44 PM PDT 24 42212215 ps
T941 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3934656827 May 12 12:41:14 PM PDT 24 May 12 12:41:16 PM PDT 24 88834521 ps
T942 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2560863300 May 12 12:41:31 PM PDT 24 May 12 12:41:33 PM PDT 24 1107580171 ps
T943 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4172906688 May 12 12:41:43 PM PDT 24 May 12 12:41:44 PM PDT 24 61667077 ps

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.895053754
Short name T29
Test name
Test status
Simulation time 52545330641 ps
CPU time 595.75 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:54:25 PM PDT 24
Peak memory 198212 kb
Host smart-da164918-aa90-4d1a-b1fe-4c0ee7631ac2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=895053754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.895053754
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.4056964497
Short name T97
Test name
Test status
Simulation time 214999073 ps
CPU time 2.24 seconds
Started May 12 01:45:32 PM PDT 24
Finished May 12 01:45:34 PM PDT 24
Peak memory 198016 kb
Host smart-93d11658-689d-491a-89b6-127de201cc84
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056964497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.4056964497
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1147757848
Short name T23
Test name
Test status
Simulation time 118157035 ps
CPU time 1 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 214916 kb
Host smart-fd44f3b0-7798-4e86-8886-86ebdd912090
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147757848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1147757848
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3015033907
Short name T58
Test name
Test status
Simulation time 74745044 ps
CPU time 0.66 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 195100 kb
Host smart-5c786b31-2e01-4aa2-9be4-d7ac18180b30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015033907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3015033907
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.797524062
Short name T1
Test name
Test status
Simulation time 150954254 ps
CPU time 1.85 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:44:22 PM PDT 24
Peak memory 197908 kb
Host smart-418c675b-c511-45f0-9088-b51952c3909d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797524062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.797524062
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.269932638
Short name T45
Test name
Test status
Simulation time 362249126 ps
CPU time 1.47 seconds
Started May 12 12:41:02 PM PDT 24
Finished May 12 12:41:04 PM PDT 24
Peak memory 197556 kb
Host smart-29d4d831-ef90-4767-a3c6-0fbc8b2b264a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269932638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.269932638
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/17.gpio_alert_test.853929997
Short name T173
Test name
Test status
Simulation time 50406061 ps
CPU time 0.57 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:31 PM PDT 24
Peak memory 194060 kb
Host smart-994c0d5e-3d1c-4b32-b620-13471273cd89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853929997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.853929997
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.902847936
Short name T80
Test name
Test status
Simulation time 38641802 ps
CPU time 0.66 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:31 PM PDT 24
Peak memory 194072 kb
Host smart-c88207e6-2a95-41f9-b6ce-d83c8fe21099
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902847936 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.902847936
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1726257523
Short name T816
Test name
Test status
Simulation time 430516902 ps
CPU time 1.39 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:17 PM PDT 24
Peak memory 197600 kb
Host smart-1133e434-e124-4849-b51e-f45814aceb42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726257523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1726257523
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3506430736
Short name T25
Test name
Test status
Simulation time 92567381444 ps
CPU time 166.3 seconds
Started May 12 01:44:25 PM PDT 24
Finished May 12 01:47:12 PM PDT 24
Peak memory 198076 kb
Host smart-87359a84-e383-408b-8076-8e5fa606f952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506430736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3506430736
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.4250662373
Short name T62
Test name
Test status
Simulation time 180989637 ps
CPU time 0.85 seconds
Started May 12 12:41:11 PM PDT 24
Finished May 12 12:41:13 PM PDT 24
Peak memory 195488 kb
Host smart-5f1ea14b-53a1-487a-99f3-ba2935915e79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250662373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.4250662373
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3536464611
Short name T72
Test name
Test status
Simulation time 81498031 ps
CPU time 2.99 seconds
Started May 12 12:40:55 PM PDT 24
Finished May 12 12:40:58 PM PDT 24
Peak memory 197968 kb
Host smart-3fcc0e2e-2666-4d5b-be9b-8ed6c964cd35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536464611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3536464611
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1253549385
Short name T829
Test name
Test status
Simulation time 19366543 ps
CPU time 0.65 seconds
Started May 12 12:40:57 PM PDT 24
Finished May 12 12:40:59 PM PDT 24
Peak memory 194520 kb
Host smart-7ca9c2fd-24ac-49fb-b56f-8d8c91600b3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253549385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1253549385
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2873736495
Short name T721
Test name
Test status
Simulation time 18158567 ps
CPU time 0.65 seconds
Started May 12 12:41:03 PM PDT 24
Finished May 12 12:41:04 PM PDT 24
Peak memory 196480 kb
Host smart-1c7758f3-5b4f-4dcb-b0a0-33ebc63180d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873736495 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2873736495
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1788285120
Short name T828
Test name
Test status
Simulation time 47500978 ps
CPU time 0.58 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:21 PM PDT 24
Peak memory 193892 kb
Host smart-4104ef22-dd56-4293-9ad9-370735d3d178
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788285120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1788285120
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1662745689
Short name T742
Test name
Test status
Simulation time 65093007 ps
CPU time 0.58 seconds
Started May 12 12:41:08 PM PDT 24
Finished May 12 12:41:09 PM PDT 24
Peak memory 193232 kb
Host smart-e0eda794-fbd7-4c1e-a72c-5dbc071a1c13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662745689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1662745689
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2296985886
Short name T728
Test name
Test status
Simulation time 520832912 ps
CPU time 2.43 seconds
Started May 12 12:41:04 PM PDT 24
Finished May 12 12:41:07 PM PDT 24
Peak memory 197592 kb
Host smart-4c70dae1-abbd-4636-9d51-3e6de181d64e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296985886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2296985886
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2592197392
Short name T36
Test name
Test status
Simulation time 141911179 ps
CPU time 0.8 seconds
Started May 12 12:41:11 PM PDT 24
Finished May 12 12:41:13 PM PDT 24
Peak memory 197388 kb
Host smart-7d70d8e1-efc1-45c0-88d3-a500f22b426b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592197392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2592197392
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1794336353
Short name T69
Test name
Test status
Simulation time 46630340 ps
CPU time 0.73 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 195208 kb
Host smart-9ec88fe8-3180-4800-94f3-c145343af295
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794336353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1794336353
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2646353481
Short name T838
Test name
Test status
Simulation time 57737153 ps
CPU time 2.14 seconds
Started May 12 12:41:07 PM PDT 24
Finished May 12 12:41:09 PM PDT 24
Peak memory 196568 kb
Host smart-903379ac-47b2-4332-a0c5-29f3b3a14ac6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646353481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2646353481
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2575164199
Short name T93
Test name
Test status
Simulation time 48253929 ps
CPU time 0.66 seconds
Started May 12 12:41:21 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 194996 kb
Host smart-961ffd67-f7b9-4ca4-9b98-87c76eb31ee3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575164199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2575164199
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1560280057
Short name T761
Test name
Test status
Simulation time 21309331 ps
CPU time 0.72 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 197260 kb
Host smart-b508f303-623d-4d19-85b7-1850287606e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560280057 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1560280057
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2779202907
Short name T67
Test name
Test status
Simulation time 36935786 ps
CPU time 0.56 seconds
Started May 12 12:41:05 PM PDT 24
Finished May 12 12:41:06 PM PDT 24
Peak memory 194744 kb
Host smart-961e5365-7022-4fe6-99e1-06e666808676
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779202907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2779202907
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3379832673
Short name T803
Test name
Test status
Simulation time 42710408 ps
CPU time 0.57 seconds
Started May 12 12:40:57 PM PDT 24
Finished May 12 12:40:58 PM PDT 24
Peak memory 193848 kb
Host smart-8c7f4501-b95a-4eee-b147-84c02d817dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379832673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3379832673
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2080763010
Short name T815
Test name
Test status
Simulation time 58684709 ps
CPU time 0.66 seconds
Started May 12 12:40:57 PM PDT 24
Finished May 12 12:40:58 PM PDT 24
Peak memory 194020 kb
Host smart-4d064144-cac9-4061-a042-7c31cb88bd22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080763010 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2080763010
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.4215556055
Short name T734
Test name
Test status
Simulation time 1585155491 ps
CPU time 2.47 seconds
Started May 12 12:41:17 PM PDT 24
Finished May 12 12:41:21 PM PDT 24
Peak memory 197508 kb
Host smart-8dfb76ad-0f0f-43a3-b7e5-8e90ec0a74ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215556055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.4215556055
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2452885233
Short name T44
Test name
Test status
Simulation time 38005616 ps
CPU time 0.83 seconds
Started May 12 12:41:17 PM PDT 24
Finished May 12 12:41:19 PM PDT 24
Peak memory 197032 kb
Host smart-17c9ef9c-bb38-4c85-89c2-7b29e23d57c3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452885233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2452885233
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.777940481
Short name T768
Test name
Test status
Simulation time 58032954 ps
CPU time 0.88 seconds
Started May 12 12:41:22 PM PDT 24
Finished May 12 12:41:23 PM PDT 24
Peak memory 197424 kb
Host smart-1dda407a-dda0-48e5-a61f-8f5eac6dc0bd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777940481 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.777940481
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1516531289
Short name T73
Test name
Test status
Simulation time 19106187 ps
CPU time 0.58 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:27 PM PDT 24
Peak memory 194320 kb
Host smart-c45a2fb7-14e7-421f-8100-a3397832e6c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516531289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1516531289
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2935261977
Short name T807
Test name
Test status
Simulation time 18876872 ps
CPU time 0.63 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 193336 kb
Host smart-dac0a3d5-5ea3-4289-a004-3ff694cf1a36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935261977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2935261977
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.138684643
Short name T79
Test name
Test status
Simulation time 19312191 ps
CPU time 0.64 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:21 PM PDT 24
Peak memory 193964 kb
Host smart-2353e92e-b253-4e71-99a6-360fd013c749
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138684643 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.138684643
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4027121097
Short name T778
Test name
Test status
Simulation time 61424458 ps
CPU time 0.82 seconds
Started May 12 12:41:22 PM PDT 24
Finished May 12 12:41:24 PM PDT 24
Peak memory 197372 kb
Host smart-b1da30ad-879d-48d4-9ae8-01049a459645
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027121097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4027121097
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.458685386
Short name T34
Test name
Test status
Simulation time 278863528 ps
CPU time 1.17 seconds
Started May 12 12:41:18 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 197492 kb
Host smart-9f53e7e1-8ffc-443c-ad23-11a373a5c644
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458685386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.458685386
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.979503053
Short name T750
Test name
Test status
Simulation time 30543951 ps
CPU time 0.68 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 197092 kb
Host smart-6ea4d22b-e590-4ab3-8e22-cdf1973ec086
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979503053 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.979503053
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1304912167
Short name T94
Test name
Test status
Simulation time 13009097 ps
CPU time 0.61 seconds
Started May 12 12:41:11 PM PDT 24
Finished May 12 12:41:13 PM PDT 24
Peak memory 194140 kb
Host smart-181da76c-c923-4b9d-9a3d-2a65ca55e1f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304912167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1304912167
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3741651361
Short name T814
Test name
Test status
Simulation time 44151725 ps
CPU time 0.66 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 193836 kb
Host smart-ba365037-b523-4acc-8204-b9426e93650f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741651361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3741651361
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.775408478
Short name T795
Test name
Test status
Simulation time 37939169 ps
CPU time 0.82 seconds
Started May 12 12:41:42 PM PDT 24
Finished May 12 12:41:43 PM PDT 24
Peak memory 195788 kb
Host smart-4b3fa781-b30e-46fd-8ddd-ee7af3b06a27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775408478 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.775408478
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2920202916
Short name T808
Test name
Test status
Simulation time 184070036 ps
CPU time 2.59 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 197532 kb
Host smart-fe4e5d65-a428-4af9-b7b5-b92c6857063a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920202916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2920202916
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.99718996
Short name T48
Test name
Test status
Simulation time 215162015 ps
CPU time 1.44 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:19 PM PDT 24
Peak memory 197472 kb
Host smart-5456f279-70a3-44b5-ae1c-99237c54008c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99718996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.gpio_tl_intg_err.99718996
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3955073037
Short name T820
Test name
Test status
Simulation time 119065321 ps
CPU time 1.01 seconds
Started May 12 12:41:38 PM PDT 24
Finished May 12 12:41:40 PM PDT 24
Peak memory 197480 kb
Host smart-8fabff39-e1e3-4f93-8ee6-f3f2b8ef41ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955073037 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3955073037
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3098041393
Short name T769
Test name
Test status
Simulation time 21627076 ps
CPU time 0.59 seconds
Started May 12 12:41:13 PM PDT 24
Finished May 12 12:41:14 PM PDT 24
Peak memory 193872 kb
Host smart-2df1a47d-5845-4cb4-a01e-94f4ad8264a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098041393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3098041393
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.96718784
Short name T819
Test name
Test status
Simulation time 43372905 ps
CPU time 0.56 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 193152 kb
Host smart-2b577f33-acb4-483b-a74f-a18e95edde12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96718784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.96718784
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3013298878
Short name T65
Test name
Test status
Simulation time 22377425 ps
CPU time 0.88 seconds
Started May 12 12:41:42 PM PDT 24
Finished May 12 12:41:43 PM PDT 24
Peak memory 196044 kb
Host smart-8a00fef3-ca58-4683-a964-e366bb659f64
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013298878 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3013298878
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2662024749
Short name T720
Test name
Test status
Simulation time 82326046 ps
CPU time 1.47 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 197548 kb
Host smart-b61a4bfc-db37-4ee9-b487-cb8b4460417d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662024749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2662024749
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3863861108
Short name T836
Test name
Test status
Simulation time 71552508 ps
CPU time 0.89 seconds
Started May 12 12:41:46 PM PDT 24
Finished May 12 12:41:47 PM PDT 24
Peak memory 197504 kb
Host smart-b7b535fd-2022-462b-bc7c-6080c6aec198
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863861108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3863861108
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.846978229
Short name T739
Test name
Test status
Simulation time 73638320 ps
CPU time 0.92 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 197564 kb
Host smart-5ebe15db-f539-4790-87f0-9d1d33cd5e87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846978229 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.846978229
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.70322200
Short name T727
Test name
Test status
Simulation time 11583308 ps
CPU time 0.61 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 193980 kb
Host smart-9dd062f6-7b6e-4085-965c-3ace0fe0f5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70322200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.70322200
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1608986328
Short name T798
Test name
Test status
Simulation time 155726048 ps
CPU time 0.82 seconds
Started May 12 12:41:34 PM PDT 24
Finished May 12 12:41:35 PM PDT 24
Peak memory 195668 kb
Host smart-d2f60186-ee24-451b-b3e8-f5a465780584
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608986328 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1608986328
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1823188050
Short name T811
Test name
Test status
Simulation time 37920311 ps
CPU time 1.9 seconds
Started May 12 12:41:21 PM PDT 24
Finished May 12 12:41:24 PM PDT 24
Peak memory 197572 kb
Host smart-5e446d8d-94e3-433b-a192-85d002fca0f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823188050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1823188050
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.534664590
Short name T759
Test name
Test status
Simulation time 166316688 ps
CPU time 0.91 seconds
Started May 12 12:41:11 PM PDT 24
Finished May 12 12:41:13 PM PDT 24
Peak memory 197408 kb
Host smart-253c6084-cdfd-4951-9f19-54f5b4f85ef6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534664590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.534664590
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1150397571
Short name T771
Test name
Test status
Simulation time 24375687 ps
CPU time 1.2 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 197588 kb
Host smart-dca9b97f-8155-48e0-b0b6-31792f762a23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150397571 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1150397571
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1112582214
Short name T774
Test name
Test status
Simulation time 23717209 ps
CPU time 0.57 seconds
Started May 12 12:41:17 PM PDT 24
Finished May 12 12:41:19 PM PDT 24
Peak memory 194024 kb
Host smart-a96f5a02-b17e-4b35-bc6c-4991d16c9486
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112582214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1112582214
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.510901298
Short name T746
Test name
Test status
Simulation time 22962850 ps
CPU time 0.63 seconds
Started May 12 12:41:47 PM PDT 24
Finished May 12 12:41:48 PM PDT 24
Peak memory 193936 kb
Host smart-9e92db8b-01fa-4f4b-997f-168696e113e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510901298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.510901298
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1993307561
Short name T60
Test name
Test status
Simulation time 59077190 ps
CPU time 0.76 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:16 PM PDT 24
Peak memory 195684 kb
Host smart-dc03df55-e245-49ce-a941-73d46fec0b7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993307561 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1993307561
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.502480968
Short name T822
Test name
Test status
Simulation time 42008475 ps
CPU time 1.79 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 197528 kb
Host smart-f08e285b-e655-4bcd-ba35-3e48fa24d0d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502480968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.502480968
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1601787393
Short name T43
Test name
Test status
Simulation time 184526253 ps
CPU time 1.31 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:36 PM PDT 24
Peak memory 197612 kb
Host smart-3039d8bc-21bd-4c9a-8118-7053a42493a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601787393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1601787393
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3796930225
Short name T765
Test name
Test status
Simulation time 117398416 ps
CPU time 0.91 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:27 PM PDT 24
Peak memory 197476 kb
Host smart-ec47f7b2-da42-4f63-8b79-64d0e93b80e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796930225 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3796930225
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.472856626
Short name T64
Test name
Test status
Simulation time 50806397 ps
CPU time 0.62 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:15 PM PDT 24
Peak memory 194128 kb
Host smart-9130636e-a63e-461f-a239-955404c31122
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472856626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.472856626
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3959887625
Short name T804
Test name
Test status
Simulation time 11168050 ps
CPU time 0.56 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 193172 kb
Host smart-2c145e7d-cea5-4349-a93f-93d07c7e6b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959887625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3959887625
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1085162082
Short name T77
Test name
Test status
Simulation time 35862874 ps
CPU time 0.74 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:24 PM PDT 24
Peak memory 195692 kb
Host smart-21d03b0d-61c6-4808-91d5-3f18d5ec03c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085162082 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1085162082
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2385665348
Short name T832
Test name
Test status
Simulation time 78098653 ps
CPU time 1.14 seconds
Started May 12 12:41:22 PM PDT 24
Finished May 12 12:41:24 PM PDT 24
Peak memory 197548 kb
Host smart-9e42d671-a4fb-495d-a730-08e48f31a683
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385665348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2385665348
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1556682950
Short name T757
Test name
Test status
Simulation time 362956155 ps
CPU time 0.83 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 196736 kb
Host smart-18bff115-c805-47d4-b0b1-3ca6cf33abe8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556682950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1556682950
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.997903029
Short name T802
Test name
Test status
Simulation time 57698907 ps
CPU time 0.66 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:31 PM PDT 24
Peak memory 196488 kb
Host smart-d03f9bd9-efa0-4772-955b-6228a0ffb33e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997903029 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.997903029
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2230831523
Short name T794
Test name
Test status
Simulation time 85465971 ps
CPU time 0.62 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 194552 kb
Host smart-3020c6ef-869c-4d25-9193-8e50cc7eb8db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230831523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2230831523
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1591975711
Short name T747
Test name
Test status
Simulation time 51849696 ps
CPU time 0.61 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:16 PM PDT 24
Peak memory 193904 kb
Host smart-ee42cb09-bd52-4657-a3c1-0ce76deae65c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591975711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1591975711
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1907926692
Short name T81
Test name
Test status
Simulation time 68503092 ps
CPU time 0.66 seconds
Started May 12 12:41:09 PM PDT 24
Finished May 12 12:41:10 PM PDT 24
Peak memory 194856 kb
Host smart-6343d299-6571-4af8-8b40-f2d0196b9592
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907926692 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1907926692
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1415301937
Short name T788
Test name
Test status
Simulation time 430247045 ps
CPU time 2.29 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 197584 kb
Host smart-a0bc9177-ae0a-4d07-b374-b6bc634f2f56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415301937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1415301937
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.500608184
Short name T760
Test name
Test status
Simulation time 43849429 ps
CPU time 0.86 seconds
Started May 12 12:41:54 PM PDT 24
Finished May 12 12:41:56 PM PDT 24
Peak memory 196876 kb
Host smart-c7e75e1c-5703-4def-ad51-f5933990a9b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500608184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.500608184
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.336470731
Short name T756
Test name
Test status
Simulation time 115889493 ps
CPU time 1.5 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 197596 kb
Host smart-6a5aa70a-cec0-4525-bb17-277e54df41e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336470731 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.336470731
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2527293301
Short name T770
Test name
Test status
Simulation time 17449736 ps
CPU time 0.66 seconds
Started May 12 12:41:47 PM PDT 24
Finished May 12 12:41:48 PM PDT 24
Peak memory 194400 kb
Host smart-ebe66bda-c02f-4ff2-b212-45ba8cfe2af9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527293301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2527293301
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2814857245
Short name T724
Test name
Test status
Simulation time 16243185 ps
CPU time 0.56 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 193156 kb
Host smart-0b3aee0c-f504-466a-b3d6-66f74fdef2c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814857245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2814857245
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.673805614
Short name T76
Test name
Test status
Simulation time 23014453 ps
CPU time 0.69 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:21 PM PDT 24
Peak memory 194636 kb
Host smart-e6e4c908-a8b1-4970-9c01-65aeb6086093
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673805614 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.673805614
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1080064044
Short name T743
Test name
Test status
Simulation time 93725214 ps
CPU time 1.24 seconds
Started May 12 12:41:31 PM PDT 24
Finished May 12 12:41:33 PM PDT 24
Peak memory 197576 kb
Host smart-5ed9eb8d-38cc-4500-bcf7-bf2bb8511aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080064044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1080064044
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3783635236
Short name T830
Test name
Test status
Simulation time 65643779 ps
CPU time 0.88 seconds
Started May 12 12:41:56 PM PDT 24
Finished May 12 12:41:57 PM PDT 24
Peak memory 196808 kb
Host smart-12154505-54a5-470f-8c92-9372d14b360a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783635236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3783635236
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3106955839
Short name T789
Test name
Test status
Simulation time 21497218 ps
CPU time 0.68 seconds
Started May 12 12:41:47 PM PDT 24
Finished May 12 12:41:48 PM PDT 24
Peak memory 196520 kb
Host smart-66d77f11-b890-4e81-b143-28d2c288ced8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106955839 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3106955839
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4048192908
Short name T63
Test name
Test status
Simulation time 11709313 ps
CPU time 0.6 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:15 PM PDT 24
Peak memory 194216 kb
Host smart-0b391997-cca9-4332-b793-d09b313458c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048192908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.4048192908
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3148265356
Short name T839
Test name
Test status
Simulation time 21280751 ps
CPU time 0.6 seconds
Started May 12 12:41:48 PM PDT 24
Finished May 12 12:41:49 PM PDT 24
Peak memory 193868 kb
Host smart-8ed8e70b-8e1b-4537-ae3d-980f3c26902b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148265356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3148265356
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.4137338144
Short name T824
Test name
Test status
Simulation time 45339871 ps
CPU time 0.82 seconds
Started May 12 12:41:55 PM PDT 24
Finished May 12 12:41:56 PM PDT 24
Peak memory 195708 kb
Host smart-a7a0b742-85a9-4826-813d-c70cc2459c6d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137338144 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.4137338144
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3351838624
Short name T787
Test name
Test status
Simulation time 66307823 ps
CPU time 1.4 seconds
Started May 12 12:41:21 PM PDT 24
Finished May 12 12:41:23 PM PDT 24
Peak memory 197548 kb
Host smart-8068344c-cad5-4ff3-9db2-df25dfa5768c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351838624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3351838624
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1975151638
Short name T49
Test name
Test status
Simulation time 87579413 ps
CPU time 0.86 seconds
Started May 12 12:42:01 PM PDT 24
Finished May 12 12:42:02 PM PDT 24
Peak memory 197464 kb
Host smart-11b2f396-dd3d-4ca6-a085-dedca88231e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975151638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1975151638
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3877891600
Short name T738
Test name
Test status
Simulation time 33406693 ps
CPU time 0.96 seconds
Started May 12 12:41:46 PM PDT 24
Finished May 12 12:41:48 PM PDT 24
Peak memory 197484 kb
Host smart-5a543f19-082c-4a1f-9eae-9f3066e9a8fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877891600 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3877891600
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4106083863
Short name T823
Test name
Test status
Simulation time 57463615 ps
CPU time 0.57 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:31 PM PDT 24
Peak memory 193644 kb
Host smart-d1d252d3-4b9e-40ec-8840-7ea5d1b6b2ef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106083863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4106083863
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3252962861
Short name T827
Test name
Test status
Simulation time 17137183 ps
CPU time 0.57 seconds
Started May 12 12:41:48 PM PDT 24
Finished May 12 12:41:49 PM PDT 24
Peak memory 193176 kb
Host smart-49a66a65-9c59-4129-a96e-f90f83e0598c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252962861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3252962861
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.4146474351
Short name T817
Test name
Test status
Simulation time 28119431 ps
CPU time 0.74 seconds
Started May 12 12:42:05 PM PDT 24
Finished May 12 12:42:06 PM PDT 24
Peak memory 195296 kb
Host smart-93bd547c-0f88-4a91-bc3d-1e3d01f81964
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146474351 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.4146474351
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1978046560
Short name T813
Test name
Test status
Simulation time 29214265 ps
CPU time 1.5 seconds
Started May 12 12:41:47 PM PDT 24
Finished May 12 12:41:49 PM PDT 24
Peak memory 197612 kb
Host smart-cf81b124-e15a-4f27-aff0-e7585916efe1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978046560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1978046560
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.4121048440
Short name T835
Test name
Test status
Simulation time 345655491 ps
CPU time 1.41 seconds
Started May 12 12:41:52 PM PDT 24
Finished May 12 12:41:54 PM PDT 24
Peak memory 197600 kb
Host smart-d13d40c9-9f2d-4340-98a3-3ab96a338068
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121048440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.4121048440
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1070303645
Short name T70
Test name
Test status
Simulation time 58993758 ps
CPU time 0.81 seconds
Started May 12 12:41:12 PM PDT 24
Finished May 12 12:41:13 PM PDT 24
Peak memory 196056 kb
Host smart-0ba74152-3671-494a-b4ae-e22aed90f4cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070303645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1070303645
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.665764353
Short name T801
Test name
Test status
Simulation time 318832671 ps
CPU time 1.45 seconds
Started May 12 12:41:18 PM PDT 24
Finished May 12 12:41:21 PM PDT 24
Peak memory 197484 kb
Host smart-8ef0c376-7a92-4ffb-a61d-2d924299fb67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665764353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.665764353
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.802758705
Short name T740
Test name
Test status
Simulation time 33735510 ps
CPU time 0.67 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 194464 kb
Host smart-a6596541-1e36-4dde-909b-26cdba5c9963
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802758705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.802758705
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.291045259
Short name T736
Test name
Test status
Simulation time 108191458 ps
CPU time 0.88 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:16 PM PDT 24
Peak memory 197448 kb
Host smart-f33f7a4f-bd8e-4b4b-a537-8e1418a9ff16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291045259 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.291045259
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.3906701045
Short name T61
Test name
Test status
Simulation time 42109236 ps
CPU time 0.56 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:30 PM PDT 24
Peak memory 192852 kb
Host smart-a529e8a2-e10a-49a3-bdb6-18a0ab81fd0d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906701045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.3906701045
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.609092416
Short name T783
Test name
Test status
Simulation time 12375227 ps
CPU time 0.68 seconds
Started May 12 12:41:11 PM PDT 24
Finished May 12 12:41:13 PM PDT 24
Peak memory 192448 kb
Host smart-041ecab6-8172-4200-8414-bdad658bb2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609092416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.609092416
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2838202132
Short name T791
Test name
Test status
Simulation time 34578778 ps
CPU time 0.81 seconds
Started May 12 12:40:55 PM PDT 24
Finished May 12 12:40:56 PM PDT 24
Peak memory 195704 kb
Host smart-6884b96c-e3d8-4325-a689-ede3a0e5f70e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838202132 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2838202132
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3416011019
Short name T737
Test name
Test status
Simulation time 166585885 ps
CPU time 1.63 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 197612 kb
Host smart-a86d1add-758f-42a0-bb25-efeeab571bbd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416011019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3416011019
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.4121517947
Short name T826
Test name
Test status
Simulation time 25730180 ps
CPU time 0.59 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:30 PM PDT 24
Peak memory 193836 kb
Host smart-b5e2c823-5b04-402b-be0f-ef78ba7b707c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121517947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.4121517947
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.4076087396
Short name T764
Test name
Test status
Simulation time 67202780 ps
CPU time 0.61 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 193288 kb
Host smart-0809e950-910f-40e2-9794-32a40f7e4eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076087396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.4076087396
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2179486345
Short name T779
Test name
Test status
Simulation time 20671969 ps
CPU time 0.58 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:21 PM PDT 24
Peak memory 193140 kb
Host smart-0b51f481-5b04-45ba-99bd-77e7816f7f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179486345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2179486345
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1731946735
Short name T806
Test name
Test status
Simulation time 15190763 ps
CPU time 0.57 seconds
Started May 12 12:41:17 PM PDT 24
Finished May 12 12:41:19 PM PDT 24
Peak memory 193160 kb
Host smart-7a2cbcf8-7122-49be-b77b-bccfadfc9d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731946735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1731946735
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.313858600
Short name T775
Test name
Test status
Simulation time 41326196 ps
CPU time 0.56 seconds
Started May 12 12:41:33 PM PDT 24
Finished May 12 12:41:34 PM PDT 24
Peak memory 193872 kb
Host smart-19f44a88-5439-4ca5-a44b-20b69f793eea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313858600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.313858600
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2136376694
Short name T755
Test name
Test status
Simulation time 48926319 ps
CPU time 0.62 seconds
Started May 12 12:41:13 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 193164 kb
Host smart-3139627a-6c8c-4203-a579-1b3ea9909ac0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136376694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2136376694
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2569260743
Short name T754
Test name
Test status
Simulation time 30272638 ps
CPU time 0.6 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 193260 kb
Host smart-0b4b90e7-3643-4eef-821b-d7979a996403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569260743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2569260743
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2285359227
Short name T800
Test name
Test status
Simulation time 13988229 ps
CPU time 0.61 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 193204 kb
Host smart-0cea9515-c022-4df2-a856-e01b2426877a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285359227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2285359227
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.10764222
Short name T726
Test name
Test status
Simulation time 14849395 ps
CPU time 0.66 seconds
Started May 12 12:41:22 PM PDT 24
Finished May 12 12:41:23 PM PDT 24
Peak memory 193244 kb
Host smart-41b5ec2e-e9d4-4527-9e0d-63b1e8ee753a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10764222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.10764222
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2946061329
Short name T772
Test name
Test status
Simulation time 17472404 ps
CPU time 0.62 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:27 PM PDT 24
Peak memory 193140 kb
Host smart-1ee21958-4eb8-42b5-9dc1-ae962bd4fbcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946061329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2946061329
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1697175482
Short name T66
Test name
Test status
Simulation time 50760985 ps
CPU time 0.87 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:15 PM PDT 24
Peak memory 195756 kb
Host smart-0eb8fb8a-815c-47a4-aa3d-e2255e7e79ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697175482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1697175482
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.648362393
Short name T748
Test name
Test status
Simulation time 81845528 ps
CPU time 2.93 seconds
Started May 12 12:41:38 PM PDT 24
Finished May 12 12:41:41 PM PDT 24
Peak memory 196296 kb
Host smart-752e35f5-0126-4745-9cc9-57e2b6b53b36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648362393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.648362393
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3035729485
Short name T763
Test name
Test status
Simulation time 14599199 ps
CPU time 0.65 seconds
Started May 12 12:41:11 PM PDT 24
Finished May 12 12:41:12 PM PDT 24
Peak memory 193808 kb
Host smart-fba60819-b0ab-4306-8481-8eabcf9a6de6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035729485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3035729485
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1480457265
Short name T735
Test name
Test status
Simulation time 48114404 ps
CPU time 0.76 seconds
Started May 12 12:41:11 PM PDT 24
Finished May 12 12:41:13 PM PDT 24
Peak memory 197416 kb
Host smart-72437825-2539-4cc7-881e-8899076bc1aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480457265 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1480457265
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3167855843
Short name T74
Test name
Test status
Simulation time 47167854 ps
CPU time 0.62 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:17 PM PDT 24
Peak memory 194996 kb
Host smart-5a73c223-fea0-46da-ae83-3d51f5a152e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167855843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3167855843
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2064192963
Short name T725
Test name
Test status
Simulation time 11621016 ps
CPU time 0.6 seconds
Started May 12 12:41:17 PM PDT 24
Finished May 12 12:41:19 PM PDT 24
Peak memory 193268 kb
Host smart-cb68cceb-2a31-47b5-8338-9751f67575f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064192963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2064192963
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.1883949641
Short name T805
Test name
Test status
Simulation time 16430167 ps
CPU time 0.84 seconds
Started May 12 12:41:13 PM PDT 24
Finished May 12 12:41:14 PM PDT 24
Peak memory 196356 kb
Host smart-1bb5e99d-6a20-40ed-a530-33ff4513ac7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883949641 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.1883949641
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.696905476
Short name T719
Test name
Test status
Simulation time 145246067 ps
CPU time 3.03 seconds
Started May 12 12:41:03 PM PDT 24
Finished May 12 12:41:06 PM PDT 24
Peak memory 197572 kb
Host smart-64d5c9a0-1ed6-4330-a900-7593a3d8ac93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696905476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.696905476
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1565357994
Short name T723
Test name
Test status
Simulation time 16025976 ps
CPU time 0.63 seconds
Started May 12 12:41:20 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 192448 kb
Host smart-ef3bbb8f-ac0d-4205-821c-737fc108f01f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565357994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1565357994
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3124405602
Short name T784
Test name
Test status
Simulation time 14592360 ps
CPU time 0.57 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:30 PM PDT 24
Peak memory 193196 kb
Host smart-f020c109-ef07-449b-8685-b2ceb9e54e04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124405602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3124405602
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2227192108
Short name T833
Test name
Test status
Simulation time 12402961 ps
CPU time 0.58 seconds
Started May 12 12:41:13 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 193148 kb
Host smart-75f0abf9-3fb2-4d63-97e7-26905840d6f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227192108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2227192108
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1352091578
Short name T722
Test name
Test status
Simulation time 12120728 ps
CPU time 0.59 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 193844 kb
Host smart-8d7e24aa-3534-4953-8771-037f08054a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352091578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1352091578
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2289515413
Short name T790
Test name
Test status
Simulation time 117458670 ps
CPU time 0.58 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 193860 kb
Host smart-857e54a2-3aa1-43a6-b6aa-f81d6e36d832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289515413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2289515413
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.739224773
Short name T796
Test name
Test status
Simulation time 43843899 ps
CPU time 0.57 seconds
Started May 12 12:41:30 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 193204 kb
Host smart-6f2b3b12-f792-45ff-819c-28505eee25d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739224773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.739224773
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3253511209
Short name T818
Test name
Test status
Simulation time 12941321 ps
CPU time 0.61 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:24 PM PDT 24
Peak memory 193676 kb
Host smart-a183ce7e-a7db-4c8c-97c1-dc9d715ceecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253511209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3253511209
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.543491504
Short name T729
Test name
Test status
Simulation time 14283889 ps
CPU time 0.56 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 193812 kb
Host smart-801ce527-e9d6-4354-b9fc-b91a0543978c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543491504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.543491504
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.485278825
Short name T777
Test name
Test status
Simulation time 16024305 ps
CPU time 0.6 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 193240 kb
Host smart-6a2f9921-f5ba-4b2e-be0c-77b1f9550177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485278825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.485278825
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1503584626
Short name T744
Test name
Test status
Simulation time 15027755 ps
CPU time 0.61 seconds
Started May 12 12:41:20 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 193840 kb
Host smart-4036791e-a0eb-43f7-b940-db0e007a4646
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503584626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1503584626
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2220237293
Short name T59
Test name
Test status
Simulation time 17399249 ps
CPU time 0.66 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 193940 kb
Host smart-8f937810-cb56-4052-91ca-1d1a0cfc52f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220237293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2220237293
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2201400561
Short name T745
Test name
Test status
Simulation time 994649818 ps
CPU time 3.17 seconds
Started May 12 12:41:32 PM PDT 24
Finished May 12 12:41:36 PM PDT 24
Peak memory 196604 kb
Host smart-458ed605-27ab-442d-9e96-0a14c7e2ddb3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201400561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2201400561
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2218940890
Short name T825
Test name
Test status
Simulation time 15210182 ps
CPU time 0.69 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:15 PM PDT 24
Peak memory 193380 kb
Host smart-99ee1f85-e9bf-42c1-848e-312b28576265
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218940890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2218940890
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2107647832
Short name T792
Test name
Test status
Simulation time 135188777 ps
CPU time 1.65 seconds
Started May 12 12:41:03 PM PDT 24
Finished May 12 12:41:06 PM PDT 24
Peak memory 197624 kb
Host smart-e43b8445-6fbd-4498-a0cb-9c0aefaaf2e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107647832 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2107647832
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.130200318
Short name T773
Test name
Test status
Simulation time 38195695 ps
CPU time 0.58 seconds
Started May 12 12:41:10 PM PDT 24
Finished May 12 12:41:11 PM PDT 24
Peak memory 193988 kb
Host smart-d5e195fd-5992-41b2-8d6b-e75076e9577a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130200318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.130200318
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2658412206
Short name T749
Test name
Test status
Simulation time 67904209 ps
CPU time 0.57 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:21 PM PDT 24
Peak memory 193264 kb
Host smart-66a1abba-88a3-409f-b8f3-4e34debb973d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658412206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2658412206
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2085166202
Short name T793
Test name
Test status
Simulation time 39435937 ps
CPU time 0.81 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 195660 kb
Host smart-8de0deed-75db-4b28-99a1-c9704a21e070
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085166202 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2085166202
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2010763265
Short name T782
Test name
Test status
Simulation time 237590045 ps
CPU time 1.49 seconds
Started May 12 12:41:12 PM PDT 24
Finished May 12 12:41:14 PM PDT 24
Peak memory 197568 kb
Host smart-2e77ffe6-3b7e-4d78-af4e-36d2f46a5a67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010763265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2010763265
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1127645316
Short name T42
Test name
Test status
Simulation time 769779673 ps
CPU time 1.47 seconds
Started May 12 12:41:03 PM PDT 24
Finished May 12 12:41:06 PM PDT 24
Peak memory 197540 kb
Host smart-2e4108e4-da2b-46ba-a6b2-d034ed08443b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127645316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1127645316
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1047844749
Short name T767
Test name
Test status
Simulation time 42899917 ps
CPU time 0.64 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 193192 kb
Host smart-9be32212-e10e-4116-8245-20ae098b57c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047844749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1047844749
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2121639858
Short name T831
Test name
Test status
Simulation time 19278768 ps
CPU time 0.57 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:15 PM PDT 24
Peak memory 193104 kb
Host smart-22ecd621-3e95-4bff-a9df-be90dbc898f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121639858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2121639858
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1037607133
Short name T732
Test name
Test status
Simulation time 17522755 ps
CPU time 0.57 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 193220 kb
Host smart-f5195ba4-22ef-411b-be21-9b6fe1a38a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037607133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1037607133
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2496121199
Short name T799
Test name
Test status
Simulation time 64166902 ps
CPU time 0.6 seconds
Started May 12 12:41:20 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 193256 kb
Host smart-497790d2-5eb8-459e-8f58-b78bb0588a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496121199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2496121199
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.480133131
Short name T776
Test name
Test status
Simulation time 24971023 ps
CPU time 0.58 seconds
Started May 12 12:41:31 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 193116 kb
Host smart-4d2102cb-9962-4a2a-a18d-6673689b085f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480133131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.480133131
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2429956001
Short name T731
Test name
Test status
Simulation time 155093143 ps
CPU time 0.63 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 193296 kb
Host smart-33cf970e-f0f9-4237-b15e-92c9143a18ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429956001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2429956001
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3363944170
Short name T842
Test name
Test status
Simulation time 14113242 ps
CPU time 0.61 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 193256 kb
Host smart-4b819a84-6d6f-4519-b170-69b7285c9065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363944170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3363944170
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1820217294
Short name T837
Test name
Test status
Simulation time 41241140 ps
CPU time 0.61 seconds
Started May 12 12:41:30 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 193984 kb
Host smart-0d392565-65db-4f1e-81bc-0e2d3849a367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820217294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1820217294
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2434976765
Short name T758
Test name
Test status
Simulation time 14824298 ps
CPU time 0.61 seconds
Started May 12 12:41:37 PM PDT 24
Finished May 12 12:41:38 PM PDT 24
Peak memory 193844 kb
Host smart-b23441de-b603-4bbe-92ae-2c4a2aad2bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434976765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2434976765
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3378976303
Short name T786
Test name
Test status
Simulation time 47537438 ps
CPU time 0.65 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 193252 kb
Host smart-34299cfe-4dca-4630-b252-fdefef50a7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378976303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3378976303
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3237550029
Short name T753
Test name
Test status
Simulation time 24729679 ps
CPU time 1.06 seconds
Started May 12 12:41:38 PM PDT 24
Finished May 12 12:41:39 PM PDT 24
Peak memory 197564 kb
Host smart-3e8f4d33-a578-4da6-b289-f5954010fb10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237550029 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3237550029
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3195662020
Short name T71
Test name
Test status
Simulation time 41748065 ps
CPU time 0.6 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 194236 kb
Host smart-dd26c110-68bb-468c-a799-05e1761f337b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195662020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3195662020
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.879251069
Short name T780
Test name
Test status
Simulation time 81732205 ps
CPU time 0.58 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:17 PM PDT 24
Peak memory 193208 kb
Host smart-e50312e5-4d04-44d4-84c0-31523b936eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879251069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.879251069
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2946933671
Short name T82
Test name
Test status
Simulation time 16429583 ps
CPU time 0.74 seconds
Started May 12 12:41:46 PM PDT 24
Finished May 12 12:41:47 PM PDT 24
Peak memory 196476 kb
Host smart-7e77276d-48da-4c9c-ba5a-15e830e1b5a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946933671 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2946933671
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2667047570
Short name T843
Test name
Test status
Simulation time 71748836 ps
CPU time 1.58 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 197548 kb
Host smart-b6fdc54f-b5c8-49d9-8bc0-2c81ed31e5da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667047570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2667047570
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.807081376
Short name T46
Test name
Test status
Simulation time 108062216 ps
CPU time 1.59 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 197992 kb
Host smart-60041099-01cc-4bed-a947-4c353baefce4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807081376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.807081376
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.1024161678
Short name T741
Test name
Test status
Simulation time 72406023 ps
CPU time 1.02 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:17 PM PDT 24
Peak memory 197616 kb
Host smart-1a8287d4-786c-416e-a671-0cc1cc6c3784
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024161678 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.1024161678
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2508764458
Short name T766
Test name
Test status
Simulation time 13147143 ps
CPU time 0.6 seconds
Started May 12 12:41:46 PM PDT 24
Finished May 12 12:41:48 PM PDT 24
Peak memory 194336 kb
Host smart-3456bad5-0a2a-43a7-8a91-b46b7f27064e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508764458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2508764458
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.4243845600
Short name T752
Test name
Test status
Simulation time 12727541 ps
CPU time 0.58 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:27 PM PDT 24
Peak memory 193220 kb
Host smart-6a099cf2-aa59-453e-8142-204925f4cd52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243845600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.4243845600
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1185326797
Short name T83
Test name
Test status
Simulation time 98875329 ps
CPU time 0.68 seconds
Started May 12 12:41:17 PM PDT 24
Finished May 12 12:41:19 PM PDT 24
Peak memory 194420 kb
Host smart-9aa3931a-69bd-4a53-9bb7-fc21793395f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185326797 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1185326797
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1802453007
Short name T812
Test name
Test status
Simulation time 128784037 ps
CPU time 1.08 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:16 PM PDT 24
Peak memory 197564 kb
Host smart-f8f5e5c4-6325-415f-87ee-48612a88198b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802453007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1802453007
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.649501494
Short name T810
Test name
Test status
Simulation time 39226661 ps
CPU time 0.84 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 196760 kb
Host smart-ac17d23c-071d-4f94-ae14-9882ea6331c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649501494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.649501494
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2140033692
Short name T762
Test name
Test status
Simulation time 41458967 ps
CPU time 1 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:19 PM PDT 24
Peak memory 197492 kb
Host smart-e8f35fc1-9106-48ff-8e5f-a897495f5f7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140033692 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2140033692
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.673810429
Short name T840
Test name
Test status
Simulation time 14735938 ps
CPU time 0.58 seconds
Started May 12 12:41:38 PM PDT 24
Finished May 12 12:41:39 PM PDT 24
Peak memory 194108 kb
Host smart-278e3f92-3cb1-4a89-a222-f4505fbd8185
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673810429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.673810429
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.982508821
Short name T733
Test name
Test status
Simulation time 15349840 ps
CPU time 0.64 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 193232 kb
Host smart-ca4d477e-ec57-472d-ad1b-28fe35bab779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982508821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.982508821
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1397102438
Short name T781
Test name
Test status
Simulation time 21029481 ps
CPU time 0.63 seconds
Started May 12 12:41:21 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 195152 kb
Host smart-fcae58e0-8ef1-41a4-8589-37558647be0b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397102438 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1397102438
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1971194769
Short name T841
Test name
Test status
Simulation time 32259119 ps
CPU time 0.92 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:17 PM PDT 24
Peak memory 197392 kb
Host smart-b917d0b7-9ba2-47fb-957f-4f8de13eb4a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971194769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1971194769
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.4035294060
Short name T47
Test name
Test status
Simulation time 42904115 ps
CPU time 0.87 seconds
Started May 12 12:41:43 PM PDT 24
Finished May 12 12:41:44 PM PDT 24
Peak memory 196652 kb
Host smart-cf23d926-0a71-4754-a58b-5637aa35d85b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035294060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.4035294060
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1203566195
Short name T809
Test name
Test status
Simulation time 30445966 ps
CPU time 0.93 seconds
Started May 12 12:41:11 PM PDT 24
Finished May 12 12:41:13 PM PDT 24
Peak memory 196668 kb
Host smart-180efc29-41ef-4eb7-84f7-6f4ca58df51b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203566195 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1203566195
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.4021077942
Short name T68
Test name
Test status
Simulation time 53333284 ps
CPU time 0.66 seconds
Started May 12 12:41:17 PM PDT 24
Finished May 12 12:41:19 PM PDT 24
Peak memory 193672 kb
Host smart-45debb99-ce9b-490d-858c-3f24ca4de6e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021077942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.4021077942
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3163493756
Short name T797
Test name
Test status
Simulation time 36405467 ps
CPU time 0.55 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 193232 kb
Host smart-39c96bc1-e2a9-45a4-938d-c4919fa7886b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163493756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3163493756
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2152521624
Short name T834
Test name
Test status
Simulation time 29005416 ps
CPU time 0.8 seconds
Started May 12 12:41:19 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 195808 kb
Host smart-0c420d4f-26c5-4d42-8117-6fccb2e1efb2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152521624 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2152521624
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.3864273292
Short name T821
Test name
Test status
Simulation time 143579311 ps
CPU time 2.05 seconds
Started May 12 12:41:12 PM PDT 24
Finished May 12 12:41:16 PM PDT 24
Peak memory 197516 kb
Host smart-8a8d95b6-4765-4542-8ade-e79917ce91bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864273292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.3864273292
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3951687321
Short name T35
Test name
Test status
Simulation time 88578677 ps
CPU time 1.02 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 197576 kb
Host smart-1486ca8d-b916-4191-b333-dee9d11c7783
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951687321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3951687321
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1736336065
Short name T785
Test name
Test status
Simulation time 70672467 ps
CPU time 0.74 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 197544 kb
Host smart-5d829624-39a5-4fc7-aefb-8f0325098e17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736336065 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1736336065
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.848450253
Short name T75
Test name
Test status
Simulation time 51884333 ps
CPU time 0.63 seconds
Started May 12 12:41:17 PM PDT 24
Finished May 12 12:41:19 PM PDT 24
Peak memory 194276 kb
Host smart-6d7c273a-8f8b-46e6-b6e9-764570967099
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848450253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_
csr_rw.848450253
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3477270779
Short name T730
Test name
Test status
Simulation time 40401142 ps
CPU time 0.57 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 193260 kb
Host smart-ee742925-ee98-4fc7-99fb-8d0c1cff284f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477270779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3477270779
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2551670318
Short name T78
Test name
Test status
Simulation time 53397672 ps
CPU time 0.79 seconds
Started May 12 12:41:20 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 195204 kb
Host smart-08c176d0-dced-4b26-a460-b8a3ad4015f0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551670318 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2551670318
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.126169082
Short name T751
Test name
Test status
Simulation time 113905213 ps
CPU time 2.56 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 197576 kb
Host smart-1cc31fd7-7cd9-4991-af92-4ce0cd35127a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126169082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.126169082
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1732637611
Short name T95
Test name
Test status
Simulation time 165842504 ps
CPU time 0.99 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:17 PM PDT 24
Peak memory 197092 kb
Host smart-f970b91a-7014-4c75-8e22-285b01256748
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732637611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1732637611
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2520053373
Short name T266
Test name
Test status
Simulation time 33425068 ps
CPU time 0.61 seconds
Started May 12 01:44:03 PM PDT 24
Finished May 12 01:44:04 PM PDT 24
Peak memory 194580 kb
Host smart-e535a70e-b395-4038-bc69-05335dfe33e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520053373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2520053373
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.717834757
Short name T138
Test name
Test status
Simulation time 48366990 ps
CPU time 0.81 seconds
Started May 12 01:44:03 PM PDT 24
Finished May 12 01:44:05 PM PDT 24
Peak memory 195456 kb
Host smart-df01cbf8-4e89-433e-97e8-19629c7a1113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717834757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.717834757
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.38660881
Short name T662
Test name
Test status
Simulation time 1103404126 ps
CPU time 16.89 seconds
Started May 12 01:44:03 PM PDT 24
Finished May 12 01:44:21 PM PDT 24
Peak memory 195508 kb
Host smart-87577334-ff0f-454b-ada3-b6817d1fef36
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38660881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress.38660881
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1553183760
Short name T249
Test name
Test status
Simulation time 59577283 ps
CPU time 0.95 seconds
Started May 12 01:44:03 PM PDT 24
Finished May 12 01:44:04 PM PDT 24
Peak memory 197108 kb
Host smart-d4cfdef2-c5aa-4504-bc29-189b16022cbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553183760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1553183760
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1989844929
Short name T311
Test name
Test status
Simulation time 160437537 ps
CPU time 1.21 seconds
Started May 12 01:44:02 PM PDT 24
Finished May 12 01:44:04 PM PDT 24
Peak memory 196876 kb
Host smart-b24a6fd2-1c63-4241-b9e4-58866eda0e9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989844929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1989844929
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1069685739
Short name T588
Test name
Test status
Simulation time 398187938 ps
CPU time 1.48 seconds
Started May 12 01:44:03 PM PDT 24
Finished May 12 01:44:05 PM PDT 24
Peak memory 196600 kb
Host smart-81699f7e-1c64-4fde-850b-e620ad9b182f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069685739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1069685739
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.781087733
Short name T479
Test name
Test status
Simulation time 695948517 ps
CPU time 3.29 seconds
Started May 12 01:44:02 PM PDT 24
Finished May 12 01:44:06 PM PDT 24
Peak memory 197092 kb
Host smart-b365fcfd-1a63-476c-8d54-5591b30cbe56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781087733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.781087733
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3843717403
Short name T196
Test name
Test status
Simulation time 95955640 ps
CPU time 0.91 seconds
Started May 12 01:44:10 PM PDT 24
Finished May 12 01:44:12 PM PDT 24
Peak memory 196044 kb
Host smart-fd99946d-42b7-4062-a985-a08f6c2875c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843717403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3843717403
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1921389592
Short name T343
Test name
Test status
Simulation time 74922579 ps
CPU time 0.77 seconds
Started May 12 01:44:03 PM PDT 24
Finished May 12 01:44:05 PM PDT 24
Peak memory 195448 kb
Host smart-a5245c8d-538a-455c-a600-6fdede40ccee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921389592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1921389592
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1596103337
Short name T351
Test name
Test status
Simulation time 1064893143 ps
CPU time 6.3 seconds
Started May 12 01:44:05 PM PDT 24
Finished May 12 01:44:12 PM PDT 24
Peak memory 197992 kb
Host smart-b14a8a01-40af-4ab0-a7a1-9cfc55e4a558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596103337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1596103337
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.652605598
Short name T50
Test name
Test status
Simulation time 240662519 ps
CPU time 0.88 seconds
Started May 12 01:44:03 PM PDT 24
Finished May 12 01:44:05 PM PDT 24
Peak memory 213720 kb
Host smart-dd055429-5d80-47da-b0ac-f8186f28838f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652605598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.652605598
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3649550009
Short name T295
Test name
Test status
Simulation time 58819605 ps
CPU time 1.39 seconds
Started May 12 01:44:03 PM PDT 24
Finished May 12 01:44:06 PM PDT 24
Peak memory 196824 kb
Host smart-d5f4ce93-1fe7-436d-8866-adab02fb0284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649550009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3649550009
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2154616729
Short name T512
Test name
Test status
Simulation time 59803424 ps
CPU time 1.24 seconds
Started May 12 01:44:05 PM PDT 24
Finished May 12 01:44:06 PM PDT 24
Peak memory 197960 kb
Host smart-ef3d1209-b2d7-4526-bd89-da87bd681bb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154616729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2154616729
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1196383722
Short name T226
Test name
Test status
Simulation time 16761237676 ps
CPU time 46.72 seconds
Started May 12 01:44:03 PM PDT 24
Finished May 12 01:44:51 PM PDT 24
Peak memory 198188 kb
Host smart-dd1ece8c-5824-436a-8a0a-da2af1e64a78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196383722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1196383722
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.160724463
Short name T691
Test name
Test status
Simulation time 13274403 ps
CPU time 0.58 seconds
Started May 12 01:44:06 PM PDT 24
Finished May 12 01:44:07 PM PDT 24
Peak memory 194580 kb
Host smart-40468ca7-2a5a-43b5-9a53-d21dbd643185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160724463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.160724463
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.10505851
Short name T171
Test name
Test status
Simulation time 93114315 ps
CPU time 0.69 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 194316 kb
Host smart-842c5d59-25aa-4d93-8cea-66e8b681522b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10505851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.10505851
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1935071373
Short name T156
Test name
Test status
Simulation time 451245061 ps
CPU time 3.57 seconds
Started May 12 01:44:15 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 195472 kb
Host smart-7d202ee9-9d85-4505-bd8f-1aab74531a3f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935071373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1935071373
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3497322328
Short name T666
Test name
Test status
Simulation time 265112930 ps
CPU time 0.99 seconds
Started May 12 01:44:10 PM PDT 24
Finished May 12 01:44:11 PM PDT 24
Peak memory 197192 kb
Host smart-75999180-c16b-4dd8-8c4c-67fc0f4f2371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497322328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3497322328
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1329235181
Short name T284
Test name
Test status
Simulation time 52509723 ps
CPU time 1.34 seconds
Started May 12 01:44:06 PM PDT 24
Finished May 12 01:44:08 PM PDT 24
Peak memory 196988 kb
Host smart-f4d20d96-7b7b-4180-86b1-cc4aeab2f2db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329235181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1329235181
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2493845566
Short name T629
Test name
Test status
Simulation time 253751506 ps
CPU time 2.77 seconds
Started May 12 01:44:05 PM PDT 24
Finished May 12 01:44:08 PM PDT 24
Peak memory 198080 kb
Host smart-a201314a-a9e5-49eb-8da3-31eda95a9c6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493845566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2493845566
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.2272684857
Short name T433
Test name
Test status
Simulation time 873524682 ps
CPU time 2.43 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:16 PM PDT 24
Peak memory 196928 kb
Host smart-62396b22-ada0-4dc6-b874-4819d81f1c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272684857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
2272684857
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2526358977
Short name T499
Test name
Test status
Simulation time 72675623 ps
CPU time 0.75 seconds
Started May 12 01:44:06 PM PDT 24
Finished May 12 01:44:07 PM PDT 24
Peak memory 194364 kb
Host smart-d7eecded-cc4e-4640-a1e2-196fc8089c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526358977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2526358977
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.938183493
Short name T205
Test name
Test status
Simulation time 383811081 ps
CPU time 0.97 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:12 PM PDT 24
Peak memory 196048 kb
Host smart-b3ab4e40-eb30-4624-a6ab-2dbb6d8170fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938183493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.938183493
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.684645820
Short name T161
Test name
Test status
Simulation time 553690585 ps
CPU time 5.77 seconds
Started May 12 01:44:10 PM PDT 24
Finished May 12 01:44:16 PM PDT 24
Peak memory 198044 kb
Host smart-f9f85c91-e640-480a-99c7-e630a062c7f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684645820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.684645820
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1583253248
Short name T38
Test name
Test status
Simulation time 188435101 ps
CPU time 0.97 seconds
Started May 12 01:44:04 PM PDT 24
Finished May 12 01:44:06 PM PDT 24
Peak memory 214980 kb
Host smart-d9f24f11-0a6e-46c0-879a-ab5f3b3a253c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583253248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1583253248
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2150590264
Short name T663
Test name
Test status
Simulation time 25495632 ps
CPU time 0.81 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 195184 kb
Host smart-0e8309f6-3a38-46e7-b0a3-50707f44dae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150590264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2150590264
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.4178431496
Short name T344
Test name
Test status
Simulation time 43419662 ps
CPU time 0.84 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 195356 kb
Host smart-9724a9b1-62e4-4868-903b-564896ab75d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178431496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.4178431496
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1701382734
Short name T192
Test name
Test status
Simulation time 15700126856 ps
CPU time 94.55 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:45:47 PM PDT 24
Peak memory 198116 kb
Host smart-a777b389-eef0-45c0-be19-1a30d26aabc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701382734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1701382734
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2894528514
Short name T561
Test name
Test status
Simulation time 45418608 ps
CPU time 0.55 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:21 PM PDT 24
Peak memory 193912 kb
Host smart-7e7fceee-9a80-4a95-a6e7-1f8f328f680b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894528514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2894528514
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2283635175
Short name T610
Test name
Test status
Simulation time 54748323 ps
CPU time 0.61 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 194024 kb
Host smart-bcf20d6c-f23f-460b-a164-c592ff0b9a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283635175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2283635175
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.444909031
Short name T85
Test name
Test status
Simulation time 809284638 ps
CPU time 20.74 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:44:40 PM PDT 24
Peak memory 198028 kb
Host smart-9caae3bb-26e1-4432-86fc-4e82eb2900fa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444909031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.444909031
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.36427439
Short name T271
Test name
Test status
Simulation time 25105971 ps
CPU time 0.64 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:21 PM PDT 24
Peak memory 195204 kb
Host smart-5f6f5db3-06a6-4075-97f7-31026ccf0c66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36427439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.36427439
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3279722329
Short name T665
Test name
Test status
Simulation time 113922366 ps
CPU time 0.76 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:27 PM PDT 24
Peak memory 195636 kb
Host smart-d9868477-d530-4152-8862-ef85e996574d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279722329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3279722329
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1049347507
Short name T288
Test name
Test status
Simulation time 33536510 ps
CPU time 1.37 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:22 PM PDT 24
Peak memory 197036 kb
Host smart-1253ccae-2941-4e03-8f98-b85c635e1641
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049347507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1049347507
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2224054095
Short name T248
Test name
Test status
Simulation time 1006196058 ps
CPU time 2.28 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:44:24 PM PDT 24
Peak memory 197260 kb
Host smart-e1463c71-6282-413c-addd-97e21d9dcd40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224054095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2224054095
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.4022791411
Short name T185
Test name
Test status
Simulation time 131762895 ps
CPU time 0.9 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 196672 kb
Host smart-2086e26a-63a0-419a-a9ee-b4631bf15eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022791411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.4022791411
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4172331655
Short name T140
Test name
Test status
Simulation time 29380906 ps
CPU time 0.99 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 195908 kb
Host smart-cd0701be-cefd-4db9-a257-680ef21fcaf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172331655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.4172331655
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_smoke.2067578163
Short name T507
Test name
Test status
Simulation time 166276244 ps
CPU time 1.15 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 195712 kb
Host smart-8e19b4f2-1a71-4481-b953-7efa62bc1666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067578163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2067578163
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3073163348
Short name T710
Test name
Test status
Simulation time 200685940 ps
CPU time 0.74 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:27 PM PDT 24
Peak memory 195260 kb
Host smart-9d64cb12-04e7-4883-96b3-2983af592fe3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073163348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3073163348
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.4104942541
Short name T508
Test name
Test status
Simulation time 45490563113 ps
CPU time 157.38 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:46:59 PM PDT 24
Peak memory 198148 kb
Host smart-b24bfcc8-60a1-475f-b7da-a66948a5607f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104942541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.4104942541
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3460334252
Short name T649
Test name
Test status
Simulation time 300042001763 ps
CPU time 1394.03 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 02:07:38 PM PDT 24
Peak memory 198048 kb
Host smart-87f7ba4a-2e22-45e4-be8c-cc7e5b298604
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3460334252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3460334252
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1220799710
Short name T385
Test name
Test status
Simulation time 15590060 ps
CPU time 0.57 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 193912 kb
Host smart-879b8782-7dd7-46fa-aacb-09f7983df0ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220799710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1220799710
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2215830885
Short name T672
Test name
Test status
Simulation time 49028822 ps
CPU time 0.93 seconds
Started May 12 01:44:18 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 195816 kb
Host smart-9137ea97-4e74-44e2-ba7b-3e8e3f6dbf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215830885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2215830885
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.14036303
Short name T236
Test name
Test status
Simulation time 136284120 ps
CPU time 6.8 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 195692 kb
Host smart-aadf20af-8fa8-438a-a121-bfd7172ac67e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14036303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stress
.14036303
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1203993847
Short name T211
Test name
Test status
Simulation time 40903647 ps
CPU time 0.79 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:27 PM PDT 24
Peak memory 196688 kb
Host smart-e0ffddb2-738e-446f-b1b6-da8f7ebcc9ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203993847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1203993847
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1356316455
Short name T462
Test name
Test status
Simulation time 188804280 ps
CPU time 1.1 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 196804 kb
Host smart-f9122b4c-f267-4fb1-9f46-93145cdcab6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356316455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1356316455
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1831326246
Short name T230
Test name
Test status
Simulation time 219044147 ps
CPU time 2.84 seconds
Started May 12 01:44:25 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 198032 kb
Host smart-0ea11a28-6365-436b-865e-4a00e2ae2b89
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831326246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1831326246
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.537854610
Short name T330
Test name
Test status
Simulation time 169508820 ps
CPU time 3.32 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:24 PM PDT 24
Peak memory 198052 kb
Host smart-3ef4a3fb-0e3e-4963-8abe-b4156c184534
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537854610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
537854610
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2363857046
Short name T328
Test name
Test status
Simulation time 95056478 ps
CPU time 0.74 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 195296 kb
Host smart-fbb777c1-90c4-4574-9f6e-0103128251f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363857046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2363857046
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3848549473
Short name T222
Test name
Test status
Simulation time 38698436 ps
CPU time 0.91 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 196928 kb
Host smart-bf652233-e6e7-4f20-9e7d-d112e3eefc23
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848549473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3848549473
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2501118285
Short name T184
Test name
Test status
Simulation time 209298098 ps
CPU time 2.23 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:44:24 PM PDT 24
Peak memory 198224 kb
Host smart-c1cd25a6-2a4d-407d-a294-c01fc2b9992d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501118285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2501118285
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.4155854205
Short name T534
Test name
Test status
Simulation time 20233692 ps
CPU time 0.73 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 194224 kb
Host smart-66805960-f02b-403d-bbc3-74bdd5e8376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155854205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.4155854205
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3244777418
Short name T136
Test name
Test status
Simulation time 125201468 ps
CPU time 1.03 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 196404 kb
Host smart-352466b9-ecf7-4c72-adfd-777d279ad5e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244777418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3244777418
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.363121022
Short name T52
Test name
Test status
Simulation time 50375879055 ps
CPU time 715.27 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:56:19 PM PDT 24
Peak memory 198240 kb
Host smart-b6c2206a-0a57-4530-ba8a-ad22f40fc607
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=363121022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.363121022
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.415386470
Short name T255
Test name
Test status
Simulation time 30878517 ps
CPU time 0.57 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:26 PM PDT 24
Peak memory 193828 kb
Host smart-f156bfad-96c5-40aa-915a-aec64fb45716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415386470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.415386470
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1123254375
Short name T652
Test name
Test status
Simulation time 39917228 ps
CPU time 0.61 seconds
Started May 12 01:44:22 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 193948 kb
Host smart-abb2814e-435d-431b-a8fe-ad19f9a85ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123254375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1123254375
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1254827370
Short name T15
Test name
Test status
Simulation time 1481849365 ps
CPU time 26.78 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:50 PM PDT 24
Peak memory 196844 kb
Host smart-922c7908-c039-4293-beb7-a40fd3c08487
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254827370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1254827370
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2356047524
Short name T705
Test name
Test status
Simulation time 177610718 ps
CPU time 0.89 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 196156 kb
Host smart-649932aa-5756-4afd-addf-73de22987fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356047524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2356047524
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.717481355
Short name T582
Test name
Test status
Simulation time 45003732 ps
CPU time 1.19 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:26 PM PDT 24
Peak memory 196068 kb
Host smart-13132f04-5964-4f47-aeac-194d13116e46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717481355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.717481355
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.4163491120
Short name T367
Test name
Test status
Simulation time 112929513 ps
CPU time 1.28 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:26 PM PDT 24
Peak memory 196516 kb
Host smart-9d460474-98f6-46a3-b8be-8ec14b174c09
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163491120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.4163491120
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2871048483
Short name T468
Test name
Test status
Simulation time 182353580 ps
CPU time 3.37 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:30 PM PDT 24
Peak memory 195840 kb
Host smart-f88376fc-b096-470b-abaf-9025e9cf420f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871048483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2871048483
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.544167378
Short name T19
Test name
Test status
Simulation time 65205968 ps
CPU time 0.88 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 195956 kb
Host smart-03bfbdd4-21c3-4027-9085-f53133724819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544167378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.544167378
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2898912322
Short name T340
Test name
Test status
Simulation time 181656517 ps
CPU time 1.17 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 196108 kb
Host smart-02778637-8f9c-47cf-b782-df048e7105d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898912322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2898912322
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3417492130
Short name T535
Test name
Test status
Simulation time 105381217 ps
CPU time 4.54 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:31 PM PDT 24
Peak memory 197968 kb
Host smart-6f36eb7f-4fcb-4034-924a-f3500b01e92e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417492130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3417492130
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.4164843389
Short name T371
Test name
Test status
Simulation time 61783294 ps
CPU time 0.8 seconds
Started May 12 01:44:22 PM PDT 24
Finished May 12 01:44:24 PM PDT 24
Peak memory 195316 kb
Host smart-931bdfe1-93c3-4dcc-b4fb-6ffc8e98363c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164843389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.4164843389
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3831481054
Short name T411
Test name
Test status
Simulation time 84405307 ps
CPU time 0.78 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 195328 kb
Host smart-644a31fc-92e8-43d6-b650-5525d3da0da6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831481054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3831481054
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4263451377
Short name T308
Test name
Test status
Simulation time 3595026470 ps
CPU time 40.88 seconds
Started May 12 01:44:25 PM PDT 24
Finished May 12 01:45:07 PM PDT 24
Peak memory 198092 kb
Host smart-ea0b0d94-3de7-4beb-8f57-3dad035df20d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263451377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4263451377
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3964629988
Short name T360
Test name
Test status
Simulation time 37206164 ps
CPU time 0.56 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:22 PM PDT 24
Peak memory 194036 kb
Host smart-3f930354-b1be-4b59-ac58-cf962fa8dc40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964629988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3964629988
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3606615391
Short name T326
Test name
Test status
Simulation time 93058917 ps
CPU time 0.74 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:26 PM PDT 24
Peak memory 196148 kb
Host smart-3da3ea0e-de2f-4aff-8fcb-53db16c34c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606615391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3606615391
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.682022716
Short name T706
Test name
Test status
Simulation time 1421666111 ps
CPU time 19.36 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:47 PM PDT 24
Peak memory 197004 kb
Host smart-0023f11b-9516-4aac-8c2b-c21016ea5e1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682022716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.682022716
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1295597453
Short name T21
Test name
Test status
Simulation time 337967149 ps
CPU time 0.95 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 196344 kb
Host smart-a88b807d-f366-4b8c-afa3-5b7c4abe41b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295597453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1295597453
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1499668782
Short name T555
Test name
Test status
Simulation time 187230313 ps
CPU time 1.09 seconds
Started May 12 01:44:25 PM PDT 24
Finished May 12 01:44:27 PM PDT 24
Peak memory 195708 kb
Host smart-e0622505-9d80-46cc-b4a3-35229ce577f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499668782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1499668782
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1262976539
Short name T432
Test name
Test status
Simulation time 47486209 ps
CPU time 1.12 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 196072 kb
Host smart-97717396-827c-42f3-b856-9c5f58ab6911
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262976539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1262976539
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.371409042
Short name T711
Test name
Test status
Simulation time 228998898 ps
CPU time 1.29 seconds
Started May 12 01:44:25 PM PDT 24
Finished May 12 01:44:27 PM PDT 24
Peak memory 196540 kb
Host smart-7a6a9120-c859-4c38-9913-2a7f82804bad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371409042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
371409042
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1327075526
Short name T187
Test name
Test status
Simulation time 55307807 ps
CPU time 1.06 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:26 PM PDT 24
Peak memory 196024 kb
Host smart-26f02bc4-eac3-438b-b990-57eaf16aee9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327075526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1327075526
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3904097785
Short name T182
Test name
Test status
Simulation time 44534663 ps
CPU time 0.86 seconds
Started May 12 01:44:22 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 196388 kb
Host smart-1ab243e4-ceb8-4635-8220-033573974a27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904097785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3904097785
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1923781723
Short name T407
Test name
Test status
Simulation time 41522131 ps
CPU time 1.8 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:26 PM PDT 24
Peak memory 197948 kb
Host smart-577cff71-3213-4008-9bc0-09fbc193e5a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923781723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1923781723
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.4098917786
Short name T509
Test name
Test status
Simulation time 134046490 ps
CPU time 1.14 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 195716 kb
Host smart-3ce1f2ae-f8b4-4f7f-8f07-402f1a8fe5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098917786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.4098917786
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2922249853
Short name T353
Test name
Test status
Simulation time 51415130 ps
CPU time 0.86 seconds
Started May 12 01:44:25 PM PDT 24
Finished May 12 01:44:27 PM PDT 24
Peak memory 196532 kb
Host smart-b38b371c-abf1-41d3-9896-0a40f3de81ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922249853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2922249853
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.565366877
Short name T667
Test name
Test status
Simulation time 10974656176 ps
CPU time 143.72 seconds
Started May 12 01:44:25 PM PDT 24
Finished May 12 01:46:50 PM PDT 24
Peak memory 198116 kb
Host smart-633175ea-4604-43c4-a1bf-94ebd8260999
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565366877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.565366877
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1418210391
Short name T54
Test name
Test status
Simulation time 68374750711 ps
CPU time 505.38 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:52:50 PM PDT 24
Peak memory 198160 kb
Host smart-df90578e-0c52-492f-962b-e9c9036031a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1418210391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1418210391
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3255552827
Short name T716
Test name
Test status
Simulation time 14947286 ps
CPU time 0.59 seconds
Started May 12 01:44:28 PM PDT 24
Finished May 12 01:44:30 PM PDT 24
Peak memory 194868 kb
Host smart-4cc282e2-65b4-4c3c-b243-4115e6a9063a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255552827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3255552827
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3902454865
Short name T670
Test name
Test status
Simulation time 22131160 ps
CPU time 0.8 seconds
Started May 12 01:44:22 PM PDT 24
Finished May 12 01:44:24 PM PDT 24
Peak memory 196180 kb
Host smart-e8591b54-8e7e-4a91-8442-efec6e5474ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902454865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3902454865
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.4149700512
Short name T493
Test name
Test status
Simulation time 548302141 ps
CPU time 7.72 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:36 PM PDT 24
Peak memory 197108 kb
Host smart-d9eba1e4-d86f-4b40-9c9f-50dd94a6ca71
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149700512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.4149700512
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3341232128
Short name T465
Test name
Test status
Simulation time 95645271 ps
CPU time 0.96 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 196608 kb
Host smart-95bbd00a-8264-4ee0-9bef-6222e86d8700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341232128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3341232128
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4221643714
Short name T437
Test name
Test status
Simulation time 45988053 ps
CPU time 0.96 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 197552 kb
Host smart-4e113676-e88b-4ef7-9621-d16c79cead07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221643714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4221643714
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2525349403
Short name T238
Test name
Test status
Simulation time 177207670 ps
CPU time 3.34 seconds
Started May 12 01:44:28 PM PDT 24
Finished May 12 01:44:33 PM PDT 24
Peak memory 197944 kb
Host smart-fd294e84-a7ec-4cd8-8be4-07507fb21aad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525349403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2525349403
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.527666293
Short name T581
Test name
Test status
Simulation time 549325230 ps
CPU time 3.16 seconds
Started May 12 01:44:28 PM PDT 24
Finished May 12 01:44:32 PM PDT 24
Peak memory 197032 kb
Host smart-bf785094-1202-4bb9-924d-04be9b9f8902
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527666293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
527666293
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1802638750
Short name T637
Test name
Test status
Simulation time 49040033 ps
CPU time 0.96 seconds
Started May 12 01:44:25 PM PDT 24
Finished May 12 01:44:27 PM PDT 24
Peak memory 196408 kb
Host smart-38b0068d-53a9-42a8-b6c4-e9960445d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802638750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1802638750
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.416151670
Short name T630
Test name
Test status
Simulation time 45994410 ps
CPU time 0.98 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:26 PM PDT 24
Peak memory 196024 kb
Host smart-ef5d5eff-9a62-4b15-b09a-50159b3681cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416151670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.416151670
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2844763121
Short name T262
Test name
Test status
Simulation time 70991808 ps
CPU time 1.67 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:31 PM PDT 24
Peak memory 197976 kb
Host smart-31d6a38f-2e37-44aa-8155-d395d19a3c20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844763121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2844763121
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.40469338
Short name T606
Test name
Test status
Simulation time 218150801 ps
CPU time 1.31 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:25 PM PDT 24
Peak memory 195532 kb
Host smart-9267fd30-7c75-4b37-83e1-57e9fa9c9bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40469338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.40469338
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.3910474433
Short name T391
Test name
Test status
Simulation time 63197139 ps
CPU time 1.16 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:26 PM PDT 24
Peak memory 195600 kb
Host smart-045d6f7b-c0cc-49dc-97be-49107786c5ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910474433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.3910474433
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1274365453
Short name T533
Test name
Test status
Simulation time 70107248326 ps
CPU time 204.92 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:47:54 PM PDT 24
Peak memory 198180 kb
Host smart-6b7ecda7-274d-4910-9977-6ce8c0a2c740
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274365453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1274365453
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1726288539
Short name T678
Test name
Test status
Simulation time 12997886 ps
CPU time 0.57 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:30 PM PDT 24
Peak memory 194600 kb
Host smart-cfa27c12-bc9c-4fd4-99e1-d28e1b446c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726288539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1726288539
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1332938469
Short name T552
Test name
Test status
Simulation time 34126069 ps
CPU time 0.76 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 196084 kb
Host smart-2c48b62e-1229-4a01-a91c-14b9d05dbdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332938469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1332938469
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2663331779
Short name T403
Test name
Test status
Simulation time 111960767 ps
CPU time 5.62 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:44:31 PM PDT 24
Peak memory 196900 kb
Host smart-c8bf3f06-2404-4f0f-ba64-088509d11b9a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663331779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2663331779
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1224850448
Short name T172
Test name
Test status
Simulation time 226019403 ps
CPU time 1.02 seconds
Started May 12 01:44:28 PM PDT 24
Finished May 12 01:44:30 PM PDT 24
Peak memory 196556 kb
Host smart-a8ebc9a2-6ac1-470d-8be1-400b23bdc783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224850448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1224850448
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.1763391397
Short name T345
Test name
Test status
Simulation time 23963159 ps
CPU time 0.78 seconds
Started May 12 01:44:28 PM PDT 24
Finished May 12 01:44:30 PM PDT 24
Peak memory 195472 kb
Host smart-a52a125a-20f9-4d1b-bad9-acf80732150e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763391397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.1763391397
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.4125729619
Short name T647
Test name
Test status
Simulation time 288960210 ps
CPU time 2.97 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:33 PM PDT 24
Peak memory 198096 kb
Host smart-30384060-7a36-4a40-b39c-58cbbc5605e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125729619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.4125729619
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2062465885
Short name T313
Test name
Test status
Simulation time 89702479 ps
CPU time 1.22 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 196896 kb
Host smart-6dc5f825-894e-4085-a919-9439d2290dd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062465885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2062465885
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3479941161
Short name T632
Test name
Test status
Simulation time 43413201 ps
CPU time 0.95 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 196020 kb
Host smart-f1a94fdb-bfcc-408a-bb2c-3764f7f55157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479941161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3479941161
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3191616066
Short name T688
Test name
Test status
Simulation time 351740944 ps
CPU time 1.1 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 196048 kb
Host smart-74c8158e-e9af-4971-b663-1e87ae02cec8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191616066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3191616066
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2407255729
Short name T426
Test name
Test status
Simulation time 377235734 ps
CPU time 1.11 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 196552 kb
Host smart-74c80a87-ebe0-4110-a35c-945b6e4e4e73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407255729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2407255729
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3452447579
Short name T141
Test name
Test status
Simulation time 61831119 ps
CPU time 1.18 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 195812 kb
Host smart-6b9fd899-7e41-476b-9cf6-7c316094fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452447579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3452447579
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3094097122
Short name T593
Test name
Test status
Simulation time 1040869788 ps
CPU time 1.15 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 195532 kb
Host smart-870da552-f02e-4c7f-bd64-e59a7149be7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094097122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3094097122
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1861071518
Short name T245
Test name
Test status
Simulation time 5703781204 ps
CPU time 144.16 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:46:52 PM PDT 24
Peak memory 198176 kb
Host smart-2d7e56a5-00c3-4d1d-a4dc-8a0a008edfe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861071518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1861071518
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.1369731536
Short name T401
Test name
Test status
Simulation time 616330820352 ps
CPU time 2149.21 seconds
Started May 12 01:44:31 PM PDT 24
Finished May 12 02:20:21 PM PDT 24
Peak memory 206424 kb
Host smart-d8d71c3b-24c3-4797-9b79-d7369696a61f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1369731536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.1369731536
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1631281379
Short name T676
Test name
Test status
Simulation time 40928928 ps
CPU time 0.58 seconds
Started May 12 01:44:32 PM PDT 24
Finished May 12 01:44:33 PM PDT 24
Peak memory 194568 kb
Host smart-1516a9a0-06a4-4000-b4ca-70d999b7a4fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631281379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1631281379
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3501791100
Short name T651
Test name
Test status
Simulation time 100235725 ps
CPU time 0.73 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:31 PM PDT 24
Peak memory 196084 kb
Host smart-f0e9ae98-b98b-4b2d-aea1-2600d70c75ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501791100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3501791100
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2222762055
Short name T246
Test name
Test status
Simulation time 734996882 ps
CPU time 15.9 seconds
Started May 12 01:44:31 PM PDT 24
Finished May 12 01:44:47 PM PDT 24
Peak memory 196748 kb
Host smart-578a671a-ff4f-4233-a7ad-4f9a6c601e56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222762055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2222762055
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.1232823135
Short name T198
Test name
Test status
Simulation time 112410615 ps
CPU time 0.92 seconds
Started May 12 01:44:33 PM PDT 24
Finished May 12 01:44:34 PM PDT 24
Peak memory 196164 kb
Host smart-935d88f6-2416-4af4-9af2-352ca845ac99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232823135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.1232823135
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.648986062
Short name T117
Test name
Test status
Simulation time 179097233 ps
CPU time 1.28 seconds
Started May 12 01:44:26 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 196988 kb
Host smart-9e7d1928-331e-4bfd-9364-dde8b1da63f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648986062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.648986062
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3408297772
Short name T139
Test name
Test status
Simulation time 103790640 ps
CPU time 1.19 seconds
Started May 12 01:44:28 PM PDT 24
Finished May 12 01:44:31 PM PDT 24
Peak memory 196688 kb
Host smart-7fabd65d-da84-494c-a7d4-bb38cfa8f175
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408297772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3408297772
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.694453778
Short name T218
Test name
Test status
Simulation time 348663567 ps
CPU time 1.99 seconds
Started May 12 01:44:31 PM PDT 24
Finished May 12 01:44:33 PM PDT 24
Peak memory 195816 kb
Host smart-9dd626ea-601a-4474-8a5c-98ed28906d0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694453778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
694453778
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1205479297
Short name T87
Test name
Test status
Simulation time 101535968 ps
CPU time 1.08 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 196696 kb
Host smart-299d1d8f-94c0-4c73-bd6c-8f3a638c9e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205479297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1205479297
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3884362419
Short name T152
Test name
Test status
Simulation time 15694649 ps
CPU time 0.71 seconds
Started May 12 01:44:27 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 194312 kb
Host smart-67bfeb63-77aa-47eb-8c7e-907f2033edd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884362419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3884362419
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3770216570
Short name T591
Test name
Test status
Simulation time 229397124 ps
CPU time 2.77 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:33 PM PDT 24
Peak memory 197944 kb
Host smart-10596d36-4246-4de4-af58-9403b1975d6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770216570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3770216570
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3547179108
Short name T680
Test name
Test status
Simulation time 163796639 ps
CPU time 0.92 seconds
Started May 12 01:44:30 PM PDT 24
Finished May 12 01:44:32 PM PDT 24
Peak memory 196472 kb
Host smart-4dc62973-0f2e-4352-8b79-ec2baa8585f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547179108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3547179108
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.780702887
Short name T668
Test name
Test status
Simulation time 87374209 ps
CPU time 1.17 seconds
Started May 12 01:44:28 PM PDT 24
Finished May 12 01:44:30 PM PDT 24
Peak memory 195480 kb
Host smart-8c211e6f-bfd1-43ad-b66f-ab8bc51e55c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780702887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.780702887
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2878944192
Short name T116
Test name
Test status
Simulation time 8344647622 ps
CPU time 114.19 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:46:24 PM PDT 24
Peak memory 198196 kb
Host smart-52389ee9-eb6f-439e-bdb3-36316db8aa92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878944192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2878944192
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.228151437
Short name T240
Test name
Test status
Simulation time 30448031 ps
CPU time 0.86 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:31 PM PDT 24
Peak memory 197288 kb
Host smart-688eee8b-3954-44eb-8096-32171bc0c3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228151437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.228151437
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.875914921
Short name T277
Test name
Test status
Simulation time 258169292 ps
CPU time 3.71 seconds
Started May 12 01:44:32 PM PDT 24
Finished May 12 01:44:37 PM PDT 24
Peak memory 196020 kb
Host smart-8d8add76-44ba-44c6-9163-d31b60ff1838
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875914921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.875914921
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.178953985
Short name T677
Test name
Test status
Simulation time 89717057 ps
CPU time 0.83 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:31 PM PDT 24
Peak memory 196576 kb
Host smart-967a497c-25ea-4480-9fa3-c5e1d89405ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178953985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.178953985
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.678857978
Short name T134
Test name
Test status
Simulation time 36482065 ps
CPU time 1.08 seconds
Started May 12 01:44:31 PM PDT 24
Finished May 12 01:44:33 PM PDT 24
Peak memory 196040 kb
Host smart-e04fd5c8-2398-45d8-a5e0-3d5e75bc290c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678857978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.678857978
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2771081459
Short name T480
Test name
Test status
Simulation time 34541036 ps
CPU time 1.5 seconds
Started May 12 01:44:30 PM PDT 24
Finished May 12 01:44:32 PM PDT 24
Peak memory 197800 kb
Host smart-14b02e32-f2d1-4fa4-8e74-310a80f26095
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771081459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2771081459
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.4025078997
Short name T451
Test name
Test status
Simulation time 114392175 ps
CPU time 1.4 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:32 PM PDT 24
Peak memory 196996 kb
Host smart-10bf11fa-c5ae-4a14-acea-61e157705932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025078997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.4025078997
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.11428595
Short name T715
Test name
Test status
Simulation time 223612722 ps
CPU time 1.16 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:31 PM PDT 24
Peak memory 196560 kb
Host smart-d49e22c5-db1a-4ddf-a9de-607d4924f9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11428595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.11428595
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.380062447
Short name T487
Test name
Test status
Simulation time 52111615 ps
CPU time 0.76 seconds
Started May 12 01:44:31 PM PDT 24
Finished May 12 01:44:33 PM PDT 24
Peak memory 195516 kb
Host smart-3d6319e3-9cb0-41ca-bac8-ff5f66dfaac9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380062447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.380062447
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.65997026
Short name T157
Test name
Test status
Simulation time 2684982135 ps
CPU time 5.72 seconds
Started May 12 01:44:31 PM PDT 24
Finished May 12 01:44:38 PM PDT 24
Peak memory 198088 kb
Host smart-8afdea05-1a40-445f-be58-c7f403b1f1d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65997026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand
om_long_reg_writes_reg_reads.65997026
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1324327243
Short name T551
Test name
Test status
Simulation time 140156202 ps
CPU time 1.02 seconds
Started May 12 01:44:38 PM PDT 24
Finished May 12 01:44:40 PM PDT 24
Peak memory 196256 kb
Host smart-e3a66784-2d17-4d9b-a950-ab54bc70097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324327243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1324327243
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2976337099
Short name T546
Test name
Test status
Simulation time 49631132 ps
CPU time 1.37 seconds
Started May 12 01:44:29 PM PDT 24
Finished May 12 01:44:32 PM PDT 24
Peak memory 196808 kb
Host smart-1a9d4136-1465-4394-abff-989d39ef87b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976337099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2976337099
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.846454190
Short name T260
Test name
Test status
Simulation time 46340400051 ps
CPU time 133.9 seconds
Started May 12 01:44:31 PM PDT 24
Finished May 12 01:46:45 PM PDT 24
Peak memory 198144 kb
Host smart-fc10555e-7db1-4992-a56d-ed68ca3a8391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846454190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.846454190
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.588683309
Short name T274
Test name
Test status
Simulation time 46836077 ps
CPU time 0.58 seconds
Started May 12 01:44:38 PM PDT 24
Finished May 12 01:44:39 PM PDT 24
Peak memory 194624 kb
Host smart-be5eac11-7a36-47da-8392-4591ff34d326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588683309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.588683309
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3602952716
Short name T418
Test name
Test status
Simulation time 174381525 ps
CPU time 0.79 seconds
Started May 12 01:44:34 PM PDT 24
Finished May 12 01:44:36 PM PDT 24
Peak memory 195280 kb
Host smart-118450c6-4bcf-4646-8ced-54731c87d8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602952716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3602952716
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1035043860
Short name T569
Test name
Test status
Simulation time 480966089 ps
CPU time 6.8 seconds
Started May 12 01:44:38 PM PDT 24
Finished May 12 01:44:46 PM PDT 24
Peak memory 196892 kb
Host smart-6135d965-54af-4964-8ccf-43366193ba3d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035043860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1035043860
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.331035216
Short name T683
Test name
Test status
Simulation time 77131511 ps
CPU time 1.05 seconds
Started May 12 01:44:37 PM PDT 24
Finished May 12 01:44:39 PM PDT 24
Peak memory 196516 kb
Host smart-c8694d68-2e16-49c0-badd-dd7bc6897de0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331035216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.331035216
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1005253048
Short name T456
Test name
Test status
Simulation time 72487443 ps
CPU time 1.07 seconds
Started May 12 01:44:37 PM PDT 24
Finished May 12 01:44:39 PM PDT 24
Peak memory 196456 kb
Host smart-9192c548-1f57-4c01-8b5f-55c37d043eb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005253048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1005253048
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2371030443
Short name T362
Test name
Test status
Simulation time 42216318 ps
CPU time 1.75 seconds
Started May 12 01:44:34 PM PDT 24
Finished May 12 01:44:36 PM PDT 24
Peak memory 198128 kb
Host smart-e43bf892-fc2a-40fb-a4ac-b3e33dc08f07
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371030443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2371030443
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3182207133
Short name T473
Test name
Test status
Simulation time 26342200 ps
CPU time 0.99 seconds
Started May 12 01:44:42 PM PDT 24
Finished May 12 01:44:43 PM PDT 24
Peak memory 196400 kb
Host smart-ad6610d4-a7bb-4f65-8e08-4e96a2a40b9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182207133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3182207133
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.947208132
Short name T491
Test name
Test status
Simulation time 49476564 ps
CPU time 1.02 seconds
Started May 12 01:44:38 PM PDT 24
Finished May 12 01:44:40 PM PDT 24
Peak memory 196696 kb
Host smart-e462fa21-915e-40c8-9989-3cd4b127b66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947208132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.947208132
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.420254015
Short name T525
Test name
Test status
Simulation time 202076935 ps
CPU time 1.2 seconds
Started May 12 01:44:36 PM PDT 24
Finished May 12 01:44:37 PM PDT 24
Peak memory 196980 kb
Host smart-fe6cf669-f253-4f9b-97f0-c47b126789c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420254015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.420254015
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.768765490
Short name T537
Test name
Test status
Simulation time 250510080 ps
CPU time 3.58 seconds
Started May 12 01:44:32 PM PDT 24
Finished May 12 01:44:36 PM PDT 24
Peak memory 198008 kb
Host smart-da7f22f6-bd96-4e08-9409-cdd01e9c295d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768765490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.768765490
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2528988855
Short name T137
Test name
Test status
Simulation time 68590237 ps
CPU time 0.91 seconds
Started May 12 01:44:30 PM PDT 24
Finished May 12 01:44:32 PM PDT 24
Peak memory 195488 kb
Host smart-61fc5934-d37c-4425-8128-0aee207fe20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528988855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2528988855
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.910477505
Short name T179
Test name
Test status
Simulation time 104884019 ps
CPU time 0.85 seconds
Started May 12 01:44:34 PM PDT 24
Finished May 12 01:44:35 PM PDT 24
Peak memory 195548 kb
Host smart-1abcd49b-bea7-45bd-87ea-49871511d5be
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910477505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.910477505
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.711815879
Short name T200
Test name
Test status
Simulation time 9504929067 ps
CPU time 68.37 seconds
Started May 12 01:44:37 PM PDT 24
Finished May 12 01:45:46 PM PDT 24
Peak memory 198200 kb
Host smart-6225f5c5-7131-486f-9e67-7dd788acb1c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711815879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.711815879
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.3873161083
Short name T4
Test name
Test status
Simulation time 63473634812 ps
CPU time 800.63 seconds
Started May 12 01:44:39 PM PDT 24
Finished May 12 01:58:00 PM PDT 24
Peak memory 198292 kb
Host smart-5e9c4e05-80b4-4824-a423-613f18391fd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3873161083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.3873161083
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2828902550
Short name T464
Test name
Test status
Simulation time 31723418 ps
CPU time 0.61 seconds
Started May 12 01:44:36 PM PDT 24
Finished May 12 01:44:38 PM PDT 24
Peak memory 194716 kb
Host smart-ac4f12c7-23c8-4674-8180-e7623a60cccc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828902550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2828902550
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.650340408
Short name T131
Test name
Test status
Simulation time 25921191 ps
CPU time 0.65 seconds
Started May 12 01:44:41 PM PDT 24
Finished May 12 01:44:42 PM PDT 24
Peak memory 194268 kb
Host smart-041aaff1-4e37-4bae-9a7f-5b970c0db6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650340408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.650340408
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1703741228
Short name T215
Test name
Test status
Simulation time 209452033 ps
CPU time 10.75 seconds
Started May 12 01:44:44 PM PDT 24
Finished May 12 01:44:55 PM PDT 24
Peak memory 196220 kb
Host smart-c3ab1efa-e881-41f0-9f63-0185ad69b1d0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703741228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1703741228
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1193464838
Short name T611
Test name
Test status
Simulation time 617829478 ps
CPU time 0.83 seconds
Started May 12 01:44:41 PM PDT 24
Finished May 12 01:44:43 PM PDT 24
Peak memory 196716 kb
Host smart-a39f1b6a-f831-40a5-a86d-bcd94b8117bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193464838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1193464838
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1779620294
Short name T199
Test name
Test status
Simulation time 24426215 ps
CPU time 0.72 seconds
Started May 12 01:44:46 PM PDT 24
Finished May 12 01:44:47 PM PDT 24
Peak memory 194348 kb
Host smart-555f53a7-a332-43bc-a437-20f3edbc759c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779620294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1779620294
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1699681478
Short name T166
Test name
Test status
Simulation time 186569010 ps
CPU time 3.92 seconds
Started May 12 01:44:46 PM PDT 24
Finished May 12 01:44:51 PM PDT 24
Peak memory 197964 kb
Host smart-9f02bda4-9607-4775-9f51-ec66d35441da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699681478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1699681478
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.428222654
Short name T460
Test name
Test status
Simulation time 126479306 ps
CPU time 2.86 seconds
Started May 12 01:44:35 PM PDT 24
Finished May 12 01:44:38 PM PDT 24
Peak memory 198008 kb
Host smart-34f30533-df29-4e6b-9c59-9dca21e453a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428222654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
428222654
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.411983193
Short name T282
Test name
Test status
Simulation time 29298666 ps
CPU time 1.09 seconds
Started May 12 01:44:39 PM PDT 24
Finished May 12 01:44:41 PM PDT 24
Peak memory 196652 kb
Host smart-37f39137-2c8f-4795-9764-c0b45248bfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411983193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.411983193
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1617249435
Short name T570
Test name
Test status
Simulation time 22402845 ps
CPU time 0.82 seconds
Started May 12 01:44:45 PM PDT 24
Finished May 12 01:44:46 PM PDT 24
Peak memory 195496 kb
Host smart-f6db8e22-566e-4403-ad0d-5540dfc5abd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617249435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1617249435
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1587773930
Short name T155
Test name
Test status
Simulation time 680175998 ps
CPU time 4.66 seconds
Started May 12 01:44:42 PM PDT 24
Finished May 12 01:44:47 PM PDT 24
Peak memory 198008 kb
Host smart-99920760-5a7e-471e-945c-480af9bd6ccf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587773930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1587773930
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1080062350
Short name T349
Test name
Test status
Simulation time 593428234 ps
CPU time 0.91 seconds
Started May 12 01:44:41 PM PDT 24
Finished May 12 01:44:43 PM PDT 24
Peak memory 196308 kb
Host smart-2f8910c7-891f-4c77-a873-70fd454740e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080062350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1080062350
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2384715439
Short name T697
Test name
Test status
Simulation time 72502024 ps
CPU time 0.83 seconds
Started May 12 01:44:46 PM PDT 24
Finished May 12 01:44:47 PM PDT 24
Peak memory 195280 kb
Host smart-4bf555b5-f5af-4d9b-947b-b85749182b1b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384715439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2384715439
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1635155074
Short name T212
Test name
Test status
Simulation time 5659619427 ps
CPU time 140.66 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:47:12 PM PDT 24
Peak memory 198208 kb
Host smart-6035362e-d21a-4f25-b90b-3ebb56b89cdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635155074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1635155074
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.142334399
Short name T513
Test name
Test status
Simulation time 45434699 ps
CPU time 0.55 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:13 PM PDT 24
Peak memory 194036 kb
Host smart-255d211f-e096-485b-819c-6fecc5612776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142334399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.142334399
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2328750873
Short name T324
Test name
Test status
Simulation time 58878539 ps
CPU time 0.59 seconds
Started May 12 01:44:13 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 193912 kb
Host smart-a582e8a2-d627-4c7b-89b1-7fde10d5b27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328750873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2328750873
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.513633563
Short name T321
Test name
Test status
Simulation time 1130614441 ps
CPU time 4.25 seconds
Started May 12 01:44:10 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 196708 kb
Host smart-79fe558b-4b4c-4e26-bc74-65de28a37d5f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513633563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.513633563
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.279691015
Short name T120
Test name
Test status
Simulation time 70650698 ps
CPU time 1.02 seconds
Started May 12 01:44:13 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 197428 kb
Host smart-dbe787a5-9275-4ccc-8439-7f7055676372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279691015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.279691015
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1293438353
Short name T374
Test name
Test status
Simulation time 173423333 ps
CPU time 1.12 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:12 PM PDT 24
Peak memory 196152 kb
Host smart-8f5c236d-7a50-4854-9fbc-d64f8a263555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293438353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1293438353
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.853817039
Short name T214
Test name
Test status
Simulation time 254125568 ps
CPU time 2.61 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 197828 kb
Host smart-4ff8ed51-1d8a-4649-914e-2f151c132cde
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853817039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.853817039
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2044147997
Short name T358
Test name
Test status
Simulation time 53360700 ps
CPU time 1.36 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 195780 kb
Host smart-7c8bfc0b-459a-4325-b3f3-eee7a29f2c8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044147997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2044147997
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.418003605
Short name T267
Test name
Test status
Simulation time 151021987 ps
CPU time 1.04 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:13 PM PDT 24
Peak memory 195932 kb
Host smart-c602e2f6-30ab-44e9-8a14-4eee38e5430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418003605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.418003605
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1054269709
Short name T694
Test name
Test status
Simulation time 67391058 ps
CPU time 1.23 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:13 PM PDT 24
Peak memory 197048 kb
Host smart-280f734a-323e-494d-945b-ce5beb24bfe6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054269709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1054269709
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.567765201
Short name T102
Test name
Test status
Simulation time 346881718 ps
CPU time 2.86 seconds
Started May 12 01:44:09 PM PDT 24
Finished May 12 01:44:12 PM PDT 24
Peak memory 197912 kb
Host smart-34bbee88-f0e2-4b6b-be51-6ca0e6a73acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567765201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.567765201
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1042112633
Short name T51
Test name
Test status
Simulation time 96323035 ps
CPU time 0.95 seconds
Started May 12 01:44:13 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 214968 kb
Host smart-81fdcad2-d0fe-40e2-b927-64421cff9d19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042112633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1042112633
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1548748617
Short name T628
Test name
Test status
Simulation time 182140983 ps
CPU time 0.97 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:13 PM PDT 24
Peak memory 195692 kb
Host smart-09d45cd4-6b24-4acf-bbee-49a667ca47a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548748617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1548748617
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2406329356
Short name T336
Test name
Test status
Simulation time 30752211 ps
CPU time 0.98 seconds
Started May 12 01:44:09 PM PDT 24
Finished May 12 01:44:11 PM PDT 24
Peak memory 196528 kb
Host smart-f7740c46-eb42-49d6-a870-1cbb4b8f0c8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406329356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2406329356
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1408247276
Short name T679
Test name
Test status
Simulation time 30831868320 ps
CPU time 200.58 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:47:33 PM PDT 24
Peak memory 198392 kb
Host smart-60478010-2cdc-482d-b1b9-053955a6ffe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408247276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1408247276
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.816814941
Short name T55
Test name
Test status
Simulation time 98147189473 ps
CPU time 1115.47 seconds
Started May 12 01:44:09 PM PDT 24
Finished May 12 02:02:45 PM PDT 24
Peak memory 198180 kb
Host smart-0595ded5-efcb-4767-b514-ed3ffe92037d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=816814941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.816814941
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2698524931
Short name T39
Test name
Test status
Simulation time 13774282 ps
CPU time 0.57 seconds
Started May 12 01:44:38 PM PDT 24
Finished May 12 01:44:40 PM PDT 24
Peak memory 194048 kb
Host smart-4d4d1620-81b1-46f1-8fff-59f186198554
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698524931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2698524931
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4206789478
Short name T625
Test name
Test status
Simulation time 146743387 ps
CPU time 0.89 seconds
Started May 12 01:44:39 PM PDT 24
Finished May 12 01:44:40 PM PDT 24
Peak memory 196584 kb
Host smart-dc433036-0c5b-42ff-8699-7791ebd3c1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206789478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4206789478
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3659962688
Short name T539
Test name
Test status
Simulation time 118246877 ps
CPU time 3.81 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:54 PM PDT 24
Peak memory 196384 kb
Host smart-ba7caf81-ee51-480d-8d1c-0383d9231221
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659962688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3659962688
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1838193319
Short name T292
Test name
Test status
Simulation time 108552632 ps
CPU time 0.81 seconds
Started May 12 01:44:42 PM PDT 24
Finished May 12 01:44:43 PM PDT 24
Peak memory 195920 kb
Host smart-246bd747-3395-4dd8-bfb4-7b5ebb74abf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838193319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1838193319
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2185699674
Short name T256
Test name
Test status
Simulation time 65211856 ps
CPU time 1.1 seconds
Started May 12 01:44:45 PM PDT 24
Finished May 12 01:44:46 PM PDT 24
Peak memory 196076 kb
Host smart-f1dc23d3-7251-4afa-a523-03c744e781c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185699674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2185699674
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3822435250
Short name T208
Test name
Test status
Simulation time 368505526 ps
CPU time 3.63 seconds
Started May 12 01:44:47 PM PDT 24
Finished May 12 01:44:51 PM PDT 24
Peak memory 198092 kb
Host smart-4536414f-a394-4c3e-9d98-67f8aa3eaa4a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822435250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3822435250
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3372230034
Short name T690
Test name
Test status
Simulation time 307258387 ps
CPU time 3.53 seconds
Started May 12 01:44:44 PM PDT 24
Finished May 12 01:44:48 PM PDT 24
Peak memory 198036 kb
Host smart-ef5bd998-bcf9-4827-90cd-bf28b9d304a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372230034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3372230034
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.831511061
Short name T516
Test name
Test status
Simulation time 419150649 ps
CPU time 1.3 seconds
Started May 12 01:44:44 PM PDT 24
Finished May 12 01:44:46 PM PDT 24
Peak memory 195904 kb
Host smart-830baa96-c491-46a8-834d-a723c0af1ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831511061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.831511061
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2580427577
Short name T530
Test name
Test status
Simulation time 92954653 ps
CPU time 1.16 seconds
Started May 12 01:44:48 PM PDT 24
Finished May 12 01:44:50 PM PDT 24
Peak memory 195796 kb
Host smart-74cb1919-d2bb-448b-88bc-d514b8894d18
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580427577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2580427577
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.988590833
Short name T599
Test name
Test status
Simulation time 65250462 ps
CPU time 1.41 seconds
Started May 12 01:44:44 PM PDT 24
Finished May 12 01:44:46 PM PDT 24
Peak memory 197968 kb
Host smart-36e19247-1f69-41ee-bd34-80e9ba5fa8f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988590833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.988590833
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2030210657
Short name T170
Test name
Test status
Simulation time 53849330 ps
CPU time 1.05 seconds
Started May 12 01:44:38 PM PDT 24
Finished May 12 01:44:40 PM PDT 24
Peak memory 195452 kb
Host smart-49cd6933-bb28-46e7-9fa7-d9996c75e195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030210657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2030210657
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1270719978
Short name T612
Test name
Test status
Simulation time 61019768 ps
CPU time 1.08 seconds
Started May 12 01:44:39 PM PDT 24
Finished May 12 01:44:41 PM PDT 24
Peak memory 195628 kb
Host smart-911688b2-648f-41f9-94cf-c6a4dc804bb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270719978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1270719978
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2678882014
Short name T522
Test name
Test status
Simulation time 4476335622 ps
CPU time 104.98 seconds
Started May 12 01:44:36 PM PDT 24
Finished May 12 01:46:21 PM PDT 24
Peak memory 198188 kb
Host smart-a9b5b1d9-9ad9-455a-a1fb-48b8bfa5f957
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678882014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2678882014
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2654461135
Short name T494
Test name
Test status
Simulation time 65952541556 ps
CPU time 1412.78 seconds
Started May 12 01:44:48 PM PDT 24
Finished May 12 02:08:22 PM PDT 24
Peak memory 198132 kb
Host smart-727f3972-84ec-47e1-9ffb-deb9cbd63a05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2654461135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2654461135
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.928054363
Short name T674
Test name
Test status
Simulation time 26833646 ps
CPU time 0.59 seconds
Started May 12 01:44:46 PM PDT 24
Finished May 12 01:44:47 PM PDT 24
Peak memory 194616 kb
Host smart-c34eaea0-b67d-4f06-93b6-1d4708b02be7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928054363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.928054363
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1652583944
Short name T554
Test name
Test status
Simulation time 29993074 ps
CPU time 0.94 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:44:51 PM PDT 24
Peak memory 196536 kb
Host smart-28074891-a2f9-4d18-aef6-ed4bedb65cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652583944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1652583944
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2146962761
Short name T449
Test name
Test status
Simulation time 1146763782 ps
CPU time 13.55 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:45:04 PM PDT 24
Peak memory 196840 kb
Host smart-97810b5b-e5f7-4288-bb00-0400a96083d0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146962761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2146962761
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.404768564
Short name T481
Test name
Test status
Simulation time 73408063 ps
CPU time 1.04 seconds
Started May 12 01:44:42 PM PDT 24
Finished May 12 01:44:44 PM PDT 24
Peak memory 196480 kb
Host smart-62644bc3-6509-4e7f-9152-df11bf8e946a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404768564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.404768564
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2967104401
Short name T348
Test name
Test status
Simulation time 41416464 ps
CPU time 1.23 seconds
Started May 12 01:44:40 PM PDT 24
Finished May 12 01:44:42 PM PDT 24
Peak memory 196524 kb
Host smart-3339ab71-768a-43de-aa56-bcaa3fc20f6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967104401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2967104401
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2791423234
Short name T221
Test name
Test status
Simulation time 144331277 ps
CPU time 1.14 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:55 PM PDT 24
Peak memory 197464 kb
Host smart-81578d2f-7d3f-486c-bb89-268f75ea2be5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791423234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2791423234
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2048690629
Short name T16
Test name
Test status
Simulation time 73182592 ps
CPU time 1.8 seconds
Started May 12 01:44:46 PM PDT 24
Finished May 12 01:44:48 PM PDT 24
Peak memory 196524 kb
Host smart-1265acb5-2c9c-4858-bd76-69eb07c11b29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048690629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2048690629
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.4252623755
Short name T405
Test name
Test status
Simulation time 56697432 ps
CPU time 1.22 seconds
Started May 12 01:44:44 PM PDT 24
Finished May 12 01:44:45 PM PDT 24
Peak memory 197076 kb
Host smart-f04e0f1e-6dbf-48aa-89a8-f0a1336bc7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252623755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.4252623755
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.105742358
Short name T699
Test name
Test status
Simulation time 29192703 ps
CPU time 0.71 seconds
Started May 12 01:44:43 PM PDT 24
Finished May 12 01:44:44 PM PDT 24
Peak memory 195468 kb
Host smart-5e40f220-4157-40db-bb10-ad2d6ed9986d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105742358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup
_pulldown.105742358
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3634131786
Short name T642
Test name
Test status
Simulation time 95246251 ps
CPU time 1.63 seconds
Started May 12 01:44:41 PM PDT 24
Finished May 12 01:44:43 PM PDT 24
Peak memory 198020 kb
Host smart-429808f4-e730-464e-9b08-b1885e0e07f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634131786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3634131786
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1922063601
Short name T609
Test name
Test status
Simulation time 151379506 ps
CPU time 1.09 seconds
Started May 12 01:44:44 PM PDT 24
Finished May 12 01:44:45 PM PDT 24
Peak memory 195660 kb
Host smart-6a38fb2b-b24e-4100-b4de-2135f6f8187b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922063601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1922063601
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1645777412
Short name T707
Test name
Test status
Simulation time 199763254 ps
CPU time 0.73 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 194876 kb
Host smart-9fdb6976-bcfb-4c60-a4d9-56f4b07c44d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645777412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1645777412
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.6707455
Short name T92
Test name
Test status
Simulation time 4497458597 ps
CPU time 109.67 seconds
Started May 12 01:44:46 PM PDT 24
Finished May 12 01:46:36 PM PDT 24
Peak memory 198112 kb
Host smart-ed58ccfa-e594-4e6e-a933-f3dd664ca6db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6707455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TES
T_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpi
o_stress_all.6707455
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3814609021
Short name T382
Test name
Test status
Simulation time 15407915 ps
CPU time 0.6 seconds
Started May 12 01:44:45 PM PDT 24
Finished May 12 01:44:47 PM PDT 24
Peak memory 194940 kb
Host smart-ed551c57-abb1-448d-a8bb-6e7f74691566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814609021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3814609021
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1337749242
Short name T576
Test name
Test status
Simulation time 19267158 ps
CPU time 0.68 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 194188 kb
Host smart-67748b5d-3a70-46ab-8b98-88257e8cfd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337749242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1337749242
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.440581989
Short name T195
Test name
Test status
Simulation time 1590188680 ps
CPU time 5.04 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:45:00 PM PDT 24
Peak memory 198012 kb
Host smart-ec85e9be-b3a9-4429-8830-6af2235cdd14
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440581989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.440581989
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1884491813
Short name T322
Test name
Test status
Simulation time 21688011 ps
CPU time 0.64 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:44:52 PM PDT 24
Peak memory 194564 kb
Host smart-f062e241-0991-4e35-b87f-45cbe0b52f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884491813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1884491813
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3365679240
Short name T658
Test name
Test status
Simulation time 48009816 ps
CPU time 0.88 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 196624 kb
Host smart-b1a5950f-2a9c-4aec-a296-4c2684cdae2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365679240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3365679240
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2747200694
Short name T565
Test name
Test status
Simulation time 263943923 ps
CPU time 2.49 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:52 PM PDT 24
Peak memory 198268 kb
Host smart-1624be39-cf80-4849-924c-bc6aa82db0a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747200694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2747200694
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1528414283
Short name T383
Test name
Test status
Simulation time 140685984 ps
CPU time 3.01 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 197220 kb
Host smart-4b572285-eca0-47c6-9b1b-55ff6b1e5d8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528414283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1528414283
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2531586064
Short name T261
Test name
Test status
Simulation time 69403528 ps
CPU time 0.87 seconds
Started May 12 01:44:48 PM PDT 24
Finished May 12 01:44:49 PM PDT 24
Peak memory 196652 kb
Host smart-06fc9b49-a95e-4087-889b-8035d8ef1e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531586064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2531586064
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3722801904
Short name T197
Test name
Test status
Simulation time 50364892 ps
CPU time 1.13 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 195968 kb
Host smart-27efc733-7d3d-427c-a4a9-d64cca560f36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722801904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3722801904
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.150444434
Short name T119
Test name
Test status
Simulation time 316426059 ps
CPU time 5.31 seconds
Started May 12 01:44:44 PM PDT 24
Finished May 12 01:44:50 PM PDT 24
Peak memory 197936 kb
Host smart-4a8e09bb-0fc3-462f-9d53-6a4970505af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150444434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.150444434
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3062993740
Short name T636
Test name
Test status
Simulation time 112498990 ps
CPU time 1.47 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:51 PM PDT 24
Peak memory 196808 kb
Host smart-521f6615-b027-4ded-9b88-8355df90988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062993740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3062993740
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3340346677
Short name T425
Test name
Test status
Simulation time 820104925 ps
CPU time 1.39 seconds
Started May 12 01:44:46 PM PDT 24
Finished May 12 01:44:48 PM PDT 24
Peak memory 197016 kb
Host smart-9eb6a27f-a9ae-45fa-8c46-6c179ab45599
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340346677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3340346677
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3430107105
Short name T495
Test name
Test status
Simulation time 20639445990 ps
CPU time 221.35 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:48:34 PM PDT 24
Peak memory 198232 kb
Host smart-e3ec5029-76a5-4cc3-8352-45b19cd03893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430107105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3430107105
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2654280649
Short name T130
Test name
Test status
Simulation time 13910737 ps
CPU time 0.6 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:50 PM PDT 24
Peak memory 194832 kb
Host smart-fcfa0b77-9257-4b02-a8a9-9675e541d720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654280649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2654280649
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.52756707
Short name T108
Test name
Test status
Simulation time 68825712 ps
CPU time 0.85 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:54 PM PDT 24
Peak memory 196356 kb
Host smart-50468893-5272-4dcb-a082-7780e6f7ac9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52756707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.52756707
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1064850626
Short name T296
Test name
Test status
Simulation time 1441580227 ps
CPU time 17.9 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:45:09 PM PDT 24
Peak memory 196876 kb
Host smart-e6fe421e-5214-4fe0-886e-a412623f30e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064850626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1064850626
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3322818521
Short name T566
Test name
Test status
Simulation time 313343138 ps
CPU time 0.96 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:51 PM PDT 24
Peak memory 196160 kb
Host smart-ce130744-a9c9-4bff-95b9-b728103bc3fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322818521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3322818521
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2298622175
Short name T626
Test name
Test status
Simulation time 87357840 ps
CPU time 0.69 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 195164 kb
Host smart-65456d87-aeca-4a5b-a41a-cdf2d2f55c83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298622175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2298622175
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1431142811
Short name T257
Test name
Test status
Simulation time 343810257 ps
CPU time 3.33 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:44:55 PM PDT 24
Peak memory 198004 kb
Host smart-f4d1e3ba-cbac-4b1e-ba4c-c7870e02651f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431142811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1431142811
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3313538868
Short name T306
Test name
Test status
Simulation time 738347096 ps
CPU time 3.31 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 198104 kb
Host smart-85fb033a-896b-4827-bc91-c325cd5f4292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313538868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3313538868
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.4110852029
Short name T104
Test name
Test status
Simulation time 50504285 ps
CPU time 0.76 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:51 PM PDT 24
Peak memory 195396 kb
Host smart-8c3481cb-96e6-4ed7-9b04-e44892e9d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110852029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.4110852029
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1912147681
Short name T448
Test name
Test status
Simulation time 209106154 ps
CPU time 1.15 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 196880 kb
Host smart-88fa1596-115a-483d-8b5a-2506e2a916b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912147681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1912147681
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4224640317
Short name T474
Test name
Test status
Simulation time 345363339 ps
CPU time 4.03 seconds
Started May 12 01:44:48 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 197940 kb
Host smart-aa21c711-7df5-43c5-a569-3db1f4b48024
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224640317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4224640317
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3071390211
Short name T538
Test name
Test status
Simulation time 119730841 ps
CPU time 1.15 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:44:52 PM PDT 24
Peak memory 196420 kb
Host smart-04dba3ff-e528-4b3c-b6c1-76111851148d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071390211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3071390211
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2002901497
Short name T14
Test name
Test status
Simulation time 196458100 ps
CPU time 1.09 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:51 PM PDT 24
Peak memory 195844 kb
Host smart-84d1a8ef-49ce-45b1-9e1c-fa4e604738e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002901497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2002901497
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2331819925
Short name T390
Test name
Test status
Simulation time 11224199529 ps
CPU time 151.23 seconds
Started May 12 01:44:48 PM PDT 24
Finished May 12 01:47:20 PM PDT 24
Peak memory 198188 kb
Host smart-c9931c62-7716-491f-bbf7-d0cd6c0db510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331819925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2331819925
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1288057312
Short name T597
Test name
Test status
Simulation time 12185793 ps
CPU time 0.57 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 193892 kb
Host smart-5a9a5a13-b985-46a1-86fc-1606c2ef8650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288057312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1288057312
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1665258534
Short name T188
Test name
Test status
Simulation time 23573481 ps
CPU time 0.73 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 194136 kb
Host smart-f19c50fb-3281-457d-b14f-cdef98a9089d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665258534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1665258534
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1492230324
Short name T252
Test name
Test status
Simulation time 1600284404 ps
CPU time 11.86 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 197092 kb
Host smart-17e3e1c3-66bb-4509-88be-2f958180799e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492230324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1492230324
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4076652332
Short name T656
Test name
Test status
Simulation time 80006286 ps
CPU time 0.98 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:44:52 PM PDT 24
Peak memory 197772 kb
Host smart-a5e14998-d49a-4114-b649-96a08ba7569f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076652332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4076652332
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3028438695
Short name T378
Test name
Test status
Simulation time 107012011 ps
CPU time 0.93 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 195704 kb
Host smart-f3630c07-8c9f-4ad1-a263-6e52e66ade38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028438695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3028438695
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.937094895
Short name T557
Test name
Test status
Simulation time 40615510 ps
CPU time 1.02 seconds
Started May 12 01:44:55 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 196816 kb
Host smart-30d4572b-9ff1-4fb0-9a26-98b7c3dcc515
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937094895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.937094895
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.783979515
Short name T458
Test name
Test status
Simulation time 43876494 ps
CPU time 1.46 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 196040 kb
Host smart-20b7ee99-ac03-4292-a41e-c40ae91dd6bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783979515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
783979515
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1473570496
Short name T114
Test name
Test status
Simulation time 176661264 ps
CPU time 0.84 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 196516 kb
Host smart-91f656ca-186f-4321-8e24-6a60d6ed58e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473570496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1473570496
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.974132058
Short name T478
Test name
Test status
Simulation time 27130917 ps
CPU time 1.09 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 195716 kb
Host smart-30ad9e3f-0498-4a78-ad34-1ad15ead2e7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974132058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.974132058
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2001234667
Short name T8
Test name
Test status
Simulation time 138604397 ps
CPU time 1.89 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 198000 kb
Host smart-00fb597d-4c82-4541-a13b-c40cc20cedd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001234667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2001234667
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2552772286
Short name T334
Test name
Test status
Simulation time 266046898 ps
CPU time 1.3 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 196516 kb
Host smart-cc103c53-058e-483b-8b03-5a3e0ea761da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552772286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2552772286
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3812181725
Short name T219
Test name
Test status
Simulation time 163414358 ps
CPU time 0.99 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 196532 kb
Host smart-dca6736f-7f93-45b2-b990-ab0562ff4c32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812181725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3812181725
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.867939885
Short name T190
Test name
Test status
Simulation time 17173804494 ps
CPU time 203.28 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:48:13 PM PDT 24
Peak memory 198168 kb
Host smart-5a49c9c0-fb46-4858-9ee4-05145ca2a8c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867939885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.867939885
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3557597042
Short name T89
Test name
Test status
Simulation time 73337674 ps
CPU time 0.55 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 193892 kb
Host smart-d6c8127b-a874-4c8c-b21f-6ce7f7af07de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557597042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3557597042
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3920007493
Short name T27
Test name
Test status
Simulation time 23912651 ps
CPU time 0.71 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:50 PM PDT 24
Peak memory 195252 kb
Host smart-a6c90e1f-61bd-4f7a-8923-0a560a0f94de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920007493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3920007493
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1125999806
Short name T317
Test name
Test status
Simulation time 1985873544 ps
CPU time 26.26 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 01:45:21 PM PDT 24
Peak memory 196580 kb
Host smart-756b9c0d-8bf7-4bb9-b382-a241d4d05233
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125999806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1125999806
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.505735686
Short name T135
Test name
Test status
Simulation time 23272130 ps
CPU time 0.61 seconds
Started May 12 01:44:55 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 194504 kb
Host smart-0e37c7a0-bdcb-424a-936d-d39c4efc9ab5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505735686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.505735686
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2636621842
Short name T435
Test name
Test status
Simulation time 112188853 ps
CPU time 1.01 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 196812 kb
Host smart-3d1b2b07-6266-45ad-be77-3b28a05d662b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636621842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2636621842
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4221525607
Short name T601
Test name
Test status
Simulation time 32464219 ps
CPU time 1.35 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:51 PM PDT 24
Peak memory 196460 kb
Host smart-3c021282-adc8-45cd-8b6e-c7b895547e8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221525607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4221525607
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1140047390
Short name T235
Test name
Test status
Simulation time 88370298 ps
CPU time 0.91 seconds
Started May 12 01:44:48 PM PDT 24
Finished May 12 01:44:50 PM PDT 24
Peak memory 196256 kb
Host smart-8e6b4ea0-f192-4293-a6f3-b2ecc9c79e7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140047390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1140047390
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1540708527
Short name T556
Test name
Test status
Simulation time 57455995 ps
CPU time 1.13 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:54 PM PDT 24
Peak memory 197160 kb
Host smart-67e31d84-3327-4d9d-8d58-33c4f6350786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540708527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1540708527
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2526408954
Short name T122
Test name
Test status
Simulation time 30407292 ps
CPU time 0.94 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 196112 kb
Host smart-947799d6-892e-4ed5-be81-8d5113589939
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526408954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2526408954
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3458139400
Short name T276
Test name
Test status
Simulation time 1410705744 ps
CPU time 2.86 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:44:55 PM PDT 24
Peak memory 198000 kb
Host smart-d747d314-aa82-477c-919d-cd9a2c72a219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458139400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3458139400
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1771113726
Short name T314
Test name
Test status
Simulation time 185147908 ps
CPU time 1.2 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 196688 kb
Host smart-3fb03d81-622d-4239-8e1b-db8405156948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771113726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1771113726
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3106763316
Short name T315
Test name
Test status
Simulation time 40095461 ps
CPU time 1.14 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:54 PM PDT 24
Peak memory 196488 kb
Host smart-a4ceeb9f-3251-4fbd-a6b9-e3dde68e37f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106763316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3106763316
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2251671794
Short name T568
Test name
Test status
Simulation time 1318499721 ps
CPU time 33.99 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:45:25 PM PDT 24
Peak memory 198080 kb
Host smart-418a61df-d800-4d09-b656-92b0be315cb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251671794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2251671794
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.761376826
Short name T53
Test name
Test status
Simulation time 19893805127 ps
CPU time 316.78 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:50:14 PM PDT 24
Peak memory 198156 kb
Host smart-3bd24b99-b207-4031-a095-570b3d51e3a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=761376826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.761376826
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1415111796
Short name T234
Test name
Test status
Simulation time 27109858 ps
CPU time 0.56 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 194680 kb
Host smart-460ad6f4-765c-45ed-a19b-8a6eb935c6bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415111796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1415111796
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.4084082714
Short name T422
Test name
Test status
Simulation time 103184239 ps
CPU time 0.83 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 195280 kb
Host smart-75459ee2-dd1e-4463-83f6-d3f063cd0ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084082714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.4084082714
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3376337407
Short name T421
Test name
Test status
Simulation time 330527944 ps
CPU time 9.8 seconds
Started May 12 01:44:49 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 196740 kb
Host smart-a85c7991-aa12-447c-bf1e-bbeaaea460d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376337407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3376337407
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1136315232
Short name T293
Test name
Test status
Simulation time 77084607 ps
CPU time 0.98 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:55 PM PDT 24
Peak memory 196552 kb
Host smart-80712e21-ce8f-45dd-b6ee-780a6a733f18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136315232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1136315232
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3505271733
Short name T189
Test name
Test status
Simulation time 309351412 ps
CPU time 1.02 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 195828 kb
Host smart-367b7497-4380-4b41-a8dd-5f4e9c16161b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505271733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3505271733
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.4000548402
Short name T445
Test name
Test status
Simulation time 234870234 ps
CPU time 3.18 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:44:55 PM PDT 24
Peak memory 198064 kb
Host smart-66a3d33e-f159-442e-8013-2a8fa0f9fc93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000548402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.4000548402
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.4018358856
Short name T664
Test name
Test status
Simulation time 225375604 ps
CPU time 1.46 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:44:53 PM PDT 24
Peak memory 197280 kb
Host smart-52d14c14-797d-44c8-bd4f-3eb823427923
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018358856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.4018358856
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.243007585
Short name T409
Test name
Test status
Simulation time 40130975 ps
CPU time 0.89 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 195984 kb
Host smart-45f5a7fa-474c-43cf-981e-efb5bb93c7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243007585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.243007585
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.730659976
Short name T646
Test name
Test status
Simulation time 398406439 ps
CPU time 1.28 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 197316 kb
Host smart-50ba08c5-3c77-4309-a15d-5d047d0286c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730659976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullup
_pulldown.730659976
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1488467311
Short name T442
Test name
Test status
Simulation time 155384970 ps
CPU time 3.49 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 197976 kb
Host smart-254d2a69-0843-4277-8f23-b4620cf44c77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488467311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1488467311
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2374552596
Short name T272
Test name
Test status
Simulation time 112316619 ps
CPU time 1 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 196328 kb
Host smart-fa0b86ea-8d45-4ba7-a7b9-511578d66d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374552596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2374552596
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.709161993
Short name T545
Test name
Test status
Simulation time 171279104 ps
CPU time 1.25 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 196740 kb
Host smart-04f082a2-09a4-42d5-9443-68aeb5d375c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709161993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.709161993
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.441819316
Short name T159
Test name
Test status
Simulation time 8134362377 ps
CPU time 216.05 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:48:29 PM PDT 24
Peak memory 198048 kb
Host smart-ae988259-cfd9-4bfc-945b-a7d1c16b3c98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441819316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.441819316
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1325064891
Short name T580
Test name
Test status
Simulation time 13527582 ps
CPU time 0.57 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 193916 kb
Host smart-021adb32-4712-4ebc-b6b5-24b223f4d5cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325064891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1325064891
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2696003444
Short name T280
Test name
Test status
Simulation time 20811986 ps
CPU time 0.71 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 195236 kb
Host smart-8c4aa9ec-bf88-44a8-beb0-a93adbd92e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696003444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2696003444
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1632183697
Short name T335
Test name
Test status
Simulation time 1366564070 ps
CPU time 16.92 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:45:09 PM PDT 24
Peak memory 196984 kb
Host smart-de9e2658-ff89-457a-96b9-1d44baea78cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632183697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1632183697
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2460206323
Short name T398
Test name
Test status
Simulation time 61223691 ps
CPU time 0.87 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:55 PM PDT 24
Peak memory 195924 kb
Host smart-1572b737-5ffe-463c-b8ee-ba6697987fb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460206323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2460206323
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.2777097021
Short name T341
Test name
Test status
Simulation time 75175013 ps
CPU time 1.22 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:44:52 PM PDT 24
Peak memory 196672 kb
Host smart-aad3c76c-b7a7-43d9-bda4-fff408739fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777097021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.2777097021
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2651020080
Short name T169
Test name
Test status
Simulation time 90239360 ps
CPU time 3.2 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 197740 kb
Host smart-9f5449c4-7e63-4a7d-b7d1-2c661d74f87a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651020080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2651020080
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.822164942
Short name T250
Test name
Test status
Simulation time 138336797 ps
CPU time 2.65 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 197152 kb
Host smart-fcd6ef73-6ffd-4864-8f25-e9dea71f49f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822164942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
822164942
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2722918859
Short name T32
Test name
Test status
Simulation time 29362779 ps
CPU time 0.84 seconds
Started May 12 01:44:55 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 196632 kb
Host smart-13f82499-bddb-4617-bd6b-144c1fc8916a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722918859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2722918859
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1965958882
Short name T327
Test name
Test status
Simulation time 93175071 ps
CPU time 1.12 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:54 PM PDT 24
Peak memory 196768 kb
Host smart-be7d9638-a7be-45f6-8ef8-bcf1fd53fd95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965958882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1965958882
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.341325696
Short name T567
Test name
Test status
Simulation time 188780432 ps
CPU time 1.27 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 197940 kb
Host smart-4d331a27-4f7d-4052-a25f-5c51b9f36dea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341325696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.341325696
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.544340266
Short name T528
Test name
Test status
Simulation time 99947533 ps
CPU time 1.5 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 196764 kb
Host smart-861a347b-e08c-412d-b03e-4c4144ea8b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544340266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.544340266
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.92090150
Short name T595
Test name
Test status
Simulation time 105348058 ps
CPU time 1.24 seconds
Started May 12 01:45:07 PM PDT 24
Finished May 12 01:45:09 PM PDT 24
Peak memory 197944 kb
Host smart-8e3a723e-4b74-49a9-b556-c35a308251c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92090150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.92090150
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1364113402
Short name T587
Test name
Test status
Simulation time 19664698284 ps
CPU time 187.33 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:48:01 PM PDT 24
Peak memory 198136 kb
Host smart-4c2e7a89-21ea-4851-a3b1-56d8fe157893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364113402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1364113402
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.386128379
Short name T659
Test name
Test status
Simulation time 65299577 ps
CPU time 0.56 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 193868 kb
Host smart-46f589c2-1fc0-4c2f-8e56-e1aafad6bfdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386128379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.386128379
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1311276387
Short name T103
Test name
Test status
Simulation time 90728992 ps
CPU time 0.91 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 195468 kb
Host smart-e0d6e883-33ef-479d-bc26-88ba7b7558c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311276387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1311276387
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3664296646
Short name T692
Test name
Test status
Simulation time 3213325434 ps
CPU time 14.88 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:22 PM PDT 24
Peak memory 198056 kb
Host smart-23f00eeb-73bd-4e3d-b2a9-ecc597012394
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664296646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3664296646
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2282641007
Short name T331
Test name
Test status
Simulation time 44963040 ps
CPU time 0.66 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:55 PM PDT 24
Peak memory 194688 kb
Host smart-57fa4b5f-3ed2-4b55-971b-014724ab2888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282641007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2282641007
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.861504083
Short name T361
Test name
Test status
Simulation time 465492703 ps
CPU time 1.51 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 197216 kb
Host smart-434003d3-cae3-4582-9449-6c506bd27ffc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861504083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.861504083
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.27600095
Short name T558
Test name
Test status
Simulation time 88792643 ps
CPU time 1.82 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 198132 kb
Host smart-37e0ccb2-b51f-4671-9019-b578016c4f62
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27600095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.gpio_intr_with_filter_rand_intr_event.27600095
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3514574636
Short name T121
Test name
Test status
Simulation time 88254536 ps
CPU time 2.78 seconds
Started May 12 01:44:50 PM PDT 24
Finished May 12 01:44:54 PM PDT 24
Peak memory 195884 kb
Host smart-6547d7bc-5f09-4946-b406-0030b010b8fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514574636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3514574636
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3158777040
Short name T521
Test name
Test status
Simulation time 786665718 ps
CPU time 1.24 seconds
Started May 12 01:44:55 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 196988 kb
Host smart-edaee1ba-f543-400d-83e3-45612dbaef3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158777040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3158777040
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.695088518
Short name T201
Test name
Test status
Simulation time 109243356 ps
CPU time 1.05 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 196004 kb
Host smart-cc1be28b-99bb-4d26-9672-bbd6c86c768b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695088518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.695088518
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3217711479
Short name T183
Test name
Test status
Simulation time 547996812 ps
CPU time 4.69 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 197940 kb
Host smart-da66f09b-c4a0-4b52-a9f3-6b954663677f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217711479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3217711479
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2940070321
Short name T412
Test name
Test status
Simulation time 459823933 ps
CPU time 1.19 seconds
Started May 12 01:44:52 PM PDT 24
Finished May 12 01:44:54 PM PDT 24
Peak memory 195804 kb
Host smart-3109455e-42dd-4af5-8fda-7a323ea70f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940070321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2940070321
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.143574152
Short name T379
Test name
Test status
Simulation time 252199395 ps
CPU time 1.22 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 195532 kb
Host smart-ac49bace-f62c-45c9-9dbd-faa35723e397
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143574152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.143574152
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2965766908
Short name T529
Test name
Test status
Simulation time 34416355345 ps
CPU time 125.87 seconds
Started May 12 01:44:51 PM PDT 24
Finished May 12 01:46:58 PM PDT 24
Peak memory 198200 kb
Host smart-d53705ea-29eb-494d-b82b-a35791b4a49f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965766908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2965766908
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2125328578
Short name T515
Test name
Test status
Simulation time 196810244582 ps
CPU time 2317.28 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 02:23:37 PM PDT 24
Peak memory 198248 kb
Host smart-f5a60c8e-1462-453e-9ada-f077fd0471d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2125328578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2125328578
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1890374126
Short name T653
Test name
Test status
Simulation time 13038400 ps
CPU time 0.6 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 193860 kb
Host smart-76630343-71ea-42ec-8aee-13ca2c06aa96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890374126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1890374126
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3533422777
Short name T693
Test name
Test status
Simulation time 40417374 ps
CPU time 0.94 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 195720 kb
Host smart-5ee515ae-15a6-48a1-8f87-34dd27133c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533422777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3533422777
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.673226428
Short name T233
Test name
Test status
Simulation time 391811959 ps
CPU time 4.64 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 196992 kb
Host smart-cc611565-8974-4ed2-a602-fd2db245b9f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673226428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.673226428
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3612061996
Short name T482
Test name
Test status
Simulation time 177249661 ps
CPU time 0.65 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 01:44:55 PM PDT 24
Peak memory 195360 kb
Host smart-6d66d175-bf58-4610-b0e2-868f0294517c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612061996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3612061996
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3219779012
Short name T476
Test name
Test status
Simulation time 19488710 ps
CPU time 0.65 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 194312 kb
Host smart-5f1f3331-b6e8-4eef-9c02-5a1212cc2ce3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219779012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3219779012
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1255750903
Short name T373
Test name
Test status
Simulation time 78367180 ps
CPU time 2.99 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:04 PM PDT 24
Peak memory 198028 kb
Host smart-bbbfdc35-4e2d-4d66-b2ba-c8a09274d311
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255750903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1255750903
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3431323898
Short name T26
Test name
Test status
Simulation time 156604629 ps
CPU time 3.28 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 196488 kb
Host smart-feef1e5a-22cc-4b0a-a64b-6d5926737346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431323898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3431323898
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.4076432071
Short name T310
Test name
Test status
Simulation time 113874366 ps
CPU time 1.14 seconds
Started May 12 01:44:53 PM PDT 24
Finished May 12 01:44:56 PM PDT 24
Peak memory 196544 kb
Host smart-991d1f7c-0b03-4f19-9677-d69b2fe3b89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076432071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.4076432071
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3534416121
Short name T463
Test name
Test status
Simulation time 16143381 ps
CPU time 0.76 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 196184 kb
Host smart-990b3c66-c155-40db-8230-6835573285e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534416121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3534416121
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3286845534
Short name T698
Test name
Test status
Simulation time 558291456 ps
CPU time 3.43 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 197988 kb
Host smart-4d726b41-76d7-46e2-887e-5e9a8a88ba9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286845534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3286845534
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3298936655
Short name T113
Test name
Test status
Simulation time 68245032 ps
CPU time 1.33 seconds
Started May 12 01:44:55 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 196232 kb
Host smart-5648aea5-90c5-44f9-855c-07efffca7afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298936655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3298936655
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2249416795
Short name T564
Test name
Test status
Simulation time 205668473 ps
CPU time 0.95 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 01:45:00 PM PDT 24
Peak memory 195648 kb
Host smart-95f201f7-ccba-45e5-9819-d3922f819d37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249416795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2249416795
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3178577678
Short name T298
Test name
Test status
Simulation time 12726315714 ps
CPU time 88.63 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:46:29 PM PDT 24
Peak memory 198160 kb
Host smart-bd3629c3-bac4-4ef6-91e6-343fc4496623
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178577678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3178577678
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2512036973
Short name T11
Test name
Test status
Simulation time 291067608447 ps
CPU time 1677.43 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 02:12:53 PM PDT 24
Peak memory 198204 kb
Host smart-976b23a5-b20e-483e-86e0-d6a5edf734ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2512036973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2512036973
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3049499392
Short name T586
Test name
Test status
Simulation time 43169053 ps
CPU time 0.6 seconds
Started May 12 01:44:14 PM PDT 24
Finished May 12 01:44:16 PM PDT 24
Peak memory 193836 kb
Host smart-7a8f571b-4a80-413d-9133-b6440adcea0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049499392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3049499392
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1271477343
Short name T532
Test name
Test status
Simulation time 37623548 ps
CPU time 0.9 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:13 PM PDT 24
Peak memory 195792 kb
Host smart-b7e142a6-a18a-4885-ba21-2a38f663be08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271477343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1271477343
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3835299921
Short name T342
Test name
Test status
Simulation time 741943013 ps
CPU time 18.06 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:30 PM PDT 24
Peak memory 196652 kb
Host smart-f465e3f4-c275-4a73-8512-3275e97a2990
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835299921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3835299921
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.462230724
Short name T143
Test name
Test status
Simulation time 51564370 ps
CPU time 0.71 seconds
Started May 12 01:44:09 PM PDT 24
Finished May 12 01:44:11 PM PDT 24
Peak memory 194600 kb
Host smart-c734ecae-41a5-4589-8987-10bc201fef22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462230724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.462230724
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2828441994
Short name T165
Test name
Test status
Simulation time 91539613 ps
CPU time 0.79 seconds
Started May 12 01:44:10 PM PDT 24
Finished May 12 01:44:11 PM PDT 24
Peak memory 196364 kb
Host smart-6edf1711-e81e-4b3c-b054-310687c2a409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828441994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2828441994
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1776609138
Short name T368
Test name
Test status
Simulation time 62242844 ps
CPU time 2.24 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 196340 kb
Host smart-7bc3de0e-1bd1-49a8-9fa2-775d640aef30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776609138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1776609138
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.630651570
Short name T502
Test name
Test status
Simulation time 134872453 ps
CPU time 2.1 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 196488 kb
Host smart-82503eb3-e4ea-4202-9f89-02ffc03dab33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630651570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.630651570
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1753914513
Short name T394
Test name
Test status
Simulation time 32394556 ps
CPU time 1.29 seconds
Started May 12 01:44:14 PM PDT 24
Finished May 12 01:44:16 PM PDT 24
Peak memory 197012 kb
Host smart-5eed0945-0bf2-44ac-9c2f-7524023e62f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753914513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1753914513
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2531179632
Short name T616
Test name
Test status
Simulation time 21663469 ps
CPU time 0.68 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 194272 kb
Host smart-65f453ce-14f1-4f9b-b12d-a373a37c79de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531179632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2531179632
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.4007093402
Short name T696
Test name
Test status
Simulation time 127286376 ps
CPU time 2.98 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:17 PM PDT 24
Peak memory 197996 kb
Host smart-83ad5547-4094-40a4-a2b2-6a8f12b2b8ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007093402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.4007093402
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.4014080573
Short name T37
Test name
Test status
Simulation time 83048496 ps
CPU time 0.99 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:13 PM PDT 24
Peak memory 215144 kb
Host smart-d54b53cb-4df8-42b9-91d5-740abb2490f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014080573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.4014080573
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.4293657224
Short name T30
Test name
Test status
Simulation time 59372544 ps
CPU time 1.12 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 196212 kb
Host smart-906247bc-518b-4f44-8598-121de906a224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293657224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.4293657224
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2291936142
Short name T438
Test name
Test status
Simulation time 24827225 ps
CPU time 0.73 seconds
Started May 12 01:44:14 PM PDT 24
Finished May 12 01:44:16 PM PDT 24
Peak memory 194888 kb
Host smart-17587eaa-4de0-44a2-b3aa-112a8b8e07f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291936142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2291936142
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1295510320
Short name T410
Test name
Test status
Simulation time 38217868654 ps
CPU time 143.42 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:46:37 PM PDT 24
Peak memory 198176 kb
Host smart-fbde7bb4-16fd-4342-9db0-365660729585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295510320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1295510320
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1843758224
Short name T147
Test name
Test status
Simulation time 58371785 ps
CPU time 0.61 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 193880 kb
Host smart-437b31b5-f8f1-4e1c-9b30-540e22618c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843758224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1843758224
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2409434861
Short name T289
Test name
Test status
Simulation time 20181732 ps
CPU time 0.63 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 194084 kb
Host smart-b74fd925-6c5b-4097-b146-4d60f7be9f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409434861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2409434861
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3692903883
Short name T605
Test name
Test status
Simulation time 176983277 ps
CPU time 8.88 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:10 PM PDT 24
Peak memory 196660 kb
Host smart-6c3ff5b8-37dd-4265-a3ff-25e21f67c5b2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692903883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3692903883
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3128302146
Short name T24
Test name
Test status
Simulation time 852370694 ps
CPU time 1.06 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:44:59 PM PDT 24
Peak memory 196312 kb
Host smart-7eb19bd5-b040-44a4-a0fb-6446a25d88af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128302146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3128302146
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3394976196
Short name T319
Test name
Test status
Simulation time 47739827 ps
CPU time 0.94 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:04 PM PDT 24
Peak memory 195708 kb
Host smart-2571d2cb-5605-405c-9055-b09d04acd6c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394976196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3394976196
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1093135702
Short name T224
Test name
Test status
Simulation time 171219343 ps
CPU time 3.28 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 196312 kb
Host smart-31dcdde3-8e80-4b46-9b2c-81723d3991c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093135702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1093135702
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3359824292
Short name T86
Test name
Test status
Simulation time 392401586 ps
CPU time 2.34 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 195824 kb
Host smart-ac5ca280-42a6-4aaa-b2e0-8f3142e2ef01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359824292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3359824292
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3164757433
Short name T105
Test name
Test status
Simulation time 304119127 ps
CPU time 0.81 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 196452 kb
Host smart-568c5580-321f-479b-b646-225cc7a74c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164757433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3164757433
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3147516445
Short name T209
Test name
Test status
Simulation time 18588842 ps
CPU time 0.87 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 196604 kb
Host smart-5d353fb3-2a46-48f4-aa0c-79e3320e6fb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147516445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3147516445
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.4139491846
Short name T207
Test name
Test status
Simulation time 103446233 ps
CPU time 4.66 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 198008 kb
Host smart-a514e2f9-b8f5-488b-a033-9b77c297fd28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139491846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.4139491846
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2982443611
Short name T685
Test name
Test status
Simulation time 42533806 ps
CPU time 1.14 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:45:07 PM PDT 24
Peak memory 195840 kb
Host smart-82d777da-43bc-48ef-ae0c-9a1abb8af600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982443611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2982443611
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1934550094
Short name T149
Test name
Test status
Simulation time 55954564 ps
CPU time 1.23 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 195784 kb
Host smart-2c82e686-8941-418d-be21-b9ab26196b44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934550094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1934550094
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2223359113
Short name T124
Test name
Test status
Simulation time 19011161267 ps
CPU time 77.57 seconds
Started May 12 01:44:57 PM PDT 24
Finished May 12 01:46:15 PM PDT 24
Peak memory 198196 kb
Host smart-11eeeb83-dc7f-4562-8fd3-0e7e3e127713
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223359113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2223359113
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3329931168
Short name T603
Test name
Test status
Simulation time 99194308362 ps
CPU time 1731.22 seconds
Started May 12 01:44:54 PM PDT 24
Finished May 12 02:13:47 PM PDT 24
Peak memory 198204 kb
Host smart-b0663b4d-7466-42a8-a65d-5382b5564bf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3329931168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3329931168
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.4230603554
Short name T217
Test name
Test status
Simulation time 38443509 ps
CPU time 0.59 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 01:45:00 PM PDT 24
Peak memory 194080 kb
Host smart-05c1738b-90c6-4613-b0d4-84efbf4368df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230603554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4230603554
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.926049339
Short name T439
Test name
Test status
Simulation time 12596277 ps
CPU time 0.63 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 194568 kb
Host smart-46fe79f1-1f94-47d8-b8f7-0e3410df720e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926049339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.926049339
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.4013689242
Short name T225
Test name
Test status
Simulation time 579714950 ps
CPU time 18.88 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:26 PM PDT 24
Peak memory 197948 kb
Host smart-63df0efd-e299-421e-aab3-f8aafeffafbb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013689242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.4013689242
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1040033294
Short name T216
Test name
Test status
Simulation time 128320201 ps
CPU time 0.84 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:04 PM PDT 24
Peak memory 196384 kb
Host smart-a1ea0d50-5cdf-4609-90b0-fadf1aed2234
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040033294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1040033294
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1823303183
Short name T709
Test name
Test status
Simulation time 192974414 ps
CPU time 1.38 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:09 PM PDT 24
Peak memory 198056 kb
Host smart-4372a1ab-70df-4829-9a41-217a22f39036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823303183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1823303183
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3965346548
Short name T414
Test name
Test status
Simulation time 35121980 ps
CPU time 1.2 seconds
Started May 12 01:45:07 PM PDT 24
Finished May 12 01:45:09 PM PDT 24
Peak memory 196396 kb
Host smart-5eb6cc92-251a-49f3-9983-4ec5f0c97d6e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965346548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3965346548
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.732361242
Short name T604
Test name
Test status
Simulation time 216068620 ps
CPU time 2.11 seconds
Started May 12 01:45:07 PM PDT 24
Finished May 12 01:45:10 PM PDT 24
Peak memory 195708 kb
Host smart-12bc913b-27e7-411a-bb5a-dc73d9be0819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732361242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
732361242
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2267600355
Short name T333
Test name
Test status
Simulation time 21458401 ps
CPU time 0.84 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:57 PM PDT 24
Peak memory 196652 kb
Host smart-57396afa-8324-45d5-841a-090f36c3f3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267600355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2267600355
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2588808372
Short name T547
Test name
Test status
Simulation time 164314583 ps
CPU time 1.05 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 196540 kb
Host smart-2290f7a5-a06f-4cde-93b0-a4bafbc58ca9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588808372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2588808372
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2038799337
Short name T404
Test name
Test status
Simulation time 84983569 ps
CPU time 1.24 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 197896 kb
Host smart-38553266-2277-41b9-b0d6-90b6839ef4da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038799337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2038799337
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3770551820
Short name T395
Test name
Test status
Simulation time 37448211 ps
CPU time 1.08 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:02 PM PDT 24
Peak memory 195664 kb
Host smart-a96c4b37-08fa-4c84-9375-a8f8cb5777bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770551820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3770551820
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2725257815
Short name T357
Test name
Test status
Simulation time 586424484 ps
CPU time 1.03 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 197332 kb
Host smart-e381f5ab-dff0-4b97-a59e-ed8d37de0bcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725257815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2725257815
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2721268557
Short name T589
Test name
Test status
Simulation time 39672630501 ps
CPU time 139.35 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:47:19 PM PDT 24
Peak memory 198124 kb
Host smart-fa5e01d6-41b0-4231-b525-19a28119c1ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721268557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2721268557
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.523526154
Short name T384
Test name
Test status
Simulation time 23676941 ps
CPU time 0.57 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:07 PM PDT 24
Peak memory 194096 kb
Host smart-7e190ea8-6959-4f52-8d3f-e9dce9d78a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523526154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.523526154
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.882830171
Short name T600
Test name
Test status
Simulation time 57617938 ps
CPU time 0.65 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 194556 kb
Host smart-33aec2e2-9475-4e94-b263-d0b453aa1927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882830171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.882830171
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2157396829
Short name T503
Test name
Test status
Simulation time 2569236290 ps
CPU time 18.75 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:19 PM PDT 24
Peak memory 196628 kb
Host smart-2f6c1e1a-7f40-4d8a-abd6-a117dcaa4a1d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157396829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2157396829
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1194937277
Short name T446
Test name
Test status
Simulation time 64894787 ps
CPU time 0.83 seconds
Started May 12 01:44:56 PM PDT 24
Finished May 12 01:44:58 PM PDT 24
Peak memory 195960 kb
Host smart-905edc33-fc4b-4558-bf0a-0de4185eb6cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194937277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1194937277
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3454973449
Short name T186
Test name
Test status
Simulation time 365514589 ps
CPU time 1.34 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:02 PM PDT 24
Peak memory 197024 kb
Host smart-a9bdcfe2-9f2a-4e46-a7a8-3cec9a57cc0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454973449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3454973449
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.855537209
Short name T467
Test name
Test status
Simulation time 227744740 ps
CPU time 3.13 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 01:45:02 PM PDT 24
Peak memory 198052 kb
Host smart-eabdc9cf-c990-4175-a6a4-f74e68f94890
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855537209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.855537209
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2371302229
Short name T700
Test name
Test status
Simulation time 85930577 ps
CPU time 1.85 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:04 PM PDT 24
Peak memory 195804 kb
Host smart-15b32f83-a8c8-48b9-80d2-804d9418b824
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371302229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2371302229
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2012587773
Short name T702
Test name
Test status
Simulation time 233427780 ps
CPU time 1.23 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 196080 kb
Host smart-bb14373c-b454-4bdd-afc1-1b61869ffa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012587773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2012587773
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2340672184
Short name T303
Test name
Test status
Simulation time 104813469 ps
CPU time 1.07 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 195828 kb
Host smart-75fb051c-936a-44c3-a963-99ca5d75227e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340672184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2340672184
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2691149737
Short name T285
Test name
Test status
Simulation time 101552609 ps
CPU time 2.4 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 197940 kb
Host smart-51b85a72-446d-4ba9-b45e-c2ef2c2c609a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691149737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2691149737
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3986263426
Short name T498
Test name
Test status
Simulation time 65505892 ps
CPU time 1.22 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 195540 kb
Host smart-3c5df584-5612-450b-a60c-015a883b647a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986263426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3986263426
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3413854341
Short name T559
Test name
Test status
Simulation time 100054422 ps
CPU time 0.9 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 195816 kb
Host smart-ed758d78-17d7-4724-8914-eb54d003622e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413854341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3413854341
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4196849030
Short name T168
Test name
Test status
Simulation time 10029544678 ps
CPU time 112.68 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:46:56 PM PDT 24
Peak memory 198148 kb
Host smart-e9a83eaa-be3c-47ba-9275-32f071f7fa81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196849030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4196849030
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3157641327
Short name T204
Test name
Test status
Simulation time 23720318 ps
CPU time 0.58 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:02 PM PDT 24
Peak memory 194784 kb
Host smart-178b40fa-bc48-4986-938b-3ac4c766515b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157641327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3157641327
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3225303482
Short name T377
Test name
Test status
Simulation time 30556382 ps
CPU time 0.83 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 196112 kb
Host smart-c74c4e8b-7d13-41b4-950b-23ba24ece478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225303482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3225303482
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2622190613
Short name T227
Test name
Test status
Simulation time 425642010 ps
CPU time 12.56 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:15 PM PDT 24
Peak memory 198224 kb
Host smart-6e1e2944-253a-4a2a-a3b4-182ba02ef4d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622190613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2622190613
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.771848458
Short name T531
Test name
Test status
Simulation time 89468711 ps
CPU time 0.99 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 196384 kb
Host smart-86eb4fb6-e2fe-40bc-914c-00fab89c7718
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771848458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.771848458
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2839440319
Short name T268
Test name
Test status
Simulation time 23286592 ps
CPU time 0.75 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 195532 kb
Host smart-8701f18e-4d18-47e1-86dc-312056e2ac04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839440319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2839440319
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.350185027
Short name T229
Test name
Test status
Simulation time 356315074 ps
CPU time 3.36 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 198112 kb
Host smart-23cd33db-e626-41aa-8281-311b4891c88e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350185027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.350185027
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1898123571
Short name T713
Test name
Test status
Simulation time 479251691 ps
CPU time 2.64 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 01:45:02 PM PDT 24
Peak memory 195760 kb
Host smart-71da2d3e-02fb-40a2-84d7-ed0a8ea47c39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898123571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1898123571
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1479871772
Short name T228
Test name
Test status
Simulation time 21476220 ps
CPU time 0.89 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:45:07 PM PDT 24
Peak memory 196636 kb
Host smart-8b445fe2-99eb-426f-8b74-1aaeef35c903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479871772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1479871772
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4281246240
Short name T506
Test name
Test status
Simulation time 54578127 ps
CPU time 1.07 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:45:06 PM PDT 24
Peak memory 195948 kb
Host smart-69d5d9ec-22db-4a4c-82e5-02fd080f3fb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281246240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4281246240
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1095772288
Short name T356
Test name
Test status
Simulation time 646297591 ps
CPU time 4.25 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 197944 kb
Host smart-31b9e395-fa7e-4792-9d78-98e1b13731ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095772288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1095772288
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2564698087
Short name T191
Test name
Test status
Simulation time 41276109 ps
CPU time 0.98 seconds
Started May 12 01:44:58 PM PDT 24
Finished May 12 01:45:00 PM PDT 24
Peak memory 196556 kb
Host smart-8a48839d-8bca-4334-88e8-3c6b22d072f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564698087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2564698087
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3621369128
Short name T193
Test name
Test status
Simulation time 130445123 ps
CPU time 1.05 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:04 PM PDT 24
Peak memory 195500 kb
Host smart-ff066166-e3b6-4e70-bb8b-fa780695d7c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621369128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3621369128
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2628887976
Short name T415
Test name
Test status
Simulation time 5909132926 ps
CPU time 153.94 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:47:37 PM PDT 24
Peak memory 198164 kb
Host smart-8bffb71d-eeb3-4e81-9682-c818d58fd82b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628887976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2628887976
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1443165442
Short name T302
Test name
Test status
Simulation time 39369000 ps
CPU time 0.58 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 193928 kb
Host smart-7d8e4aad-6565-45e3-8282-b31a184d17e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443165442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1443165442
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.1444361624
Short name T364
Test name
Test status
Simulation time 76091554 ps
CPU time 0.84 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 195516 kb
Host smart-8930ae40-7065-4997-b1ec-5b269723bd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444361624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.1444361624
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2184028225
Short name T392
Test name
Test status
Simulation time 653772840 ps
CPU time 10.66 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:45:16 PM PDT 24
Peak memory 195416 kb
Host smart-87605e39-5f0e-4c60-9a4d-5e92331ceb44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184028225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2184028225
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2319033163
Short name T365
Test name
Test status
Simulation time 224188478 ps
CPU time 0.8 seconds
Started May 12 01:45:14 PM PDT 24
Finished May 12 01:45:15 PM PDT 24
Peak memory 195800 kb
Host smart-4adcd279-dd8b-4569-8ad0-8e0d083ac6f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319033163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2319033163
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1306101622
Short name T575
Test name
Test status
Simulation time 87236022 ps
CPU time 1.25 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 196812 kb
Host smart-2a668ce0-346d-4aa7-8972-af7e888a7870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306101622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1306101622
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1061859408
Short name T145
Test name
Test status
Simulation time 299577479 ps
CPU time 3.45 seconds
Started May 12 01:45:10 PM PDT 24
Finished May 12 01:45:14 PM PDT 24
Peak memory 198052 kb
Host smart-6fdd0148-c4c9-4887-bcb0-90436f4a6fc4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061859408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1061859408
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1970547354
Short name T594
Test name
Test status
Simulation time 182519794 ps
CPU time 1.62 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:06 PM PDT 24
Peak memory 196496 kb
Host smart-8b1a343d-79c8-43d7-b8b0-b284bb1c64cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970547354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1970547354
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3752531282
Short name T375
Test name
Test status
Simulation time 21389556 ps
CPU time 0.69 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:04 PM PDT 24
Peak memory 194252 kb
Host smart-60c7ec3e-f3bb-424e-933b-3d77e9c96053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752531282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3752531282
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1645575749
Short name T544
Test name
Test status
Simulation time 57701269 ps
CPU time 1.06 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 195956 kb
Host smart-1a288cd8-cdfa-48e6-8bd5-9b5f3c8ee0c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645575749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1645575749
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.4187679805
Short name T553
Test name
Test status
Simulation time 436331483 ps
CPU time 2.72 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:04 PM PDT 24
Peak memory 197888 kb
Host smart-d58ba535-ef69-43d0-a1d4-bd0ea421fbc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187679805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.4187679805
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3058465527
Short name T12
Test name
Test status
Simulation time 52296595 ps
CPU time 1.31 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 196208 kb
Host smart-62b94cc8-e878-4b3c-86e3-4413bbdcc5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058465527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3058465527
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2442211038
Short name T440
Test name
Test status
Simulation time 486697971 ps
CPU time 1.19 seconds
Started May 12 01:44:59 PM PDT 24
Finished May 12 01:45:01 PM PDT 24
Peak memory 195572 kb
Host smart-f034b4a7-0a20-4298-9b05-ba5c07271124
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442211038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2442211038
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3989810061
Short name T254
Test name
Test status
Simulation time 25811262941 ps
CPU time 177.01 seconds
Started May 12 01:45:07 PM PDT 24
Finished May 12 01:48:05 PM PDT 24
Peak memory 198144 kb
Host smart-7af3ed0a-3a26-4f17-ac17-ccabc5d0847f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989810061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3989810061
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.479348775
Short name T386
Test name
Test status
Simulation time 116522774878 ps
CPU time 610.28 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:55:13 PM PDT 24
Peak memory 198276 kb
Host smart-5916f7fd-47ed-42ee-ba49-5ecdb9739700
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=479348775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.479348775
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.4217444260
Short name T41
Test name
Test status
Simulation time 19249940 ps
CPU time 0.58 seconds
Started May 12 01:45:09 PM PDT 24
Finished May 12 01:45:10 PM PDT 24
Peak memory 194096 kb
Host smart-7c540fab-dd5c-456f-9ee2-4621d787b669
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217444260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.4217444260
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2060224252
Short name T614
Test name
Test status
Simulation time 46646825 ps
CPU time 0.67 seconds
Started May 12 01:45:14 PM PDT 24
Finished May 12 01:45:15 PM PDT 24
Peak memory 194748 kb
Host smart-f3affe4e-00d8-4480-9a1b-a2b4beb8f86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060224252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2060224252
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.3996873832
Short name T18
Test name
Test status
Simulation time 596215794 ps
CPU time 8.27 seconds
Started May 12 01:45:01 PM PDT 24
Finished May 12 01:45:11 PM PDT 24
Peak memory 197200 kb
Host smart-9322cf2a-9497-42a2-a5a5-bcde83300dc2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996873832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.3996873832
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3251773855
Short name T527
Test name
Test status
Simulation time 86731434 ps
CPU time 0.93 seconds
Started May 12 01:45:14 PM PDT 24
Finished May 12 01:45:15 PM PDT 24
Peak memory 196380 kb
Host smart-75c3c5e5-868f-4227-9277-0e25172337b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251773855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3251773855
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2458172882
Short name T174
Test name
Test status
Simulation time 291406526 ps
CPU time 1.34 seconds
Started May 12 01:45:12 PM PDT 24
Finished May 12 01:45:14 PM PDT 24
Peak memory 197316 kb
Host smart-a0463bf9-00b0-4e96-a122-edbb8dd1f2f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458172882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2458172882
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.4124696028
Short name T99
Test name
Test status
Simulation time 23391897 ps
CPU time 1 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 196188 kb
Host smart-f317aaa0-dfce-4a6b-9a3c-948abe0887e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124696028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.4124696028
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.2837965984
Short name T84
Test name
Test status
Simulation time 84478466 ps
CPU time 1.75 seconds
Started May 12 01:45:19 PM PDT 24
Finished May 12 01:45:21 PM PDT 24
Peak memory 196388 kb
Host smart-c3f67fc2-a620-42f1-ab55-67887ffe829e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837965984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.2837965984
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3513488431
Short name T622
Test name
Test status
Simulation time 94770463 ps
CPU time 0.98 seconds
Started May 12 01:45:24 PM PDT 24
Finished May 12 01:45:25 PM PDT 24
Peak memory 195872 kb
Host smart-3fe41b76-caa1-4c98-8028-a47f3fd2176f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513488431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3513488431
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2385725466
Short name T110
Test name
Test status
Simulation time 111817746 ps
CPU time 1.18 seconds
Started May 12 01:45:00 PM PDT 24
Finished May 12 01:45:03 PM PDT 24
Peak memory 197252 kb
Host smart-abfe6eb6-9496-4bb8-b0de-63b2b7384d80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385725466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2385725466
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3130384453
Short name T687
Test name
Test status
Simulation time 373958501 ps
CPU time 4.67 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 198036 kb
Host smart-1531e3e2-93cc-411f-a23b-57819c1ba4f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130384453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3130384453
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1557768068
Short name T275
Test name
Test status
Simulation time 143324114 ps
CPU time 1.21 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:06 PM PDT 24
Peak memory 197952 kb
Host smart-c82009a2-e6e3-4ba0-aa62-9bf6fed4ed2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557768068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1557768068
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3899787823
Short name T560
Test name
Test status
Simulation time 251512464 ps
CPU time 1.16 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:06 PM PDT 24
Peak memory 195716 kb
Host smart-5a64c562-8586-47bf-a289-2962ef79b38c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899787823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3899787823
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2980508805
Short name T146
Test name
Test status
Simulation time 3493812196 ps
CPU time 25.26 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:29 PM PDT 24
Peak memory 198128 kb
Host smart-79748847-d0e5-485d-be4a-626e71443912
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980508805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2980508805
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2393427643
Short name T639
Test name
Test status
Simulation time 183033111 ps
CPU time 0.57 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:04 PM PDT 24
Peak memory 193868 kb
Host smart-2b3cc986-b9d3-40b9-89be-52e1456bd89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393427643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2393427643
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.139647506
Short name T380
Test name
Test status
Simulation time 45360395 ps
CPU time 0.82 seconds
Started May 12 01:45:08 PM PDT 24
Finished May 12 01:45:10 PM PDT 24
Peak memory 195504 kb
Host smart-06658897-12ee-47c1-8812-48c994836473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139647506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.139647506
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.177102496
Short name T339
Test name
Test status
Simulation time 927807357 ps
CPU time 25.84 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:29 PM PDT 24
Peak memory 196912 kb
Host smart-c8444694-5ec6-4a03-a0ee-587e4c4ecf54
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177102496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.177102496
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1906822695
Short name T571
Test name
Test status
Simulation time 95199945 ps
CPU time 1.09 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:06 PM PDT 24
Peak memory 196504 kb
Host smart-6d3c32a6-5d82-4e0d-9939-b59777367fa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906822695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1906822695
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1636275112
Short name T718
Test name
Test status
Simulation time 66990819 ps
CPU time 0.99 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 196620 kb
Host smart-9c36d9d9-1414-43f9-b72a-c3bd6b7a088b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636275112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1636275112
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.638065791
Short name T160
Test name
Test status
Simulation time 65806210 ps
CPU time 2.32 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:09 PM PDT 24
Peak memory 198020 kb
Host smart-40ebad7e-ae74-44ab-9d07-8c88098f9cc8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638065791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.638065791
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2339578477
Short name T644
Test name
Test status
Simulation time 53460182 ps
CPU time 1.31 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:06 PM PDT 24
Peak memory 196780 kb
Host smart-c3d6b19f-0896-40be-8ee7-d7c13738bec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339578477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2339578477
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1019323542
Short name T90
Test name
Test status
Simulation time 74003805 ps
CPU time 1.02 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:45:06 PM PDT 24
Peak memory 195992 kb
Host smart-eaab9a33-1965-4d17-a694-bb3ba74ae119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019323542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1019323542
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3954481788
Short name T220
Test name
Test status
Simulation time 242555264 ps
CPU time 1.19 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:45:06 PM PDT 24
Peak memory 196088 kb
Host smart-6c698348-a3aa-4809-814d-2a63bc82209b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954481788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3954481788
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.13804568
Short name T231
Test name
Test status
Simulation time 1169422318 ps
CPU time 5.22 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:11 PM PDT 24
Peak memory 197968 kb
Host smart-3fda6507-da45-43ad-9a84-f01b6e79211d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13804568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand
om_long_reg_writes_reg_reads.13804568
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1063102188
Short name T471
Test name
Test status
Simulation time 146844059 ps
CPU time 1.07 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 195768 kb
Host smart-74a58e4a-8f4e-48c2-a251-9c76d81892ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063102188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1063102188
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.4245631234
Short name T443
Test name
Test status
Simulation time 141790006 ps
CPU time 1.23 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 196908 kb
Host smart-83abee2f-b299-4f30-9b35-bcbac9c1e8e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245631234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.4245631234
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3117354311
Short name T452
Test name
Test status
Simulation time 17277242168 ps
CPU time 214.68 seconds
Started May 12 01:45:09 PM PDT 24
Finished May 12 01:48:44 PM PDT 24
Peak memory 198184 kb
Host smart-65f97214-4de0-470c-8b56-2da38835c166
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117354311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3117354311
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3717522189
Short name T584
Test name
Test status
Simulation time 59686873034 ps
CPU time 211.34 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:48:36 PM PDT 24
Peak memory 198184 kb
Host smart-d89b546c-162e-4b1b-b4d9-cae5b4fcd0f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3717522189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3717522189
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2286340749
Short name T500
Test name
Test status
Simulation time 32498570 ps
CPU time 0.58 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:07 PM PDT 24
Peak memory 193916 kb
Host smart-cc5d5e5e-961b-420f-b551-ddf758882f64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286340749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2286340749
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.43817370
Short name T175
Test name
Test status
Simulation time 84431798 ps
CPU time 0.88 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 196016 kb
Host smart-35527309-6505-476c-998a-17115ca63d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43817370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.43817370
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.737970465
Short name T301
Test name
Test status
Simulation time 553064436 ps
CPU time 13.9 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:21 PM PDT 24
Peak memory 195500 kb
Host smart-fd0eb71a-c1d6-4c66-93a5-3ac9cd3cb75d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737970465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.737970465
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3551940613
Short name T641
Test name
Test status
Simulation time 49440025 ps
CPU time 0.87 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:07 PM PDT 24
Peak memory 197712 kb
Host smart-e6d08e01-1373-4255-8ccb-1e9525ccd754
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551940613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3551940613
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2711839004
Short name T619
Test name
Test status
Simulation time 151700162 ps
CPU time 1.27 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 196772 kb
Host smart-1ac38acc-0043-46be-9de2-3ce91f39d2bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711839004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2711839004
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1359196323
Short name T320
Test name
Test status
Simulation time 20798326 ps
CPU time 0.98 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 196208 kb
Host smart-6a1300fe-0b72-4c92-bc89-b13769b2790f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359196323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1359196323
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3362942740
Short name T486
Test name
Test status
Simulation time 140618477 ps
CPU time 2.25 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 197156 kb
Host smart-49d50afe-1424-4d28-a26f-db9693ca1657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362942740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3362942740
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3887924054
Short name T242
Test name
Test status
Simulation time 18297745 ps
CPU time 0.75 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 196036 kb
Host smart-cde2da90-e829-4355-82e1-51605f617a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887924054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3887924054
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.611890841
Short name T542
Test name
Test status
Simulation time 19554596 ps
CPU time 0.73 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:07 PM PDT 24
Peak memory 196132 kb
Host smart-e28a6ac8-69bd-4dce-8ee7-abb0e6e9133d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611890841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.611890841
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.321582680
Short name T118
Test name
Test status
Simulation time 383817205 ps
CPU time 4.5 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:45:10 PM PDT 24
Peak memory 198040 kb
Host smart-ec50db9b-17cd-4479-a42b-8d12fa599dee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321582680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.321582680
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.158114093
Short name T517
Test name
Test status
Simulation time 249002747 ps
CPU time 1.11 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:07 PM PDT 24
Peak memory 195496 kb
Host smart-4fc49ed0-a7c6-4e7d-adb6-0f9dcc1b66eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158114093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.158114093
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2567398903
Short name T167
Test name
Test status
Simulation time 51484393 ps
CPU time 1.36 seconds
Started May 12 01:45:02 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 196696 kb
Host smart-1351d69d-2f53-4467-867f-059b941eab62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567398903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2567398903
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.535591483
Short name T164
Test name
Test status
Simulation time 13579826411 ps
CPU time 174.38 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:48:01 PM PDT 24
Peak memory 198120 kb
Host smart-ee1079e6-dd1a-4ec5-8461-b9df5e1f5574
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535591483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.535591483
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2669932333
Short name T648
Test name
Test status
Simulation time 19497256621 ps
CPU time 274.24 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:49:40 PM PDT 24
Peak memory 198292 kb
Host smart-38dbfbef-f551-4f40-a2ff-aab905e1d344
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2669932333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2669932333
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.34135199
Short name T661
Test name
Test status
Simulation time 13674717 ps
CPU time 0.61 seconds
Started May 12 01:45:20 PM PDT 24
Finished May 12 01:45:21 PM PDT 24
Peak memory 194792 kb
Host smart-de117a60-4157-473c-bda3-4d4a6bc772e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34135199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.34135199
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2912204788
Short name T673
Test name
Test status
Simulation time 16100966 ps
CPU time 0.66 seconds
Started May 12 01:45:08 PM PDT 24
Finished May 12 01:45:09 PM PDT 24
Peak memory 194132 kb
Host smart-ce902f8a-8339-42c9-be10-56f780d0400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912204788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2912204788
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1495524609
Short name T400
Test name
Test status
Simulation time 442477101 ps
CPU time 11.04 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:18 PM PDT 24
Peak memory 197072 kb
Host smart-69607e84-f608-4120-8c1c-8889554a3d9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495524609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1495524609
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1164434167
Short name T635
Test name
Test status
Simulation time 77117261 ps
CPU time 0.8 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 195960 kb
Host smart-4424a0eb-f583-4819-8216-a7a65cab9a26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164434167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1164434167
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3342179932
Short name T583
Test name
Test status
Simulation time 54405361 ps
CPU time 1.02 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:45:06 PM PDT 24
Peak memory 196172 kb
Host smart-1cbd6a80-e20c-4ab7-acb1-20e94ea751fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342179932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3342179932
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.4078259355
Short name T194
Test name
Test status
Simulation time 87642686 ps
CPU time 1.05 seconds
Started May 12 01:45:03 PM PDT 24
Finished May 12 01:45:05 PM PDT 24
Peak memory 196100 kb
Host smart-c36dc6be-7d28-415a-8307-ea9c11e23bb1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078259355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.4078259355
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1376445535
Short name T520
Test name
Test status
Simulation time 368814858 ps
CPU time 3.29 seconds
Started May 12 01:45:07 PM PDT 24
Finished May 12 01:45:11 PM PDT 24
Peak memory 197256 kb
Host smart-88067244-0c31-46b6-a620-7264bdf76210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376445535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1376445535
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3719271421
Short name T180
Test name
Test status
Simulation time 25063038 ps
CPU time 0.86 seconds
Started May 12 01:45:14 PM PDT 24
Finished May 12 01:45:15 PM PDT 24
Peak memory 196604 kb
Host smart-d29e4c30-e369-4a8f-9dd6-f9fe1e1e9ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719271421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3719271421
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3271742799
Short name T151
Test name
Test status
Simulation time 126939383 ps
CPU time 1.28 seconds
Started May 12 01:45:05 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 196928 kb
Host smart-f4f8beb0-da1d-4b74-a1ab-ad5667c48efa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271742799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3271742799
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1805378925
Short name T381
Test name
Test status
Simulation time 310939364 ps
CPU time 3.59 seconds
Started May 12 01:45:21 PM PDT 24
Finished May 12 01:45:25 PM PDT 24
Peak memory 198024 kb
Host smart-7a59ec26-fd8e-496b-a6c6-a88493ccf06f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805378925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1805378925
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3874745700
Short name T88
Test name
Test status
Simulation time 922494796 ps
CPU time 0.97 seconds
Started May 12 01:45:06 PM PDT 24
Finished May 12 01:45:08 PM PDT 24
Peak memory 195828 kb
Host smart-396ea09e-982b-4b11-8267-2c57959fbe5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874745700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3874745700
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3888807500
Short name T31
Test name
Test status
Simulation time 51068622 ps
CPU time 1.01 seconds
Started May 12 01:45:04 PM PDT 24
Finished May 12 01:45:07 PM PDT 24
Peak memory 196520 kb
Host smart-60564993-6e84-4043-add3-a560e809262a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888807500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3888807500
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.17320296
Short name T387
Test name
Test status
Simulation time 10114911471 ps
CPU time 124.51 seconds
Started May 12 01:45:10 PM PDT 24
Finished May 12 01:47:15 PM PDT 24
Peak memory 198116 kb
Host smart-41aafe03-277f-4d43-b603-d689a81fc5bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17320296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gp
io_stress_all.17320296
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.551443371
Short name T444
Test name
Test status
Simulation time 77648677 ps
CPU time 0.55 seconds
Started May 12 01:45:17 PM PDT 24
Finished May 12 01:45:18 PM PDT 24
Peak memory 194560 kb
Host smart-5ae1e948-965f-483e-a286-c7dbe216bbe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551443371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.551443371
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.394867006
Short name T325
Test name
Test status
Simulation time 51128596 ps
CPU time 0.94 seconds
Started May 12 01:45:12 PM PDT 24
Finished May 12 01:45:13 PM PDT 24
Peak memory 196648 kb
Host smart-49b8f86c-3fed-4dd5-84c1-c52d32de2a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394867006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.394867006
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3173047989
Short name T596
Test name
Test status
Simulation time 334005940 ps
CPU time 10.12 seconds
Started May 12 01:45:13 PM PDT 24
Finished May 12 01:45:24 PM PDT 24
Peak memory 196916 kb
Host smart-eb928071-96bf-424e-8656-2c47ab650597
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173047989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3173047989
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3085566400
Short name T237
Test name
Test status
Simulation time 22458675 ps
CPU time 0.59 seconds
Started May 12 01:45:18 PM PDT 24
Finished May 12 01:45:19 PM PDT 24
Peak memory 194260 kb
Host smart-9f05ca59-0ee1-4aed-b24b-b7f26d41a2af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085566400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3085566400
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.522219624
Short name T420
Test name
Test status
Simulation time 134624650 ps
CPU time 1.07 seconds
Started May 12 01:45:07 PM PDT 24
Finished May 12 01:45:09 PM PDT 24
Peak memory 195964 kb
Host smart-17ce6689-7b1e-4a0c-a03c-4bdd40774a86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522219624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.522219624
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3281687420
Short name T657
Test name
Test status
Simulation time 65848926 ps
CPU time 2.63 seconds
Started May 12 01:45:12 PM PDT 24
Finished May 12 01:45:15 PM PDT 24
Peak memory 198052 kb
Host smart-482b0b54-bb39-48eb-9224-529b06962a58
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281687420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3281687420
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2818637608
Short name T548
Test name
Test status
Simulation time 121443560 ps
CPU time 1.38 seconds
Started May 12 01:45:10 PM PDT 24
Finished May 12 01:45:12 PM PDT 24
Peak memory 196080 kb
Host smart-a1fabc39-0bd9-4180-8ed2-dd52013132b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818637608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2818637608
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1201627741
Short name T177
Test name
Test status
Simulation time 57919587 ps
CPU time 1.23 seconds
Started May 12 01:45:07 PM PDT 24
Finished May 12 01:45:09 PM PDT 24
Peak memory 196560 kb
Host smart-b65c09c1-0976-4cd7-a406-e2a12446836a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201627741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1201627741
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1336854690
Short name T350
Test name
Test status
Simulation time 569314676 ps
CPU time 1.22 seconds
Started May 12 01:45:08 PM PDT 24
Finished May 12 01:45:10 PM PDT 24
Peak memory 198020 kb
Host smart-065e5be1-db5c-40d2-8f13-8e086f3da606
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336854690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1336854690
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1375501430
Short name T627
Test name
Test status
Simulation time 298512329 ps
CPU time 4.8 seconds
Started May 12 01:45:12 PM PDT 24
Finished May 12 01:45:17 PM PDT 24
Peak memory 197856 kb
Host smart-db94a6d7-a6bb-49e0-b450-1ff890b1cb2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375501430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1375501430
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.3451804400
Short name T128
Test name
Test status
Simulation time 131453568 ps
CPU time 1.08 seconds
Started May 12 01:45:08 PM PDT 24
Finished May 12 01:45:10 PM PDT 24
Peak memory 196548 kb
Host smart-52dbf656-0e42-477c-8a3d-0ae4474503e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451804400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.3451804400
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.556005425
Short name T369
Test name
Test status
Simulation time 110841080 ps
CPU time 0.88 seconds
Started May 12 01:45:15 PM PDT 24
Finished May 12 01:45:17 PM PDT 24
Peak memory 196580 kb
Host smart-c45f21f9-3a64-4155-b2c4-da91fafebf3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556005425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.556005425
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4252839082
Short name T669
Test name
Test status
Simulation time 3767256518 ps
CPU time 48.29 seconds
Started May 12 01:45:16 PM PDT 24
Finished May 12 01:46:05 PM PDT 24
Peak memory 198248 kb
Host smart-f27fde78-37a5-409e-8292-ba18ab709dc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252839082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4252839082
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1714425133
Short name T389
Test name
Test status
Simulation time 21437004 ps
CPU time 0.56 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:18 PM PDT 24
Peak memory 193912 kb
Host smart-3263371b-37c9-4e2a-8d2a-3326c694f829
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714425133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1714425133
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1745285690
Short name T447
Test name
Test status
Simulation time 96968821 ps
CPU time 1 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 196700 kb
Host smart-513fbb10-46b9-4fa0-804b-7d59aeb9a183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745285690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1745285690
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2144397933
Short name T294
Test name
Test status
Simulation time 345978932 ps
CPU time 4.7 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 196660 kb
Host smart-9a6af2a6-5f73-4772-bd39-a326dca2a3f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144397933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2144397933
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.172395975
Short name T352
Test name
Test status
Simulation time 64060759 ps
CPU time 0.89 seconds
Started May 12 01:44:14 PM PDT 24
Finished May 12 01:44:16 PM PDT 24
Peak memory 195912 kb
Host smart-e89e0ba8-c52f-422a-beb6-40639a775408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172395975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.172395975
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3262551978
Short name T695
Test name
Test status
Simulation time 212979213 ps
CPU time 1.05 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:18 PM PDT 24
Peak memory 195860 kb
Host smart-575a1ec2-4a60-48ff-a428-94e1391b91e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262551978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3262551978
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2475819909
Short name T536
Test name
Test status
Simulation time 64223031 ps
CPU time 2.41 seconds
Started May 12 01:44:13 PM PDT 24
Finished May 12 01:44:17 PM PDT 24
Peak memory 196492 kb
Host smart-d2878dde-a5f9-45a6-82f7-dc87f3b15a14
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475819909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2475819909
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.4236199217
Short name T291
Test name
Test status
Simulation time 163938096 ps
CPU time 1.79 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 196040 kb
Host smart-3c68b84a-0e1a-4455-9f6e-b1351cc57848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236199217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
4236199217
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.2699313207
Short name T318
Test name
Test status
Simulation time 50709480 ps
CPU time 1.25 seconds
Started May 12 01:44:15 PM PDT 24
Finished May 12 01:44:17 PM PDT 24
Peak memory 196940 kb
Host smart-ac0c2d49-7978-4e0d-95e3-29f83739d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699313207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.2699313207
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2571644045
Short name T501
Test name
Test status
Simulation time 235042173 ps
CPU time 1.14 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 196880 kb
Host smart-2cb005ef-a788-4a61-a83a-72d1807a67f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571644045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2571644045
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3565230037
Short name T638
Test name
Test status
Simulation time 899224930 ps
CPU time 5.76 seconds
Started May 12 01:44:22 PM PDT 24
Finished May 12 01:44:29 PM PDT 24
Peak memory 197996 kb
Host smart-8d30210e-851b-44fa-a391-7fd0da08d826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565230037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3565230037
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_smoke.355589303
Short name T490
Test name
Test status
Simulation time 54574696 ps
CPU time 1.04 seconds
Started May 12 01:44:12 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 195636 kb
Host smart-2c79947a-0b6a-472f-9b25-7c80f99829f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355589303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.355589303
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2468214162
Short name T312
Test name
Test status
Simulation time 56883723 ps
CPU time 0.79 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:13 PM PDT 24
Peak memory 195312 kb
Host smart-ca96ba4b-5d94-44ff-82c1-4104a1108c47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468214162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2468214162
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2754833198
Short name T142
Test name
Test status
Simulation time 6406628621 ps
CPU time 87.74 seconds
Started May 12 01:44:22 PM PDT 24
Finished May 12 01:45:51 PM PDT 24
Peak memory 198092 kb
Host smart-e74a4d2c-a931-4143-bab3-d9f1a00c9167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754833198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2754833198
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2348689192
Short name T33
Test name
Test status
Simulation time 118173426685 ps
CPU time 1731.63 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 02:13:10 PM PDT 24
Peak memory 198244 kb
Host smart-1f4c4140-34bb-40e1-bad2-3b7152b2b816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2348689192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2348689192
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.168462753
Short name T585
Test name
Test status
Simulation time 129316803 ps
CPU time 0.61 seconds
Started May 12 01:45:18 PM PDT 24
Finished May 12 01:45:19 PM PDT 24
Peak memory 192784 kb
Host smart-04da2265-a372-46f6-a64a-a9b72976c618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168462753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.168462753
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3465237148
Short name T431
Test name
Test status
Simulation time 70706355 ps
CPU time 0.63 seconds
Started May 12 01:45:15 PM PDT 24
Finished May 12 01:45:16 PM PDT 24
Peak memory 194032 kb
Host smart-2f39b058-e776-45dd-b975-1d78f751d80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465237148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3465237148
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1235186092
Short name T574
Test name
Test status
Simulation time 19892958772 ps
CPU time 28.35 seconds
Started May 12 01:45:19 PM PDT 24
Finished May 12 01:45:47 PM PDT 24
Peak memory 197080 kb
Host smart-1b420d22-1b76-45e7-bf28-8c63e605551d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235186092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1235186092
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3918063204
Short name T299
Test name
Test status
Simulation time 51716090 ps
CPU time 0.62 seconds
Started May 12 01:45:18 PM PDT 24
Finished May 12 01:45:19 PM PDT 24
Peak memory 194472 kb
Host smart-021786cf-bec5-4638-845c-6e2f79365304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918063204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3918063204
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2737259413
Short name T453
Test name
Test status
Simulation time 17333211 ps
CPU time 0.73 seconds
Started May 12 01:45:16 PM PDT 24
Finished May 12 01:45:17 PM PDT 24
Peak memory 194424 kb
Host smart-4a269945-e5c8-48c4-a0d7-b77e591b1de0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737259413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2737259413
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.430173862
Short name T523
Test name
Test status
Simulation time 27115619 ps
CPU time 1.17 seconds
Started May 12 01:45:23 PM PDT 24
Finished May 12 01:45:25 PM PDT 24
Peak memory 197984 kb
Host smart-590fd179-1fb0-4f88-96bd-0a698dcc611c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430173862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.430173862
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2572275775
Short name T714
Test name
Test status
Simulation time 306227333 ps
CPU time 2.67 seconds
Started May 12 01:45:14 PM PDT 24
Finished May 12 01:45:17 PM PDT 24
Peak memory 197216 kb
Host smart-f108ba4c-437b-4c8c-b4bd-d57d7d6a5227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572275775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2572275775
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1944925179
Short name T434
Test name
Test status
Simulation time 147950689 ps
CPU time 1.34 seconds
Started May 12 01:45:21 PM PDT 24
Finished May 12 01:45:23 PM PDT 24
Peak memory 197048 kb
Host smart-b1e9d0bb-6bb0-4758-85a3-6b8285e64b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944925179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1944925179
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1326851121
Short name T100
Test name
Test status
Simulation time 227980168 ps
CPU time 0.81 seconds
Started May 12 01:45:23 PM PDT 24
Finished May 12 01:45:25 PM PDT 24
Peak memory 195616 kb
Host smart-29a84f19-cc90-4eab-9108-776730bf1ba0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326851121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1326851121
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.503706175
Short name T423
Test name
Test status
Simulation time 49644150 ps
CPU time 2.1 seconds
Started May 12 01:45:19 PM PDT 24
Finished May 12 01:45:21 PM PDT 24
Peak memory 198036 kb
Host smart-8e48fe8b-d65f-491c-8d78-f84afc16f0b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503706175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.503706175
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.4151088110
Short name T202
Test name
Test status
Simulation time 208652460 ps
CPU time 1.1 seconds
Started May 12 01:45:19 PM PDT 24
Finished May 12 01:45:21 PM PDT 24
Peak memory 196504 kb
Host smart-05a521f2-453a-4680-b5bf-dcf7f97f8681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151088110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.4151088110
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3952896607
Short name T511
Test name
Test status
Simulation time 22644436 ps
CPU time 0.79 seconds
Started May 12 01:45:21 PM PDT 24
Finished May 12 01:45:22 PM PDT 24
Peak memory 196404 kb
Host smart-64a8b87b-a461-47d2-afdf-9b800c4670b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952896607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3952896607
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3792959874
Short name T671
Test name
Test status
Simulation time 16272853136 ps
CPU time 46.1 seconds
Started May 12 01:45:20 PM PDT 24
Finished May 12 01:46:06 PM PDT 24
Peak memory 198164 kb
Host smart-25e49499-52aa-496c-be26-331e0b182f21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792959874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3792959874
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.4035661224
Short name T354
Test name
Test status
Simulation time 23655650 ps
CPU time 0.57 seconds
Started May 12 01:45:34 PM PDT 24
Finished May 12 01:45:36 PM PDT 24
Peak memory 193900 kb
Host smart-d1fc5267-8677-4e9c-9dfe-7ec6e84f76bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035661224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.4035661224
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.4232617138
Short name T441
Test name
Test status
Simulation time 62106839 ps
CPU time 0.66 seconds
Started May 12 01:45:21 PM PDT 24
Finished May 12 01:45:22 PM PDT 24
Peak memory 194856 kb
Host smart-af038ea4-84dd-4899-b536-cf058a9a2802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232617138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.4232617138
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.2440263259
Short name T158
Test name
Test status
Simulation time 1216922209 ps
CPU time 12.39 seconds
Started May 12 01:45:20 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 196760 kb
Host smart-1c46a4c5-f056-4693-bf5c-6ecee74aa349
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440263259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.2440263259
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.4075330981
Short name T247
Test name
Test status
Simulation time 237241610 ps
CPU time 0.92 seconds
Started May 12 01:45:22 PM PDT 24
Finished May 12 01:45:23 PM PDT 24
Peak memory 197068 kb
Host smart-54eddc65-fc30-401b-be09-adab888d60fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075330981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.4075330981
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.4284288391
Short name T133
Test name
Test status
Simulation time 66254619 ps
CPU time 1.05 seconds
Started May 12 01:45:25 PM PDT 24
Finished May 12 01:45:27 PM PDT 24
Peak memory 195856 kb
Host smart-fca64ae2-ac2b-45ad-8654-91294960ce18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284288391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.4284288391
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.100642224
Short name T278
Test name
Test status
Simulation time 113954079 ps
CPU time 2.02 seconds
Started May 12 01:45:23 PM PDT 24
Finished May 12 01:45:25 PM PDT 24
Peak memory 197948 kb
Host smart-b6193737-c7bb-46d8-b3b1-6fe07d1d6535
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100642224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.100642224
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2674110779
Short name T346
Test name
Test status
Simulation time 82866520 ps
CPU time 2.36 seconds
Started May 12 01:45:27 PM PDT 24
Finished May 12 01:45:30 PM PDT 24
Peak memory 197132 kb
Host smart-769f46b7-9fea-4dff-a1bc-a668f7c03004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674110779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2674110779
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3005482272
Short name T429
Test name
Test status
Simulation time 59031052 ps
CPU time 1.18 seconds
Started May 12 01:45:31 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 197020 kb
Host smart-afa733ac-4ff9-4b64-bdcb-9692b0c46108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005482272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3005482272
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.251370028
Short name T540
Test name
Test status
Simulation time 442388398 ps
CPU time 1.2 seconds
Started May 12 01:45:14 PM PDT 24
Finished May 12 01:45:16 PM PDT 24
Peak memory 197100 kb
Host smart-9b1072b8-2149-4b02-a32b-2c7b4b7fbc41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251370028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.251370028
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1473020565
Short name T176
Test name
Test status
Simulation time 106165802 ps
CPU time 1.52 seconds
Started May 12 01:45:26 PM PDT 24
Finished May 12 01:45:28 PM PDT 24
Peak memory 197968 kb
Host smart-bed119ef-00d2-455b-8c86-78a57d79ff3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473020565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1473020565
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2558214497
Short name T402
Test name
Test status
Simulation time 67652010 ps
CPU time 0.82 seconds
Started May 12 01:45:25 PM PDT 24
Finished May 12 01:45:27 PM PDT 24
Peak memory 195876 kb
Host smart-d62cad72-f591-416f-8394-7c50125e0833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558214497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2558214497
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2506775104
Short name T347
Test name
Test status
Simulation time 71485329 ps
CPU time 0.91 seconds
Started May 12 01:45:25 PM PDT 24
Finished May 12 01:45:27 PM PDT 24
Peak memory 196548 kb
Host smart-fdf123e8-4cbb-43ac-8c6c-a1dff30a0b7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506775104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2506775104
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.476511462
Short name T645
Test name
Test status
Simulation time 7671821678 ps
CPU time 203.99 seconds
Started May 12 01:45:26 PM PDT 24
Finished May 12 01:48:50 PM PDT 24
Peak memory 198136 kb
Host smart-26333f3e-db35-4057-a52d-084a10b924a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476511462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.476511462
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.3551818495
Short name T56
Test name
Test status
Simulation time 33952305222 ps
CPU time 1042.94 seconds
Started May 12 01:45:29 PM PDT 24
Finished May 12 02:02:53 PM PDT 24
Peak memory 198212 kb
Host smart-1df93616-f7d3-4c27-a77d-7b7e177ecabd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3551818495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.3551818495
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.4268655467
Short name T455
Test name
Test status
Simulation time 57729733 ps
CPU time 0.55 seconds
Started May 12 01:45:27 PM PDT 24
Finished May 12 01:45:28 PM PDT 24
Peak memory 193928 kb
Host smart-4d765362-2c86-4ecd-a17d-d110cede5ca6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268655467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.4268655467
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2055562190
Short name T332
Test name
Test status
Simulation time 42718750 ps
CPU time 0.72 seconds
Started May 12 01:45:21 PM PDT 24
Finished May 12 01:45:22 PM PDT 24
Peak memory 195236 kb
Host smart-b854bd2e-bcfd-4138-9b75-4617bdf1e2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055562190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2055562190
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.3812172492
Short name T497
Test name
Test status
Simulation time 362079136 ps
CPU time 4.41 seconds
Started May 12 01:45:21 PM PDT 24
Finished May 12 01:45:26 PM PDT 24
Peak memory 195884 kb
Host smart-d2d8fd09-667c-45d6-87e0-970384485f0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812172492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.3812172492
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2121735157
Short name T526
Test name
Test status
Simulation time 113708154 ps
CPU time 0.77 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:34 PM PDT 24
Peak memory 194764 kb
Host smart-1a152e06-5331-4d19-ad22-680bc7a539c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121735157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2121735157
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3697170154
Short name T543
Test name
Test status
Simulation time 78977499 ps
CPU time 1.35 seconds
Started May 12 01:45:31 PM PDT 24
Finished May 12 01:45:32 PM PDT 24
Peak memory 198056 kb
Host smart-270e5ffa-0d0e-4335-a8d8-f32300167ba1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697170154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3697170154
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.588195906
Short name T682
Test name
Test status
Simulation time 219802473 ps
CPU time 3.58 seconds
Started May 12 01:45:26 PM PDT 24
Finished May 12 01:45:30 PM PDT 24
Peak memory 198068 kb
Host smart-d191025e-c1e8-4eb4-9619-70382476581c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588195906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.588195906
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3601219938
Short name T689
Test name
Test status
Simulation time 551250069 ps
CPU time 2.71 seconds
Started May 12 01:45:24 PM PDT 24
Finished May 12 01:45:27 PM PDT 24
Peak memory 196956 kb
Host smart-8b3ebdb7-d498-4c24-b4e7-ffa23f6e7342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601219938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3601219938
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3707611587
Short name T505
Test name
Test status
Simulation time 58300248 ps
CPU time 0.84 seconds
Started May 12 01:45:27 PM PDT 24
Finished May 12 01:45:28 PM PDT 24
Peak memory 195444 kb
Host smart-f6d84d34-4349-453f-a28e-924484685a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707611587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3707611587
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1617539548
Short name T577
Test name
Test status
Simulation time 26391897 ps
CPU time 1.02 seconds
Started May 12 01:45:23 PM PDT 24
Finished May 12 01:45:24 PM PDT 24
Peak memory 195848 kb
Host smart-9358dadb-e1f8-4ed0-a1c4-5713c6c69ebe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617539548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1617539548
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3720878582
Short name T541
Test name
Test status
Simulation time 306897744 ps
CPU time 1.54 seconds
Started May 12 01:45:26 PM PDT 24
Finished May 12 01:45:28 PM PDT 24
Peak memory 197952 kb
Host smart-32f124ff-9c26-4b14-b3f9-d45907dff9bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720878582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3720878582
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1156650834
Short name T107
Test name
Test status
Simulation time 24610115 ps
CPU time 0.86 seconds
Started May 12 01:45:31 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 196436 kb
Host smart-15d1cd52-bc88-42fc-a821-7d14e6f90e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156650834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1156650834
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3153220217
Short name T631
Test name
Test status
Simulation time 53830411 ps
CPU time 1.02 seconds
Started May 12 01:45:25 PM PDT 24
Finished May 12 01:45:27 PM PDT 24
Peak memory 196444 kb
Host smart-83e6be38-533a-4cb9-a0c9-53e0551cc3e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153220217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3153220217
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.4095027170
Short name T10
Test name
Test status
Simulation time 75066399000 ps
CPU time 207.38 seconds
Started May 12 01:45:30 PM PDT 24
Finished May 12 01:48:58 PM PDT 24
Peak memory 198148 kb
Host smart-c8563216-266e-43e1-8e0b-1732d0411ecf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095027170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.4095027170
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1583499474
Short name T413
Test name
Test status
Simulation time 18989547 ps
CPU time 0.56 seconds
Started May 12 01:45:32 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 194096 kb
Host smart-759522bd-8525-4941-afdd-1d143a2287a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583499474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1583499474
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3321118063
Short name T416
Test name
Test status
Simulation time 40351469 ps
CPU time 0.89 seconds
Started May 12 01:45:18 PM PDT 24
Finished May 12 01:45:19 PM PDT 24
Peak memory 196388 kb
Host smart-e3ca92af-0ca4-40a9-b87c-fd1f04aafe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321118063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3321118063
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1849794811
Short name T643
Test name
Test status
Simulation time 1802330893 ps
CPU time 13 seconds
Started May 12 01:45:39 PM PDT 24
Finished May 12 01:45:52 PM PDT 24
Peak memory 195528 kb
Host smart-17d2e3a5-a4fa-4744-97ff-ca522a8c049c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849794811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1849794811
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.991318771
Short name T22
Test name
Test status
Simulation time 380311174 ps
CPU time 0.99 seconds
Started May 12 01:45:28 PM PDT 24
Finished May 12 01:45:30 PM PDT 24
Peak memory 196600 kb
Host smart-ea760795-4712-4c50-8453-7fa4484f1f6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991318771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.991318771
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2934463913
Short name T607
Test name
Test status
Simulation time 35448346 ps
CPU time 1.09 seconds
Started May 12 01:45:22 PM PDT 24
Finished May 12 01:45:23 PM PDT 24
Peak memory 195980 kb
Host smart-00132ad5-3608-4da5-8473-84dcc45a52c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934463913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2934463913
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3665414225
Short name T232
Test name
Test status
Simulation time 45943623 ps
CPU time 1.82 seconds
Started May 12 01:45:32 PM PDT 24
Finished May 12 01:45:34 PM PDT 24
Peak memory 198108 kb
Host smart-913f8431-a10c-4d99-ab5b-b9d53c2bfa22
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665414225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3665414225
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1591405091
Short name T363
Test name
Test status
Simulation time 192845591 ps
CPU time 2.81 seconds
Started May 12 01:45:25 PM PDT 24
Finished May 12 01:45:28 PM PDT 24
Peak memory 195808 kb
Host smart-fcf0bf28-8c2e-479e-8d51-26e87ef7c472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591405091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1591405091
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4193270015
Short name T206
Test name
Test status
Simulation time 54449793 ps
CPU time 1.07 seconds
Started May 12 01:45:32 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 195784 kb
Host smart-481c7e34-810b-410d-838e-12882135afe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193270015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4193270015
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3074911304
Short name T269
Test name
Test status
Simulation time 71281784 ps
CPU time 1.19 seconds
Started May 12 01:45:31 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 197076 kb
Host smart-9a18d28b-91d2-435b-a0e5-18b0788b4e3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074911304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3074911304
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3813817587
Short name T621
Test name
Test status
Simulation time 183546819 ps
CPU time 4.47 seconds
Started May 12 01:45:27 PM PDT 24
Finished May 12 01:45:32 PM PDT 24
Peak memory 198036 kb
Host smart-58fcf9d6-9821-4e9c-ac01-6df684c04e35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813817587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3813817587
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1055198202
Short name T316
Test name
Test status
Simulation time 130358762 ps
CPU time 1.1 seconds
Started May 12 01:45:31 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 195688 kb
Host smart-fb88d5a3-e5f7-4b51-9752-8c82966bedcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055198202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1055198202
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.614040536
Short name T126
Test name
Test status
Simulation time 223753512 ps
CPU time 0.93 seconds
Started May 12 01:45:27 PM PDT 24
Finished May 12 01:45:28 PM PDT 24
Peak memory 195424 kb
Host smart-b114713b-1b82-45f3-90a1-61a77e68a947
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614040536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.614040536
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1663341795
Short name T704
Test name
Test status
Simulation time 15623017222 ps
CPU time 173.98 seconds
Started May 12 01:45:29 PM PDT 24
Finished May 12 01:48:24 PM PDT 24
Peak memory 198132 kb
Host smart-4a30564a-1655-4448-9009-dd540315e0a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663341795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1663341795
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1527576206
Short name T470
Test name
Test status
Simulation time 20526710470 ps
CPU time 626.22 seconds
Started May 12 01:45:28 PM PDT 24
Finished May 12 01:55:55 PM PDT 24
Peak memory 198236 kb
Host smart-4adfa986-6b66-4fd1-8216-6363e829312e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1527576206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1527576206
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1195975058
Short name T489
Test name
Test status
Simulation time 28445100 ps
CPU time 0.57 seconds
Started May 12 01:45:28 PM PDT 24
Finished May 12 01:45:31 PM PDT 24
Peak memory 194012 kb
Host smart-60ffe176-cbdf-447d-b381-18fa103b95c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195975058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1195975058
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.581408716
Short name T304
Test name
Test status
Simulation time 99782100 ps
CPU time 0.87 seconds
Started May 12 01:45:27 PM PDT 24
Finished May 12 01:45:28 PM PDT 24
Peak memory 197356 kb
Host smart-5ea00af9-827d-4c4c-9faa-53cc83ee56e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581408716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.581408716
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.856497798
Short name T717
Test name
Test status
Simulation time 813234363 ps
CPU time 25.78 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:46:00 PM PDT 24
Peak memory 195540 kb
Host smart-01175ab3-cd20-4cd1-adfd-d6b465890268
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856497798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.856497798
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.708846352
Short name T578
Test name
Test status
Simulation time 457129507 ps
CPU time 0.94 seconds
Started May 12 01:45:34 PM PDT 24
Finished May 12 01:45:36 PM PDT 24
Peak memory 197280 kb
Host smart-a8211d94-b4eb-49bd-9c6e-c74d6237074e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708846352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.708846352
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2835637723
Short name T419
Test name
Test status
Simulation time 1757355469 ps
CPU time 1.44 seconds
Started May 12 01:45:29 PM PDT 24
Finished May 12 01:45:30 PM PDT 24
Peak memory 196844 kb
Host smart-f98dfeaa-8615-41de-9269-2a70959276a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835637723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2835637723
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.166941208
Short name T406
Test name
Test status
Simulation time 275714284 ps
CPU time 2.98 seconds
Started May 12 01:45:29 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 196468 kb
Host smart-0ead189a-e9d3-4c38-91ab-3c29a091e245
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166941208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
166941208
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3005172069
Short name T127
Test name
Test status
Simulation time 55014459 ps
CPU time 1.02 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:35 PM PDT 24
Peak memory 195968 kb
Host smart-91284da2-0b53-4d97-8983-e4b7fa8cdb12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005172069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3005172069
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4176607263
Short name T366
Test name
Test status
Simulation time 55184450 ps
CPU time 0.62 seconds
Started May 12 01:45:29 PM PDT 24
Finished May 12 01:45:30 PM PDT 24
Peak memory 194272 kb
Host smart-d14b7908-3794-4a57-a1eb-784d101792b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176607263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4176607263
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2399108778
Short name T608
Test name
Test status
Simulation time 390657932 ps
CPU time 4.11 seconds
Started May 12 01:45:26 PM PDT 24
Finished May 12 01:45:30 PM PDT 24
Peak memory 197996 kb
Host smart-30813195-efa1-4cef-9118-56f2451e50ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399108778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2399108778
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1600335622
Short name T162
Test name
Test status
Simulation time 45653703 ps
CPU time 1.19 seconds
Started May 12 01:45:25 PM PDT 24
Finished May 12 01:45:26 PM PDT 24
Peak memory 196460 kb
Host smart-827adcd2-3b9c-483b-b291-6447b0866234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600335622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1600335622
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3124868090
Short name T681
Test name
Test status
Simulation time 52001580 ps
CPU time 1.41 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:35 PM PDT 24
Peak memory 196256 kb
Host smart-a4c395e8-a9e4-4a67-b40d-082cd88beac8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124868090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3124868090
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1123388374
Short name T623
Test name
Test status
Simulation time 72782077870 ps
CPU time 118.66 seconds
Started May 12 01:45:36 PM PDT 24
Finished May 12 01:47:35 PM PDT 24
Peak memory 198164 kb
Host smart-789dfbfa-1e1c-42ca-af48-e97961f5bae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123388374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1123388374
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2677646059
Short name T213
Test name
Test status
Simulation time 24993476 ps
CPU time 0.58 seconds
Started May 12 01:45:34 PM PDT 24
Finished May 12 01:45:36 PM PDT 24
Peak memory 194804 kb
Host smart-00e4081a-6923-44cb-b84d-08de0b06a656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677646059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2677646059
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2370031754
Short name T572
Test name
Test status
Simulation time 103718143 ps
CPU time 0.95 seconds
Started May 12 01:45:32 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 196700 kb
Host smart-25d7249c-c4a9-4242-901b-35ec36be0140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370031754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2370031754
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.546830048
Short name T633
Test name
Test status
Simulation time 584549155 ps
CPU time 17 seconds
Started May 12 01:45:36 PM PDT 24
Finished May 12 01:45:54 PM PDT 24
Peak memory 197972 kb
Host smart-3ca54cc9-8294-4134-b236-8fafa6617baf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546830048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.546830048
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1501585580
Short name T461
Test name
Test status
Simulation time 74417205 ps
CPU time 0.98 seconds
Started May 12 01:45:34 PM PDT 24
Finished May 12 01:45:36 PM PDT 24
Peak memory 197760 kb
Host smart-0ba36f8a-3d22-4078-b621-92da56135231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501585580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1501585580
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.698026478
Short name T153
Test name
Test status
Simulation time 39749523 ps
CPU time 1.07 seconds
Started May 12 01:45:35 PM PDT 24
Finished May 12 01:45:37 PM PDT 24
Peak memory 195784 kb
Host smart-ae177412-0c18-4c4f-8b2e-b12e49221857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698026478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.698026478
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.488420319
Short name T654
Test name
Test status
Simulation time 289314309 ps
CPU time 1.23 seconds
Started May 12 01:45:35 PM PDT 24
Finished May 12 01:45:37 PM PDT 24
Peak memory 198064 kb
Host smart-8f2b04af-78ab-4e62-bac3-74f74ab6a8b3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488420319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.488420319
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.913468805
Short name T457
Test name
Test status
Simulation time 821871053 ps
CPU time 2.26 seconds
Started May 12 01:45:39 PM PDT 24
Finished May 12 01:45:42 PM PDT 24
Peak memory 196716 kb
Host smart-fbf76709-700a-4791-a092-027ea2d1b468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913468805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger.
913468805
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1565180197
Short name T241
Test name
Test status
Simulation time 554932438 ps
CPU time 0.98 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:45:38 PM PDT 24
Peak memory 196048 kb
Host smart-812d2828-675c-49ae-a742-bf02bd81e277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565180197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1565180197
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2952048924
Short name T148
Test name
Test status
Simulation time 30259983 ps
CPU time 1.12 seconds
Started May 12 01:45:35 PM PDT 24
Finished May 12 01:45:37 PM PDT 24
Peak memory 195956 kb
Host smart-6e5ef62b-c391-478b-a517-d70c4af6e6c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952048924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2952048924
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1206217243
Short name T592
Test name
Test status
Simulation time 438496479 ps
CPU time 4.98 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:39 PM PDT 24
Peak memory 197912 kb
Host smart-83438698-a58c-4820-94b2-6ad526e4b5c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206217243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1206217243
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3042786599
Short name T270
Test name
Test status
Simulation time 102910294 ps
CPU time 1.4 seconds
Started May 12 01:45:40 PM PDT 24
Finished May 12 01:45:42 PM PDT 24
Peak memory 195480 kb
Host smart-2c88a1a2-0624-43a6-bbd8-8de64b89d32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042786599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3042786599
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2910646276
Short name T549
Test name
Test status
Simulation time 389948136 ps
CPU time 1.52 seconds
Started May 12 01:45:29 PM PDT 24
Finished May 12 01:45:31 PM PDT 24
Peak memory 197920 kb
Host smart-ad4c71ef-42ce-4baa-aca1-1aa9af6e2a5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910646276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2910646276
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.4159904844
Short name T602
Test name
Test status
Simulation time 14090893923 ps
CPU time 198.82 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:48:53 PM PDT 24
Peak memory 198096 kb
Host smart-29ef1516-49d0-4924-86bd-daff455a6423
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159904844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.4159904844
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2449421451
Short name T686
Test name
Test status
Simulation time 54228155399 ps
CPU time 859.34 seconds
Started May 12 01:45:40 PM PDT 24
Finished May 12 02:00:00 PM PDT 24
Peak memory 198220 kb
Host smart-20c3c089-dde2-44b3-a38f-e9c1fafb09a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2449421451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2449421451
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1450769499
Short name T675
Test name
Test status
Simulation time 23017737 ps
CPU time 0.58 seconds
Started May 12 01:45:34 PM PDT 24
Finished May 12 01:45:36 PM PDT 24
Peak memory 194804 kb
Host smart-4e1ac65c-da43-43bd-8781-c208b7ac1fac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450769499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1450769499
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1419783662
Short name T518
Test name
Test status
Simulation time 26508854 ps
CPU time 0.77 seconds
Started May 12 01:45:30 PM PDT 24
Finished May 12 01:45:31 PM PDT 24
Peak memory 196144 kb
Host smart-aa932a0f-2b7a-469d-aeec-23470e196da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419783662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1419783662
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2705216575
Short name T427
Test name
Test status
Simulation time 502904804 ps
CPU time 7.09 seconds
Started May 12 01:45:34 PM PDT 24
Finished May 12 01:45:42 PM PDT 24
Peak memory 196864 kb
Host smart-4b79c007-f7b3-4d45-9580-41cf5c164b83
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705216575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2705216575
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2257106211
Short name T337
Test name
Test status
Simulation time 199987890 ps
CPU time 0.83 seconds
Started May 12 01:45:34 PM PDT 24
Finished May 12 01:45:36 PM PDT 24
Peak memory 196056 kb
Host smart-f1c30b59-f5a1-45de-941c-88591264d50e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257106211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2257106211
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.643691510
Short name T101
Test name
Test status
Simulation time 227531643 ps
CPU time 0.93 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:45:39 PM PDT 24
Peak memory 197268 kb
Host smart-b64ccd4a-9f66-4212-9069-15675009f4fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643691510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.643691510
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2275652082
Short name T338
Test name
Test status
Simulation time 179838035 ps
CPU time 3.39 seconds
Started May 12 01:45:43 PM PDT 24
Finished May 12 01:45:47 PM PDT 24
Peak memory 198048 kb
Host smart-b8b658ba-3a81-4d8c-a1d6-b7d8d21e39d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275652082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2275652082
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2313859666
Short name T376
Test name
Test status
Simulation time 707740192 ps
CPU time 2.98 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:45:41 PM PDT 24
Peak memory 197288 kb
Host smart-076badef-e79a-41df-a710-7cbadb14a361
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313859666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2313859666
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1715485641
Short name T485
Test name
Test status
Simulation time 33564016 ps
CPU time 1.13 seconds
Started May 12 01:45:39 PM PDT 24
Finished May 12 01:45:41 PM PDT 24
Peak memory 198056 kb
Host smart-b6581bef-549f-40e6-9fab-734a11f1e791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715485641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1715485641
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2697075386
Short name T13
Test name
Test status
Simulation time 64398539 ps
CPU time 0.99 seconds
Started May 12 01:45:25 PM PDT 24
Finished May 12 01:45:26 PM PDT 24
Peak memory 196680 kb
Host smart-c56e0272-fe35-444c-a1f2-b80f9c3412bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697075386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2697075386
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1532321661
Short name T5
Test name
Test status
Simulation time 95057012 ps
CPU time 1.58 seconds
Started May 12 01:45:31 PM PDT 24
Finished May 12 01:45:34 PM PDT 24
Peak memory 198052 kb
Host smart-48df1e37-a224-456d-a21a-e639ba669b36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532321661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1532321661
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2007388946
Short name T263
Test name
Test status
Simulation time 125884249 ps
CPU time 0.89 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:45:38 PM PDT 24
Peak memory 196328 kb
Host smart-6cf4e4f0-c1a2-4daf-95e6-d817ba8b5843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007388946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2007388946
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.880057902
Short name T598
Test name
Test status
Simulation time 59892260 ps
CPU time 0.95 seconds
Started May 12 01:45:38 PM PDT 24
Finished May 12 01:45:39 PM PDT 24
Peak memory 195500 kb
Host smart-918a18bb-be12-4857-9a8c-099e075cba21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880057902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.880057902
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2638357716
Short name T297
Test name
Test status
Simulation time 4166976732 ps
CPU time 56.05 seconds
Started May 12 01:45:28 PM PDT 24
Finished May 12 01:46:24 PM PDT 24
Peak memory 198128 kb
Host smart-c168ce39-3fc6-4ed6-9a85-4f2a20c0379d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638357716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2638357716
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3071072554
Short name T417
Test name
Test status
Simulation time 83190071788 ps
CPU time 964.2 seconds
Started May 12 01:45:41 PM PDT 24
Finished May 12 02:01:46 PM PDT 24
Peak memory 198288 kb
Host smart-750eb18e-aae6-4cd8-95ec-3436bdbc0d8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3071072554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3071072554
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1387174237
Short name T129
Test name
Test status
Simulation time 39183729 ps
CPU time 0.56 seconds
Started May 12 01:45:45 PM PDT 24
Finished May 12 01:45:46 PM PDT 24
Peak memory 193912 kb
Host smart-95422387-9ad7-4d41-b65e-806f6f8f3ca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387174237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1387174237
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1243611515
Short name T203
Test name
Test status
Simulation time 89621167 ps
CPU time 0.93 seconds
Started May 12 01:45:43 PM PDT 24
Finished May 12 01:45:45 PM PDT 24
Peak memory 195956 kb
Host smart-48e05c1c-41d5-4391-a7ca-291344fdf1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243611515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1243611515
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2934098517
Short name T91
Test name
Test status
Simulation time 540073406 ps
CPU time 4.2 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:45:42 PM PDT 24
Peak memory 196500 kb
Host smart-37294a16-fc4f-4078-bdfd-fc8b6a0e4506
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934098517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2934098517
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.439909408
Short name T132
Test name
Test status
Simulation time 113618531 ps
CPU time 0.81 seconds
Started May 12 01:45:32 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 196024 kb
Host smart-e85a1810-78f7-4a77-8fe3-f1c15c46e220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439909408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.439909408
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.530202274
Short name T475
Test name
Test status
Simulation time 139565539 ps
CPU time 1.02 seconds
Started May 12 01:45:32 PM PDT 24
Finished May 12 01:45:33 PM PDT 24
Peak memory 196048 kb
Host smart-c27e09e2-5bec-4350-9eed-c6ba462944a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530202274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.530202274
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1072141
Short name T98
Test name
Test status
Simulation time 77844222 ps
CPU time 0.94 seconds
Started May 12 01:45:45 PM PDT 24
Finished May 12 01:45:47 PM PDT 24
Peak memory 196316 kb
Host smart-453fc51d-e658-400e-8061-f282001a268d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 47.gpio_intr_with_filter_rand_intr_event.1072141
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.315366601
Short name T290
Test name
Test status
Simulation time 64593592 ps
CPU time 1.85 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:36 PM PDT 24
Peak memory 197168 kb
Host smart-358d8066-39cd-4d53-9aa1-e04b6b25969e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315366601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
315366601
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1175277695
Short name T178
Test name
Test status
Simulation time 50969628 ps
CPU time 0.9 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:35 PM PDT 24
Peak memory 195788 kb
Host smart-6fb7a7ed-9422-4ee4-9483-cef42727bb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175277695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1175277695
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.673811968
Short name T708
Test name
Test status
Simulation time 17883209 ps
CPU time 0.67 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:45:39 PM PDT 24
Peak memory 195432 kb
Host smart-53f37487-fd1c-4608-8831-46540c40fc01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673811968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.673811968
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.217025934
Short name T309
Test name
Test status
Simulation time 43328414 ps
CPU time 1.1 seconds
Started May 12 01:45:40 PM PDT 24
Finished May 12 01:45:42 PM PDT 24
Peak memory 196204 kb
Host smart-9ce40a34-2041-4ca6-a357-c50732e372b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217025934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.217025934
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3502960974
Short name T562
Test name
Test status
Simulation time 505001349 ps
CPU time 1.37 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:35 PM PDT 24
Peak memory 196760 kb
Host smart-fb0687a4-e5b5-4c35-a389-94923dbe35f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502960974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3502960974
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.923166541
Short name T488
Test name
Test status
Simulation time 171211966 ps
CPU time 1.21 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:45:39 PM PDT 24
Peak memory 198164 kb
Host smart-6d8ebc3c-e454-4e10-a5b9-ba38e82c98d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923166541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.923166541
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1860934578
Short name T613
Test name
Test status
Simulation time 29434150374 ps
CPU time 190.24 seconds
Started May 12 01:45:48 PM PDT 24
Finished May 12 01:48:59 PM PDT 24
Peak memory 198180 kb
Host smart-a1a1a66c-3b4b-49a4-92eb-bc57a5e44004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860934578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1860934578
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.917183508
Short name T510
Test name
Test status
Simulation time 38564113 ps
CPU time 0.56 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:35 PM PDT 24
Peak memory 194580 kb
Host smart-8321f662-7d21-4dbb-bf35-12a2e01b95c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917183508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.917183508
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.4090586129
Short name T459
Test name
Test status
Simulation time 42532819 ps
CPU time 0.83 seconds
Started May 12 01:45:40 PM PDT 24
Finished May 12 01:45:41 PM PDT 24
Peak memory 196164 kb
Host smart-a3b4a577-94c6-4540-a7bb-654f149fa49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090586129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.4090586129
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.103221676
Short name T477
Test name
Test status
Simulation time 1642148921 ps
CPU time 28.13 seconds
Started May 12 01:45:35 PM PDT 24
Finished May 12 01:46:04 PM PDT 24
Peak memory 197148 kb
Host smart-7f7dd4b0-999b-4251-8c30-4f1d890e2006
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103221676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.103221676
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3449056713
Short name T615
Test name
Test status
Simulation time 488591941 ps
CPU time 1.01 seconds
Started May 12 01:45:38 PM PDT 24
Finished May 12 01:45:40 PM PDT 24
Peak memory 197864 kb
Host smart-db6b25f4-e76d-4086-a5c3-368e9aa88de6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449056713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3449056713
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.515362169
Short name T524
Test name
Test status
Simulation time 41194475 ps
CPU time 0.88 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:35 PM PDT 24
Peak memory 196540 kb
Host smart-1bc9193c-f95f-47b8-9fc1-a02486103596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515362169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.515362169
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.4223399559
Short name T428
Test name
Test status
Simulation time 48939290 ps
CPU time 1.88 seconds
Started May 12 01:45:35 PM PDT 24
Finished May 12 01:45:37 PM PDT 24
Peak memory 198064 kb
Host smart-54cb111b-ad32-4578-a1d6-0f9a1a7b8c27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223399559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.4223399559
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2845076873
Short name T109
Test name
Test status
Simulation time 375438920 ps
CPU time 2.12 seconds
Started May 12 01:45:38 PM PDT 24
Finished May 12 01:45:41 PM PDT 24
Peak memory 195796 kb
Host smart-89044a37-8df2-4995-8541-bb7131ed82f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845076873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2845076873
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3610143484
Short name T484
Test name
Test status
Simulation time 120316194 ps
CPU time 0.94 seconds
Started May 12 01:45:40 PM PDT 24
Finished May 12 01:45:42 PM PDT 24
Peak memory 195912 kb
Host smart-f8020b97-c608-40d7-9851-40b0ff8af5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610143484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3610143484
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1692941483
Short name T239
Test name
Test status
Simulation time 27940859 ps
CPU time 1.01 seconds
Started May 12 01:45:39 PM PDT 24
Finished May 12 01:45:41 PM PDT 24
Peak memory 195992 kb
Host smart-6c009795-1c26-4458-980e-0c218fcc20d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692941483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1692941483
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.922247709
Short name T283
Test name
Test status
Simulation time 52448142 ps
CPU time 2.49 seconds
Started May 12 01:45:40 PM PDT 24
Finished May 12 01:45:43 PM PDT 24
Peak memory 197952 kb
Host smart-2b7b51bf-82a5-4a25-9645-949d946c3e74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922247709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.922247709
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.274721123
Short name T265
Test name
Test status
Simulation time 228740146 ps
CPU time 1 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:35 PM PDT 24
Peak memory 195832 kb
Host smart-ed4f02d6-d8e4-4d0d-a6b5-7538232c7630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274721123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.274721123
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1785768402
Short name T181
Test name
Test status
Simulation time 450457980 ps
CPU time 1.12 seconds
Started May 12 01:45:33 PM PDT 24
Finished May 12 01:45:35 PM PDT 24
Peak memory 196516 kb
Host smart-eabe7c7a-30ec-4e75-8888-cd4c9ba5bd68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785768402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1785768402
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1253450402
Short name T393
Test name
Test status
Simulation time 6120512746 ps
CPU time 149.25 seconds
Started May 12 01:45:35 PM PDT 24
Finished May 12 01:48:05 PM PDT 24
Peak memory 198208 kb
Host smart-237d42f9-16f4-4824-ad24-c98f88ddc02a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253450402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1253450402
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1407761802
Short name T504
Test name
Test status
Simulation time 16299063 ps
CPU time 0.56 seconds
Started May 12 01:45:40 PM PDT 24
Finished May 12 01:45:41 PM PDT 24
Peak memory 193896 kb
Host smart-62ef3fd7-a33d-4e2c-be34-e071e926af54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407761802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1407761802
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2712389982
Short name T703
Test name
Test status
Simulation time 26818447 ps
CPU time 0.62 seconds
Started May 12 01:45:36 PM PDT 24
Finished May 12 01:45:37 PM PDT 24
Peak memory 194080 kb
Host smart-dc773a11-ba0a-4b72-8bcf-04a032c16cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712389982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2712389982
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.950213088
Short name T286
Test name
Test status
Simulation time 358236525 ps
CPU time 11.02 seconds
Started May 12 01:45:43 PM PDT 24
Finished May 12 01:45:54 PM PDT 24
Peak memory 197972 kb
Host smart-712d910e-135d-4b04-bf65-0fa92f7c9f11
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950213088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.950213088
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2778063377
Short name T7
Test name
Test status
Simulation time 328375915 ps
CPU time 1.03 seconds
Started May 12 01:45:36 PM PDT 24
Finished May 12 01:45:37 PM PDT 24
Peak memory 196436 kb
Host smart-f21f016e-1c89-485c-b3ea-6e7e5d0e6af0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778063377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2778063377
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3879422586
Short name T244
Test name
Test status
Simulation time 547520738 ps
CPU time 0.9 seconds
Started May 12 01:45:41 PM PDT 24
Finished May 12 01:45:42 PM PDT 24
Peak memory 196792 kb
Host smart-a16d3599-5503-457a-839e-824647d7af03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879422586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3879422586
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2749847367
Short name T96
Test name
Test status
Simulation time 257205497 ps
CPU time 2.54 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:45:40 PM PDT 24
Peak memory 196292 kb
Host smart-7eb2c3e3-9e6d-4cf8-9cd3-a7ce9334b72c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749847367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2749847367
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3408785853
Short name T684
Test name
Test status
Simulation time 187360351 ps
CPU time 3.07 seconds
Started May 12 01:45:41 PM PDT 24
Finished May 12 01:45:45 PM PDT 24
Peak memory 195712 kb
Host smart-85cf338d-e7a9-48cb-a11b-2c86f6722655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408785853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3408785853
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1179534761
Short name T483
Test name
Test status
Simulation time 14676398 ps
CPU time 0.64 seconds
Started May 12 01:45:41 PM PDT 24
Finished May 12 01:45:43 PM PDT 24
Peak memory 194368 kb
Host smart-2b3c4aa6-49a2-429b-a0c5-740ffc7eb675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179534761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1179534761
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.206876021
Short name T323
Test name
Test status
Simulation time 22380336 ps
CPU time 0.83 seconds
Started May 12 01:45:45 PM PDT 24
Finished May 12 01:45:46 PM PDT 24
Peak memory 197472 kb
Host smart-799c8884-b90b-460d-aee3-60896c40b7bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206876021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.206876021
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2400957753
Short name T660
Test name
Test status
Simulation time 100926251 ps
CPU time 4.49 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:45:42 PM PDT 24
Peak memory 197944 kb
Host smart-c61b8771-a1ab-48dc-9467-f0f3b0d45823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400957753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2400957753
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2817397815
Short name T123
Test name
Test status
Simulation time 143398418 ps
CPU time 0.73 seconds
Started May 12 01:45:35 PM PDT 24
Finished May 12 01:45:36 PM PDT 24
Peak memory 195324 kb
Host smart-b99270cf-9c48-4d1d-bc1a-b9301ab9f03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817397815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2817397815
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2752012669
Short name T579
Test name
Test status
Simulation time 70769480 ps
CPU time 1.16 seconds
Started May 12 01:45:41 PM PDT 24
Finished May 12 01:45:43 PM PDT 24
Peak memory 195688 kb
Host smart-1329c65a-0e18-4281-92ca-6ab8632b3634
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752012669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2752012669
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2662598356
Short name T6
Test name
Test status
Simulation time 24800215994 ps
CPU time 66.8 seconds
Started May 12 01:45:34 PM PDT 24
Finished May 12 01:46:42 PM PDT 24
Peak memory 198208 kb
Host smart-e2aacb57-b555-4631-911c-d5dce4ea2c90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662598356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2662598356
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2103475567
Short name T57
Test name
Test status
Simulation time 10866374228 ps
CPU time 387.62 seconds
Started May 12 01:45:37 PM PDT 24
Finished May 12 01:52:06 PM PDT 24
Peak memory 198304 kb
Host smart-5e9d6652-0489-40ce-8041-d3044089784c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2103475567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2103475567
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1489230259
Short name T701
Test name
Test status
Simulation time 34265351 ps
CPU time 0.57 seconds
Started May 12 01:44:13 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 194520 kb
Host smart-826cc963-2c16-4e8a-84e9-0bfe8330a30a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489230259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1489230259
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.1056806826
Short name T620
Test name
Test status
Simulation time 135906785 ps
CPU time 0.83 seconds
Started May 12 01:44:13 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 196160 kb
Host smart-f64601cb-c118-487b-98c8-db31ce8ad2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056806826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.1056806826
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.1948383095
Short name T115
Test name
Test status
Simulation time 3880761229 ps
CPU time 25.12 seconds
Started May 12 01:44:23 PM PDT 24
Finished May 12 01:44:48 PM PDT 24
Peak memory 197980 kb
Host smart-2797b48b-1f15-4951-b92d-e5aceabf2b75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948383095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.1948383095
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1431854182
Short name T329
Test name
Test status
Simulation time 187066672 ps
CPU time 0.68 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:22 PM PDT 24
Peak memory 194740 kb
Host smart-106e17dc-673f-4f87-836d-50d1ce408ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431854182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1431854182
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2147850015
Short name T258
Test name
Test status
Simulation time 24192211 ps
CPU time 0.77 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 195068 kb
Host smart-b64a36ba-93e4-430c-a4fd-3582c9f8f20f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147850015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2147850015
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2916492422
Short name T223
Test name
Test status
Simulation time 42244567 ps
CPU time 1.02 seconds
Started May 12 01:44:15 PM PDT 24
Finished May 12 01:44:17 PM PDT 24
Peak memory 196024 kb
Host smart-99f74b03-13a8-4de8-b153-03d8ed36ee27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916492422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2916492422
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.900679196
Short name T640
Test name
Test status
Simulation time 154707593 ps
CPU time 2.44 seconds
Started May 12 01:44:14 PM PDT 24
Finished May 12 01:44:17 PM PDT 24
Peak memory 197160 kb
Host smart-3f9ba80c-f589-4ba3-a894-d9281b96b96d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900679196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.900679196
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.327716256
Short name T624
Test name
Test status
Simulation time 176242416 ps
CPU time 0.95 seconds
Started May 12 01:44:13 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 196672 kb
Host smart-f36474be-7a68-4549-8950-954b3f90d1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327716256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.327716256
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2297276772
Short name T396
Test name
Test status
Simulation time 159332946 ps
CPU time 1.06 seconds
Started May 12 01:44:13 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 195708 kb
Host smart-7201a6f8-99d3-4b5b-831e-f215ce87fdf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297276772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2297276772
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3097756804
Short name T492
Test name
Test status
Simulation time 240560066 ps
CPU time 1.18 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:18 PM PDT 24
Peak memory 198000 kb
Host smart-901d0b3f-86f0-4d3b-a503-795a45b75839
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097756804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3097756804
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.168870972
Short name T408
Test name
Test status
Simulation time 348942993 ps
CPU time 1.07 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:18 PM PDT 24
Peak memory 195544 kb
Host smart-2fa1c9b9-482d-42f8-86aa-60204ed432e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168870972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.168870972
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.506732624
Short name T399
Test name
Test status
Simulation time 85603821 ps
CPU time 1.47 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 198052 kb
Host smart-c6c5c011-656b-4ad8-9dc0-455dd91fd6c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506732624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.506732624
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1364948163
Short name T655
Test name
Test status
Simulation time 6821980432 ps
CPU time 95.22 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:45:56 PM PDT 24
Peak memory 198076 kb
Host smart-13f7643c-b0c3-4999-b2f8-ee8a3fb3dd3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364948163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1364948163
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3278027692
Short name T436
Test name
Test status
Simulation time 13890672 ps
CPU time 0.59 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 194828 kb
Host smart-5143af56-7a43-4cc7-91a3-8002c316e1b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278027692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3278027692
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1517987354
Short name T253
Test name
Test status
Simulation time 96243242 ps
CPU time 0.73 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 195340 kb
Host smart-0736058f-4bb9-4bdd-bfdf-c697f0173dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517987354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1517987354
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.553762650
Short name T372
Test name
Test status
Simulation time 130068366 ps
CPU time 6.43 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:28 PM PDT 24
Peak memory 197936 kb
Host smart-5f47dce6-8022-4af9-b084-4b457a7dd618
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553762650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.553762650
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3536487336
Short name T111
Test name
Test status
Simulation time 277106460 ps
CPU time 1.05 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 196508 kb
Host smart-deb6a6c6-30ce-438d-b2df-344309161317
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536487336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3536487336
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.655643575
Short name T430
Test name
Test status
Simulation time 287259159 ps
CPU time 1.39 seconds
Started May 12 01:44:11 PM PDT 24
Finished May 12 01:44:14 PM PDT 24
Peak memory 197084 kb
Host smart-95c933e5-a63b-4520-947d-53ee293f6c7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655643575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.655643575
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.157241373
Short name T281
Test name
Test status
Simulation time 158244664 ps
CPU time 3.07 seconds
Started May 12 01:44:13 PM PDT 24
Finished May 12 01:44:17 PM PDT 24
Peak memory 198032 kb
Host smart-048f7ea4-4e0a-4eb0-82a1-2c9012b9ba61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157241373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.157241373
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.4096810372
Short name T163
Test name
Test status
Simulation time 101484119 ps
CPU time 2.31 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 198008 kb
Host smart-8cc46e31-ad8f-47ea-8072-427a79bb7494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096810372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
4096810372
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2111788623
Short name T210
Test name
Test status
Simulation time 18083534 ps
CPU time 0.64 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 194952 kb
Host smart-ac14daed-a6c0-4cea-b269-4b7dbb93ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111788623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2111788623
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2035676406
Short name T617
Test name
Test status
Simulation time 95403025 ps
CPU time 0.77 seconds
Started May 12 01:44:15 PM PDT 24
Finished May 12 01:44:17 PM PDT 24
Peak memory 196240 kb
Host smart-0064dc8c-8e5e-4770-bfbc-3fe68c31c1b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035676406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2035676406
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3298739311
Short name T359
Test name
Test status
Simulation time 1115705610 ps
CPU time 4.87 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:26 PM PDT 24
Peak memory 197956 kb
Host smart-aae5cb20-05b2-401a-ad85-807220b9ac69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298739311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3298739311
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3397983146
Short name T264
Test name
Test status
Simulation time 121229632 ps
CPU time 1.09 seconds
Started May 12 01:44:14 PM PDT 24
Finished May 12 01:44:16 PM PDT 24
Peak memory 195524 kb
Host smart-2ef6ce6f-de1e-474a-a848-1d7e788533d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397983146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3397983146
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2071681222
Short name T618
Test name
Test status
Simulation time 89725496 ps
CPU time 0.68 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:17 PM PDT 24
Peak memory 194144 kb
Host smart-65124b5c-c31f-4b36-84cc-8d121d673ab2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071681222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2071681222
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2944592109
Short name T9
Test name
Test status
Simulation time 64920940645 ps
CPU time 164.35 seconds
Started May 12 01:44:24 PM PDT 24
Finished May 12 01:47:10 PM PDT 24
Peak memory 198244 kb
Host smart-50593de2-ff2c-4bba-9a44-8ce892bf0636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944592109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2944592109
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2084678002
Short name T634
Test name
Test status
Simulation time 355074580681 ps
CPU time 1995.01 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 02:17:33 PM PDT 24
Peak memory 198224 kb
Host smart-2660a2c8-80fc-48b1-b1a2-b835018838fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2084678002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2084678002
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2811731275
Short name T154
Test name
Test status
Simulation time 20077322 ps
CPU time 0.54 seconds
Started May 12 01:44:14 PM PDT 24
Finished May 12 01:44:15 PM PDT 24
Peak memory 193880 kb
Host smart-9a3ea5c6-1a3a-414a-b294-0a13a95df213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811731275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2811731275
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1940710704
Short name T17
Test name
Test status
Simulation time 15621185 ps
CPU time 0.64 seconds
Started May 12 01:44:15 PM PDT 24
Finished May 12 01:44:16 PM PDT 24
Peak memory 194076 kb
Host smart-6ffa11c7-00cd-4388-bd6f-07dc98c2613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940710704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1940710704
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1967106820
Short name T397
Test name
Test status
Simulation time 645577432 ps
CPU time 14.38 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:32 PM PDT 24
Peak memory 196964 kb
Host smart-665ec523-2838-4ab9-b974-35f60e87670f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967106820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1967106820
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.639761810
Short name T20
Test name
Test status
Simulation time 62622536 ps
CPU time 0.9 seconds
Started May 12 01:44:22 PM PDT 24
Finished May 12 01:44:24 PM PDT 24
Peak memory 196040 kb
Host smart-db5357d9-32b5-4f95-bbd7-ca2d3dbacde6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639761810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.639761810
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1133884806
Short name T259
Test name
Test status
Simulation time 37944056 ps
CPU time 1.05 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:44:22 PM PDT 24
Peak memory 196748 kb
Host smart-b752a217-a5fc-4846-8742-f7707685b918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133884806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1133884806
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3620357352
Short name T590
Test name
Test status
Simulation time 72550004 ps
CPU time 2.76 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:21 PM PDT 24
Peak memory 198016 kb
Host smart-d2114301-f2e2-46d7-b07a-de78d316fc68
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620357352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3620357352
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2664774928
Short name T112
Test name
Test status
Simulation time 237677927 ps
CPU time 1.55 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 196072 kb
Host smart-71fb9326-6730-410e-9468-5e47223f3d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664774928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2664774928
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.18111378
Short name T28
Test name
Test status
Simulation time 21695170 ps
CPU time 0.66 seconds
Started May 12 01:44:14 PM PDT 24
Finished May 12 01:44:16 PM PDT 24
Peak memory 195040 kb
Host smart-1b09a0d9-bded-405e-90e5-c9c7855fdd27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18111378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.18111378
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.533149652
Short name T388
Test name
Test status
Simulation time 53551963 ps
CPU time 1.12 seconds
Started May 12 01:44:22 PM PDT 24
Finished May 12 01:44:24 PM PDT 24
Peak memory 196132 kb
Host smart-e8e4dcbd-cfe5-4903-80f3-6158b6845a12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533149652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.533149652
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4169865125
Short name T305
Test name
Test status
Simulation time 111808553 ps
CPU time 5.01 seconds
Started May 12 01:44:15 PM PDT 24
Finished May 12 01:44:21 PM PDT 24
Peak memory 197928 kb
Host smart-2fb383fe-46de-4719-8326-aee7ca901364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169865125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4169865125
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1296825534
Short name T243
Test name
Test status
Simulation time 140111212 ps
CPU time 1.63 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 196880 kb
Host smart-375a12ba-a401-464c-8009-b6897d71a789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296825534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1296825534
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3212211594
Short name T370
Test name
Test status
Simulation time 39569814 ps
CPU time 0.78 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:18 PM PDT 24
Peak memory 195908 kb
Host smart-3c8621a9-4bf7-4fc1-b424-d7e6fcd20e02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212211594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3212211594
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.946919488
Short name T2
Test name
Test status
Simulation time 16910579013 ps
CPU time 40.99 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:45:00 PM PDT 24
Peak memory 198144 kb
Host smart-c79070d3-0663-4dfe-b22b-d2f37d58dba9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946919488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.946919488
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.496221048
Short name T40
Test name
Test status
Simulation time 36771940 ps
CPU time 0.61 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 194576 kb
Host smart-b9f66d15-6669-463a-8029-ab67cfffdc90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496221048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.496221048
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3184583044
Short name T472
Test name
Test status
Simulation time 80227062 ps
CPU time 0.83 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 195424 kb
Host smart-edb48e1f-d8ac-4c77-86b5-eae0f5fb6a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184583044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3184583044
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.788164170
Short name T106
Test name
Test status
Simulation time 1809459832 ps
CPU time 13.74 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:32 PM PDT 24
Peak memory 195516 kb
Host smart-7a252d8b-0812-47aa-bc10-8abf152937e7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788164170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.788164170
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.129092122
Short name T424
Test name
Test status
Simulation time 47823094 ps
CPU time 0.82 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 195788 kb
Host smart-6ca30857-4c82-4c65-9142-8b2c4ec21039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129092122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.129092122
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2166126086
Short name T307
Test name
Test status
Simulation time 92523295 ps
CPU time 0.89 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 197284 kb
Host smart-3fefab2c-d6aa-40d5-86d8-503c556168bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166126086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2166126086
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.856270657
Short name T650
Test name
Test status
Simulation time 355023455 ps
CPU time 3.39 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:21 PM PDT 24
Peak memory 198016 kb
Host smart-92b29f67-eacd-41fa-be99-b47d937f8b80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856270657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.856270657
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3167487223
Short name T519
Test name
Test status
Simulation time 100542056 ps
CPU time 2.91 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 195840 kb
Host smart-2cdfaf2e-3793-43d3-afb7-e809100b082c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167487223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3167487223
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4098269352
Short name T150
Test name
Test status
Simulation time 330594125 ps
CPU time 1.14 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 196512 kb
Host smart-27e3abfd-d525-4063-8e1b-cf919277812b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098269352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4098269352
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1060327621
Short name T273
Test name
Test status
Simulation time 197812056 ps
CPU time 1.17 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:18 PM PDT 24
Peak memory 196864 kb
Host smart-8d766992-da53-4e6d-a45f-2dfdf38daf6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060327621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1060327621
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.4157197807
Short name T469
Test name
Test status
Simulation time 32413403 ps
CPU time 1.4 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 197948 kb
Host smart-9b922f82-8c59-48e7-a989-166e44aa46a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157197807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.4157197807
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2155151514
Short name T514
Test name
Test status
Simulation time 816536612 ps
CPU time 1.37 seconds
Started May 12 01:44:17 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 195892 kb
Host smart-cd6234c4-5d69-48d9-b263-9fe3c36ad252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155151514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2155151514
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2652248057
Short name T355
Test name
Test status
Simulation time 571494796 ps
CPU time 1.18 seconds
Started May 12 01:44:16 PM PDT 24
Finished May 12 01:44:19 PM PDT 24
Peak memory 196892 kb
Host smart-0ecee14d-742f-4586-a530-dc8207883aae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652248057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2652248057
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1542383770
Short name T3
Test name
Test status
Simulation time 42905577308 ps
CPU time 59.08 seconds
Started May 12 01:44:14 PM PDT 24
Finished May 12 01:45:14 PM PDT 24
Peak memory 198164 kb
Host smart-4c9ade65-65e9-42d8-b47e-56a50c16d13b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542383770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1542383770
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.400653564
Short name T287
Test name
Test status
Simulation time 15995036 ps
CPU time 0.63 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:44:21 PM PDT 24
Peak memory 194136 kb
Host smart-2327bcb8-67ae-410a-b695-cf7154ed9482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400653564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.400653564
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2556941180
Short name T450
Test name
Test status
Simulation time 25668475 ps
CPU time 0.72 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:22 PM PDT 24
Peak memory 194208 kb
Host smart-235488c7-446c-45bb-9dac-8dcaf2a67deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556941180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2556941180
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1815058466
Short name T712
Test name
Test status
Simulation time 2231468804 ps
CPU time 21.73 seconds
Started May 12 01:44:18 PM PDT 24
Finished May 12 01:44:41 PM PDT 24
Peak memory 196936 kb
Host smart-d668451d-35f5-432f-b704-a125172c8009
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815058466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1815058466
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1337038146
Short name T454
Test name
Test status
Simulation time 304665059 ps
CPU time 0.79 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:44:21 PM PDT 24
Peak memory 196556 kb
Host smart-d222f53b-1882-4658-a545-f9e09228a7d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337038146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1337038146
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3956963948
Short name T144
Test name
Test status
Simulation time 75668845 ps
CPU time 1.15 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:22 PM PDT 24
Peak memory 195796 kb
Host smart-23e93154-232e-4ab0-b324-58a7af12dd7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956963948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3956963948
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1978465317
Short name T496
Test name
Test status
Simulation time 392221550 ps
CPU time 1.74 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:44:24 PM PDT 24
Peak memory 197992 kb
Host smart-4b53b020-e7d6-41fa-a1f7-2e2af8b3ae54
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978465317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1978465317
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.237505214
Short name T466
Test name
Test status
Simulation time 89086381 ps
CPU time 2.47 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 195776 kb
Host smart-69a00ef5-8959-404e-8ca0-f01c697f4759
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237505214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.237505214
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.4223710608
Short name T300
Test name
Test status
Simulation time 25084455 ps
CPU time 0.97 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 195912 kb
Host smart-e2e07b25-11d9-4fd1-9233-511e756759dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223710608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.4223710608
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3414777944
Short name T279
Test name
Test status
Simulation time 114487870 ps
CPU time 1.01 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:44:23 PM PDT 24
Peak memory 196664 kb
Host smart-202ac236-5baf-49f1-8630-4e97f94d6a47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414777944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3414777944
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.2550390752
Short name T251
Test name
Test status
Simulation time 59085370 ps
CPU time 1.41 seconds
Started May 12 01:44:20 PM PDT 24
Finished May 12 01:44:22 PM PDT 24
Peak memory 197888 kb
Host smart-76681ed5-7818-4868-911c-428c19183455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550390752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.2550390752
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.957618929
Short name T125
Test name
Test status
Simulation time 431913092 ps
CPU time 1.18 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 196536 kb
Host smart-cb7aae82-960b-48a5-9d40-339e3398939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957618929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.957618929
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1984294500
Short name T550
Test name
Test status
Simulation time 36335567 ps
CPU time 1.04 seconds
Started May 12 01:44:18 PM PDT 24
Finished May 12 01:44:20 PM PDT 24
Peak memory 195852 kb
Host smart-f2483516-aa2a-40b6-8dae-6344db7d9ace
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984294500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1984294500
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1746106541
Short name T563
Test name
Test status
Simulation time 119191590400 ps
CPU time 156.25 seconds
Started May 12 01:44:21 PM PDT 24
Finished May 12 01:46:59 PM PDT 24
Peak memory 198068 kb
Host smart-838addeb-a824-4e3e-a70d-1d9ba17bc15b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746106541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1746106541
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.4204534938
Short name T573
Test name
Test status
Simulation time 85568716300 ps
CPU time 567.46 seconds
Started May 12 01:44:19 PM PDT 24
Finished May 12 01:53:48 PM PDT 24
Peak memory 198236 kb
Host smart-747fb789-5331-474c-8466-bbea0f112e95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4204534938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.4204534938
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3934656827
Short name T941
Test name
Test status
Simulation time 88834521 ps
CPU time 0.96 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:16 PM PDT 24
Peak memory 196708 kb
Host smart-81f264a9-41d4-4b8e-8a03-bf0770e7e258
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3934656827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3934656827
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4253413138
Short name T878
Test name
Test status
Simulation time 230874176 ps
CPU time 1.13 seconds
Started May 12 12:41:18 PM PDT 24
Finished May 12 12:41:20 PM PDT 24
Peak memory 196540 kb
Host smart-14f7dc63-d67b-4367-88d9-1b798d8b7dee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253413138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4253413138
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.461299594
Short name T877
Test name
Test status
Simulation time 30970765 ps
CPU time 0.74 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 194428 kb
Host smart-2957907f-2aa6-46b4-9aae-f140934d7864
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=461299594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.461299594
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.132551633
Short name T922
Test name
Test status
Simulation time 74929096 ps
CPU time 1.18 seconds
Started May 12 12:41:22 PM PDT 24
Finished May 12 12:41:24 PM PDT 24
Peak memory 196760 kb
Host smart-bf1d3a6f-2078-41a6-9dde-3648d2e660d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132551633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.132551633
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2419337622
Short name T873
Test name
Test status
Simulation time 46535945 ps
CPU time 0.89 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:31 PM PDT 24
Peak memory 196412 kb
Host smart-5aa76bc8-fa68-456d-993e-bddbec22084b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2419337622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2419337622
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3303824702
Short name T876
Test name
Test status
Simulation time 625939430 ps
CPU time 1 seconds
Started May 12 12:41:43 PM PDT 24
Finished May 12 12:41:44 PM PDT 24
Peak memory 195696 kb
Host smart-8c844d7f-acd1-4d27-935c-ea76b5859f64
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303824702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3303824702
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4239893420
Short name T896
Test name
Test status
Simulation time 48229883 ps
CPU time 0.78 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 195484 kb
Host smart-6269548a-9afb-4eea-b765-f9edceaf9a9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4239893420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.4239893420
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4162459416
Short name T875
Test name
Test status
Simulation time 59418043 ps
CPU time 1.28 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:27 PM PDT 24
Peak memory 197996 kb
Host smart-4b0ff571-b605-430b-a987-200118fa7f28
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162459416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4162459416
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3503515381
Short name T903
Test name
Test status
Simulation time 118172603 ps
CPU time 0.74 seconds
Started May 12 12:41:16 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 195400 kb
Host smart-bbf2c782-50b0-4a8f-bee9-957030581c30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3503515381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3503515381
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3965072294
Short name T872
Test name
Test status
Simulation time 39996664 ps
CPU time 1.19 seconds
Started May 12 12:41:46 PM PDT 24
Finished May 12 12:41:48 PM PDT 24
Peak memory 196472 kb
Host smart-414d3e0d-0f94-4637-bc27-5170a3132bbb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965072294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3965072294
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2266661003
Short name T907
Test name
Test status
Simulation time 656955906 ps
CPU time 1.15 seconds
Started May 12 12:41:48 PM PDT 24
Finished May 12 12:41:50 PM PDT 24
Peak memory 196600 kb
Host smart-fea8bb74-88c5-4f86-8eb5-6e67f6d4aefb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2266661003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2266661003
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2921935201
Short name T911
Test name
Test status
Simulation time 56696814 ps
CPU time 1.11 seconds
Started May 12 12:41:48 PM PDT 24
Finished May 12 12:41:50 PM PDT 24
Peak memory 198040 kb
Host smart-be77b6f5-ac5c-4922-957f-7aa830cd26e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921935201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2921935201
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2742722770
Short name T871
Test name
Test status
Simulation time 34221924 ps
CPU time 0.84 seconds
Started May 12 12:41:30 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 195544 kb
Host smart-70dc1e0c-d42a-4356-b146-b64e6bf761a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2742722770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2742722770
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2110622441
Short name T933
Test name
Test status
Simulation time 44379511 ps
CPU time 1.19 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 197976 kb
Host smart-42e2cce2-346d-4f66-ab70-895e1ee59995
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110622441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2110622441
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1637246616
Short name T885
Test name
Test status
Simulation time 42824277 ps
CPU time 1.17 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 195648 kb
Host smart-6c308619-1aa0-44cd-bb76-024fcbfcb3e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1637246616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1637246616
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2413469744
Short name T874
Test name
Test status
Simulation time 36764392 ps
CPU time 0.97 seconds
Started May 12 12:41:22 PM PDT 24
Finished May 12 12:41:24 PM PDT 24
Peak memory 196520 kb
Host smart-11619cc5-0c22-4cc3-883e-e3afd2b4a3a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413469744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2413469744
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.209285655
Short name T913
Test name
Test status
Simulation time 130272303 ps
CPU time 0.89 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 195456 kb
Host smart-9d14d15e-0780-4a6a-bac4-e0c68d8c75f5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=209285655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.209285655
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4167517283
Short name T859
Test name
Test status
Simulation time 47654237 ps
CPU time 0.86 seconds
Started May 12 12:41:49 PM PDT 24
Finished May 12 12:41:50 PM PDT 24
Peak memory 197948 kb
Host smart-01fdaf0a-b298-460f-8a94-d7aa8d0fc65e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167517283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4167517283
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3034680623
Short name T919
Test name
Test status
Simulation time 45057745 ps
CPU time 1.37 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 197004 kb
Host smart-8f9f51a1-904d-4921-9b3d-c17a91e946f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3034680623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3034680623
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2498536286
Short name T861
Test name
Test status
Simulation time 178263897 ps
CPU time 0.97 seconds
Started May 12 12:41:42 PM PDT 24
Finished May 12 12:41:43 PM PDT 24
Peak memory 196420 kb
Host smart-508259d9-2b51-438a-a7a8-b854420b0aa7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498536286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2498536286
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.3410423249
Short name T909
Test name
Test status
Simulation time 149682343 ps
CPU time 1.19 seconds
Started May 12 12:41:38 PM PDT 24
Finished May 12 12:41:39 PM PDT 24
Peak memory 196884 kb
Host smart-30067193-1562-4bbb-9e8f-3515e8bfc0f1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3410423249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.3410423249
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.591763600
Short name T927
Test name
Test status
Simulation time 58738543 ps
CPU time 1.26 seconds
Started May 12 12:41:28 PM PDT 24
Finished May 12 12:41:30 PM PDT 24
Peak memory 196488 kb
Host smart-7f99f4d0-31e5-494f-934e-f8a384b2921b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591763600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.591763600
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3021214196
Short name T854
Test name
Test status
Simulation time 198588876 ps
CPU time 1.36 seconds
Started May 12 12:41:49 PM PDT 24
Finished May 12 12:41:56 PM PDT 24
Peak memory 195660 kb
Host smart-6af07e73-edba-446a-8596-9af6b96025a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3021214196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3021214196
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2716720509
Short name T897
Test name
Test status
Simulation time 244350742 ps
CPU time 1.16 seconds
Started May 12 12:41:30 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 196832 kb
Host smart-dbe9eb99-ec2c-4ae4-935a-8652def1f9cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716720509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2716720509
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3755637160
Short name T931
Test name
Test status
Simulation time 35211509 ps
CPU time 0.8 seconds
Started May 12 12:41:28 PM PDT 24
Finished May 12 12:41:30 PM PDT 24
Peak memory 196108 kb
Host smart-a6999279-2b82-46c5-b49e-f1af0f752deb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3755637160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3755637160
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3356082246
Short name T870
Test name
Test status
Simulation time 113612862 ps
CPU time 1.05 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 197928 kb
Host smart-a490143d-2beb-4740-a668-b3b5d4daf8d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356082246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3356082246
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3185824455
Short name T921
Test name
Test status
Simulation time 77489473 ps
CPU time 1.3 seconds
Started May 12 12:41:20 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 196564 kb
Host smart-c8d64879-6362-4e22-a5f3-17d83ae1029a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3185824455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3185824455
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3720813455
Short name T844
Test name
Test status
Simulation time 73334133 ps
CPU time 1.38 seconds
Started May 12 12:41:41 PM PDT 24
Finished May 12 12:41:43 PM PDT 24
Peak memory 197980 kb
Host smart-7bed2bad-fb39-48b2-84ee-3eef49302db4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720813455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3720813455
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1442142272
Short name T847
Test name
Test status
Simulation time 106725006 ps
CPU time 1.41 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:18 PM PDT 24
Peak memory 196804 kb
Host smart-d26d2005-5fe3-4bf0-a2ab-c2affc196a5b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1442142272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1442142272
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2458921037
Short name T850
Test name
Test status
Simulation time 37160943 ps
CPU time 1.18 seconds
Started May 12 12:41:47 PM PDT 24
Finished May 12 12:41:49 PM PDT 24
Peak memory 198100 kb
Host smart-0e9dbad3-28f4-45db-976e-29f4d5f653d0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458921037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2458921037
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.80455208
Short name T928
Test name
Test status
Simulation time 144830641 ps
CPU time 1.29 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:26 PM PDT 24
Peak memory 196552 kb
Host smart-ac59db53-00fa-4222-8fe9-08218103beb9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=80455208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.80455208
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.488659947
Short name T926
Test name
Test status
Simulation time 142650708 ps
CPU time 1.3 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 198060 kb
Host smart-6cce7b55-b546-45d7-9398-d1de9e8f9a07
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488659947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.488659947
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3317965708
Short name T920
Test name
Test status
Simulation time 126762971 ps
CPU time 1.12 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:27 PM PDT 24
Peak memory 196708 kb
Host smart-1e075744-238d-47a2-803b-d4d27e795e98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3317965708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3317965708
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.476760060
Short name T924
Test name
Test status
Simulation time 70651766 ps
CPU time 0.93 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 196536 kb
Host smart-0e9df4c5-1337-404c-9031-023bc3dd1ad1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476760060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.476760060
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1316220609
Short name T929
Test name
Test status
Simulation time 132320796 ps
CPU time 1.44 seconds
Started May 12 12:42:04 PM PDT 24
Finished May 12 12:42:06 PM PDT 24
Peak memory 196360 kb
Host smart-fecbbbdf-d431-4f79-a062-ca3f4535edf2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1316220609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1316220609
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.326000252
Short name T849
Test name
Test status
Simulation time 64210861 ps
CPU time 0.85 seconds
Started May 12 12:41:52 PM PDT 24
Finished May 12 12:41:53 PM PDT 24
Peak memory 196188 kb
Host smart-823e6689-10f7-4fd2-962f-437d6089b8a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326000252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.326000252
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2349974047
Short name T864
Test name
Test status
Simulation time 141194538 ps
CPU time 0.76 seconds
Started May 12 12:41:46 PM PDT 24
Finished May 12 12:41:48 PM PDT 24
Peak memory 195476 kb
Host smart-82765cb2-0f92-4657-bbb2-3fff8d47cdf7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2349974047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2349974047
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3928211551
Short name T938
Test name
Test status
Simulation time 113964872 ps
CPU time 1.29 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:34 PM PDT 24
Peak memory 196708 kb
Host smart-0fdea23e-d5c9-4d75-a154-3f7102f49e12
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928211551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3928211551
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.991370073
Short name T914
Test name
Test status
Simulation time 350332071 ps
CPU time 1.47 seconds
Started May 12 12:41:40 PM PDT 24
Finished May 12 12:41:42 PM PDT 24
Peak memory 197320 kb
Host smart-0ea63341-85be-401a-b714-e8f1d4d79634
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=991370073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.991370073
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4120645902
Short name T917
Test name
Test status
Simulation time 213221346 ps
CPU time 0.81 seconds
Started May 12 12:41:24 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 196384 kb
Host smart-86f27518-f448-420a-b4a2-a3417fbe55c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120645902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4120645902
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2343036227
Short name T882
Test name
Test status
Simulation time 290492176 ps
CPU time 0.75 seconds
Started May 12 12:41:34 PM PDT 24
Finished May 12 12:41:35 PM PDT 24
Peak memory 195520 kb
Host smart-c7517220-8d23-422e-9646-53b79b8f571b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2343036227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2343036227
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2474472081
Short name T890
Test name
Test status
Simulation time 68191014 ps
CPU time 1.13 seconds
Started May 12 12:41:41 PM PDT 24
Finished May 12 12:41:42 PM PDT 24
Peak memory 196808 kb
Host smart-b492897c-4d37-4420-9f25-0070b1c59b7a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474472081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2474472081
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1772706246
Short name T887
Test name
Test status
Simulation time 697058414 ps
CPU time 1.35 seconds
Started May 12 12:41:32 PM PDT 24
Finished May 12 12:41:34 PM PDT 24
Peak memory 196920 kb
Host smart-911a8a47-4128-47c3-8507-aaaf02f077a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1772706246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1772706246
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.352869302
Short name T869
Test name
Test status
Simulation time 31123899 ps
CPU time 0.9 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 196624 kb
Host smart-64552716-3b4b-4ee7-be3f-f678d1fbcd9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352869302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.352869302
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.4172906688
Short name T943
Test name
Test status
Simulation time 61667077 ps
CPU time 1.24 seconds
Started May 12 12:41:43 PM PDT 24
Finished May 12 12:41:44 PM PDT 24
Peak memory 196864 kb
Host smart-ece16b43-8a85-47b8-a407-d7895264aba8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4172906688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.4172906688
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1808814034
Short name T865
Test name
Test status
Simulation time 76459513 ps
CPU time 1.41 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:30 PM PDT 24
Peak memory 196852 kb
Host smart-bff4b487-6e18-414e-9292-2a79b7434c54
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808814034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1808814034
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1071709355
Short name T925
Test name
Test status
Simulation time 61649288 ps
CPU time 1.22 seconds
Started May 12 12:41:14 PM PDT 24
Finished May 12 12:41:16 PM PDT 24
Peak memory 196648 kb
Host smart-3a25f0d0-d18a-42a5-9c5e-e53cdbd262ba
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1071709355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1071709355
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2968772411
Short name T905
Test name
Test status
Simulation time 337277645 ps
CPU time 1.31 seconds
Started May 12 12:41:20 PM PDT 24
Finished May 12 12:41:22 PM PDT 24
Peak memory 198020 kb
Host smart-718c74f7-9b65-4275-987c-e2ef19067f9f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968772411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2968772411
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1166236737
Short name T868
Test name
Test status
Simulation time 282736757 ps
CPU time 0.8 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 195416 kb
Host smart-89cc2abf-f175-44a6-b518-120c47673798
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1166236737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1166236737
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1406128657
Short name T901
Test name
Test status
Simulation time 266992437 ps
CPU time 0.85 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 197972 kb
Host smart-f481f7bb-ebd4-49ce-a98b-2aaf478e976a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406128657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1406128657
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2707290887
Short name T900
Test name
Test status
Simulation time 156420117 ps
CPU time 1.17 seconds
Started May 12 12:41:42 PM PDT 24
Finished May 12 12:41:44 PM PDT 24
Peak memory 197516 kb
Host smart-10042d1b-eba7-43c5-a14f-a0a47d783fec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2707290887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2707290887
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1846559658
Short name T880
Test name
Test status
Simulation time 35512665 ps
CPU time 0.85 seconds
Started May 12 12:41:31 PM PDT 24
Finished May 12 12:41:33 PM PDT 24
Peak memory 196300 kb
Host smart-29a2814b-722b-45fd-8cc2-272b53200201
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846559658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1846559658
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3553191109
Short name T866
Test name
Test status
Simulation time 114922116 ps
CPU time 1.03 seconds
Started May 12 12:41:47 PM PDT 24
Finished May 12 12:41:49 PM PDT 24
Peak memory 196500 kb
Host smart-c8836c85-b908-4ac3-94c0-e13129e7216e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3553191109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3553191109
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2863974979
Short name T898
Test name
Test status
Simulation time 42873561 ps
CPU time 1.31 seconds
Started May 12 12:41:27 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 196412 kb
Host smart-cdc81b1c-81ec-4b54-bd44-930e369f6317
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863974979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2863974979
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.600494792
Short name T857
Test name
Test status
Simulation time 129029705 ps
CPU time 1.21 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:31 PM PDT 24
Peak memory 196396 kb
Host smart-97695106-4aaf-4397-ba26-a6f4bbf89f94
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=600494792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.600494792
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1703582512
Short name T894
Test name
Test status
Simulation time 62485155 ps
CPU time 1.14 seconds
Started May 12 12:41:56 PM PDT 24
Finished May 12 12:41:57 PM PDT 24
Peak memory 196560 kb
Host smart-99afe422-146e-4f60-905c-721226d9d139
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703582512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1703582512
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2439043770
Short name T846
Test name
Test status
Simulation time 233419407 ps
CPU time 1.22 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 196296 kb
Host smart-786ee7c8-253f-4a37-90bc-461f33be3ca5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2439043770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2439043770
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2520509593
Short name T937
Test name
Test status
Simulation time 91667291 ps
CPU time 1.07 seconds
Started May 12 12:41:53 PM PDT 24
Finished May 12 12:41:54 PM PDT 24
Peak memory 196440 kb
Host smart-5d77c6a4-63eb-4f51-a30b-b025dc40e829
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520509593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2520509593
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3416891083
Short name T863
Test name
Test status
Simulation time 60102846 ps
CPU time 1.18 seconds
Started May 12 12:41:36 PM PDT 24
Finished May 12 12:41:37 PM PDT 24
Peak memory 195600 kb
Host smart-825e195e-d07f-4f95-9433-ca3d8f55f1fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3416891083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3416891083
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3511892307
Short name T934
Test name
Test status
Simulation time 232255136 ps
CPU time 1.13 seconds
Started May 12 12:41:48 PM PDT 24
Finished May 12 12:41:50 PM PDT 24
Peak memory 196404 kb
Host smart-0e7d5f1a-28f4-41e3-95d0-e9cfee465627
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511892307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3511892307
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.928943944
Short name T906
Test name
Test status
Simulation time 20160161 ps
CPU time 0.75 seconds
Started May 12 12:41:31 PM PDT 24
Finished May 12 12:41:33 PM PDT 24
Peak memory 196152 kb
Host smart-822afcfb-17ea-40f7-93da-7bdb6451be33
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=928943944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.928943944
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3766430793
Short name T891
Test name
Test status
Simulation time 40819402 ps
CPU time 0.87 seconds
Started May 12 12:41:34 PM PDT 24
Finished May 12 12:41:36 PM PDT 24
Peak memory 196320 kb
Host smart-52c87860-cb81-4c2d-a9fc-d851ba35249b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766430793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3766430793
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2337337032
Short name T858
Test name
Test status
Simulation time 148999374 ps
CPU time 1.06 seconds
Started May 12 12:41:45 PM PDT 24
Finished May 12 12:41:46 PM PDT 24
Peak memory 196820 kb
Host smart-7931c5d0-7703-4167-a72b-844defe0d28e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2337337032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2337337032
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1867374403
Short name T867
Test name
Test status
Simulation time 125052417 ps
CPU time 1.17 seconds
Started May 12 12:41:54 PM PDT 24
Finished May 12 12:41:55 PM PDT 24
Peak memory 196808 kb
Host smart-40ea1177-5cac-45b5-b807-6e1c3447003e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867374403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1867374403
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1710267822
Short name T860
Test name
Test status
Simulation time 177200899 ps
CPU time 1.09 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 195580 kb
Host smart-21a68099-dede-4970-893a-60a3f81b48e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1710267822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1710267822
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1676928759
Short name T893
Test name
Test status
Simulation time 87846563 ps
CPU time 1.27 seconds
Started May 12 12:41:22 PM PDT 24
Finished May 12 12:41:24 PM PDT 24
Peak memory 196944 kb
Host smart-4eef4fd3-cb41-4edb-8b7c-337ba44296ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676928759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1676928759
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3470348532
Short name T930
Test name
Test status
Simulation time 119603664 ps
CPU time 0.95 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:27 PM PDT 24
Peak memory 195604 kb
Host smart-bd4a0a81-0cb2-4c74-9ccd-61f7c556ac27
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3470348532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3470348532
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.529161370
Short name T936
Test name
Test status
Simulation time 79383133 ps
CPU time 1.41 seconds
Started May 12 12:41:39 PM PDT 24
Finished May 12 12:41:41 PM PDT 24
Peak memory 196540 kb
Host smart-9b848047-f8f6-49fd-ba09-1c62c19911c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529161370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.529161370
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1425461847
Short name T908
Test name
Test status
Simulation time 166272420 ps
CPU time 0.86 seconds
Started May 12 12:41:38 PM PDT 24
Finished May 12 12:41:40 PM PDT 24
Peak memory 196200 kb
Host smart-289e3072-2df6-4c29-8403-051bbe9b42f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1425461847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1425461847
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2414979640
Short name T889
Test name
Test status
Simulation time 191960642 ps
CPU time 0.92 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 197176 kb
Host smart-11136034-9b8b-4194-be98-695d33b843d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414979640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2414979640
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.4074559819
Short name T862
Test name
Test status
Simulation time 260776266 ps
CPU time 1.18 seconds
Started May 12 12:41:46 PM PDT 24
Finished May 12 12:41:48 PM PDT 24
Peak memory 196628 kb
Host smart-a80d5886-db31-4122-884d-79c8462fe91f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4074559819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.4074559819
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.249268987
Short name T886
Test name
Test status
Simulation time 99656210 ps
CPU time 1.47 seconds
Started May 12 12:41:39 PM PDT 24
Finished May 12 12:41:41 PM PDT 24
Peak memory 198040 kb
Host smart-bae9f9f1-b077-4269-aafa-95264f5450c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249268987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.249268987
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.354460891
Short name T853
Test name
Test status
Simulation time 134261258 ps
CPU time 1.09 seconds
Started May 12 12:41:47 PM PDT 24
Finished May 12 12:41:49 PM PDT 24
Peak memory 195100 kb
Host smart-afeca2eb-26e9-4019-8f0c-5851b9def51d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=354460891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.354460891
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1086463932
Short name T912
Test name
Test status
Simulation time 112706028 ps
CPU time 1.1 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:28 PM PDT 24
Peak memory 195784 kb
Host smart-aab5b35e-b6d2-4154-918e-58376d57c300
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086463932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1086463932
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1364192563
Short name T899
Test name
Test status
Simulation time 142939402 ps
CPU time 0.85 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:31 PM PDT 24
Peak memory 195748 kb
Host smart-c5a04954-0ed0-4210-a4d0-8a8915192823
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1364192563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1364192563
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1120729817
Short name T855
Test name
Test status
Simulation time 275370072 ps
CPU time 1.24 seconds
Started May 12 12:41:52 PM PDT 24
Finished May 12 12:41:54 PM PDT 24
Peak memory 196588 kb
Host smart-2737cc51-f8c0-4577-91c6-38ef632b82d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120729817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1120729817
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2400644750
Short name T845
Test name
Test status
Simulation time 51066075 ps
CPU time 1.34 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:31 PM PDT 24
Peak memory 196820 kb
Host smart-30128f3e-d232-4884-8f99-b23bf5214431
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2400644750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2400644750
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.330750701
Short name T883
Test name
Test status
Simulation time 135514683 ps
CPU time 1.18 seconds
Started May 12 12:41:59 PM PDT 24
Finished May 12 12:42:00 PM PDT 24
Peak memory 197024 kb
Host smart-451bebf6-c5dc-4851-a1d2-a1b57ce74817
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330750701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.330750701
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2566399016
Short name T879
Test name
Test status
Simulation time 97340488 ps
CPU time 1.11 seconds
Started May 12 12:41:55 PM PDT 24
Finished May 12 12:41:56 PM PDT 24
Peak memory 196480 kb
Host smart-4076d2d7-27a8-4d9b-a06b-c0cdf6dceeec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2566399016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2566399016
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2332164349
Short name T892
Test name
Test status
Simulation time 158646595 ps
CPU time 1.25 seconds
Started May 12 12:41:38 PM PDT 24
Finished May 12 12:41:40 PM PDT 24
Peak memory 196688 kb
Host smart-f9d2e097-0f09-491a-889c-e1186c72a3b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332164349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2332164349
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1561939456
Short name T940
Test name
Test status
Simulation time 42212215 ps
CPU time 0.93 seconds
Started May 12 12:41:43 PM PDT 24
Finished May 12 12:41:44 PM PDT 24
Peak memory 195336 kb
Host smart-65a95d4e-3466-4aaf-8673-9fe4bba94c05
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1561939456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1561939456
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1965567927
Short name T856
Test name
Test status
Simulation time 348911073 ps
CPU time 1.31 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:31 PM PDT 24
Peak memory 198060 kb
Host smart-2ab025f2-2c22-4129-a11c-0211995780e1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965567927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1965567927
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.265628244
Short name T932
Test name
Test status
Simulation time 290215006 ps
CPU time 1.23 seconds
Started May 12 12:41:28 PM PDT 24
Finished May 12 12:41:30 PM PDT 24
Peak memory 196776 kb
Host smart-069b4388-308e-49d6-8d15-dfaa3cbe27bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=265628244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.265628244
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1638421339
Short name T852
Test name
Test status
Simulation time 155531721 ps
CPU time 1.51 seconds
Started May 12 12:41:30 PM PDT 24
Finished May 12 12:41:33 PM PDT 24
Peak memory 196368 kb
Host smart-f3bd1186-7726-435a-bab8-abc8edef10d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638421339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1638421339
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3786466102
Short name T884
Test name
Test status
Simulation time 56495948 ps
CPU time 1.05 seconds
Started May 12 12:41:26 PM PDT 24
Finished May 12 12:41:29 PM PDT 24
Peak memory 195624 kb
Host smart-471d90c9-d3ac-48e9-a8e4-d3f360462ce7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3786466102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3786466102
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2096086673
Short name T851
Test name
Test status
Simulation time 94949929 ps
CPU time 1.1 seconds
Started May 12 12:41:30 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 197340 kb
Host smart-5f50234d-5a10-4e35-8c12-0e075bf81f6e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096086673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2096086673
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3185499516
Short name T848
Test name
Test status
Simulation time 87425309 ps
CPU time 1.31 seconds
Started May 12 12:41:34 PM PDT 24
Finished May 12 12:41:36 PM PDT 24
Peak memory 196552 kb
Host smart-1b36adfb-de16-446c-b30c-ba656e6bad85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3185499516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3185499516
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2633752257
Short name T888
Test name
Test status
Simulation time 158264170 ps
CPU time 1.47 seconds
Started May 12 12:41:46 PM PDT 24
Finished May 12 12:41:48 PM PDT 24
Peak memory 196784 kb
Host smart-56c932f1-96e6-403d-a2f1-e36024cad711
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633752257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2633752257
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2560863300
Short name T942
Test name
Test status
Simulation time 1107580171 ps
CPU time 1.27 seconds
Started May 12 12:41:31 PM PDT 24
Finished May 12 12:41:33 PM PDT 24
Peak memory 196356 kb
Host smart-fc6d1dd8-b1e8-4bff-be3d-cdab7cd6ba39
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2560863300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2560863300
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.574065377
Short name T895
Test name
Test status
Simulation time 181347215 ps
CPU time 0.84 seconds
Started May 12 12:41:42 PM PDT 24
Finished May 12 12:41:43 PM PDT 24
Peak memory 196308 kb
Host smart-c485bb2a-d9c6-4f05-ad9e-00194c4615b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574065377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.574065377
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.20661681
Short name T904
Test name
Test status
Simulation time 258609683 ps
CPU time 1.09 seconds
Started May 12 12:41:29 PM PDT 24
Finished May 12 12:41:31 PM PDT 24
Peak memory 196784 kb
Host smart-416963f8-3d47-4e07-af9a-af793fc493e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=20661681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.20661681
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.447019439
Short name T902
Test name
Test status
Simulation time 187567401 ps
CPU time 1.21 seconds
Started May 12 12:41:30 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 196544 kb
Host smart-d631887d-dc74-4f00-98e8-b78c0d5cb931
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447019439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.447019439
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2312247131
Short name T918
Test name
Test status
Simulation time 100065017 ps
CPU time 0.9 seconds
Started May 12 12:41:32 PM PDT 24
Finished May 12 12:41:34 PM PDT 24
Peak memory 196652 kb
Host smart-da196c94-69a2-44e9-8e08-d0ae66f9326b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2312247131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2312247131
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.46534320
Short name T915
Test name
Test status
Simulation time 63734033 ps
CPU time 1.13 seconds
Started May 12 12:41:51 PM PDT 24
Finished May 12 12:41:57 PM PDT 24
Peak memory 196608 kb
Host smart-7d6f22f7-00a2-4a19-b78d-c2a682f0b8ab
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46534320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.46534320
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1835336475
Short name T881
Test name
Test status
Simulation time 120827221 ps
CPU time 1.01 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:17 PM PDT 24
Peak memory 195876 kb
Host smart-92fa5e90-a490-4c62-a826-f629de4a5868
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1835336475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1835336475
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2501849535
Short name T923
Test name
Test status
Simulation time 75036490 ps
CPU time 0.99 seconds
Started May 12 12:41:30 PM PDT 24
Finished May 12 12:41:32 PM PDT 24
Peak memory 198012 kb
Host smart-f5e7f95f-e0a6-443d-b442-a0255cf8ac2f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501849535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2501849535
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3005677863
Short name T916
Test name
Test status
Simulation time 38479531 ps
CPU time 1.11 seconds
Started May 12 12:41:25 PM PDT 24
Finished May 12 12:41:27 PM PDT 24
Peak memory 197268 kb
Host smart-5ac36be7-d1aa-4ae3-93f8-f15de39a8fed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3005677863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3005677863
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2233607378
Short name T939
Test name
Test status
Simulation time 129217296 ps
CPU time 1.31 seconds
Started May 12 12:41:23 PM PDT 24
Finished May 12 12:41:25 PM PDT 24
Peak memory 196404 kb
Host smart-c5fa464c-ec9c-41f2-af8e-550bb93db198
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233607378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2233607378
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2755541260
Short name T910
Test name
Test status
Simulation time 40105565 ps
CPU time 0.91 seconds
Started May 12 12:41:22 PM PDT 24
Finished May 12 12:41:24 PM PDT 24
Peak memory 195488 kb
Host smart-3c3d4c57-fb4d-410f-b12f-ef90b0753e72
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2755541260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2755541260
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1344452517
Short name T935
Test name
Test status
Simulation time 43565770 ps
CPU time 0.9 seconds
Started May 12 12:41:15 PM PDT 24
Finished May 12 12:41:17 PM PDT 24
Peak memory 195424 kb
Host smart-8513e43c-4b82-42c2-be6c-60a4c77a0f1e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344452517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1344452517
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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