Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2848859	1			T22	103		T23	1		T24	1
all_pins[1]	2848859	1			T22	103		T23	1		T24	1
all_pins[2]	2848859	1			T22	103		T23	1		T24	1
all_pins[3]	2848859	1			T22	103		T23	1		T24	1
all_pins[4]	2848859	1			T22	103		T23	1		T24	1
all_pins[5]	2848859	1			T22	103		T23	1		T24	1
all_pins[6]	2848859	1			T22	103		T23	1		T24	1
all_pins[7]	2848859	1			T22	103		T23	1		T24	1
all_pins[8]	2848859	1			T22	103		T23	1		T24	1
all_pins[9]	2848859	1			T22	103		T23	1		T24	1
all_pins[10]	2848859	1			T22	103		T23	1		T24	1
all_pins[11]	2848859	1			T22	103		T23	1		T24	1
all_pins[12]	2848859	1			T22	103		T23	1		T24	1
all_pins[13]	2848859	1			T22	103		T23	1		T24	1
all_pins[14]	2848859	1			T22	103		T23	1		T24	1
all_pins[15]	2848859	1			T22	103		T23	1		T24	1
all_pins[16]	2848859	1			T22	103		T23	1		T24	1
all_pins[17]	2848859	1			T22	103		T23	1		T24	1
all_pins[18]	2848859	1			T22	103		T23	1		T24	1
all_pins[19]	2848859	1			T22	103		T23	1		T24	1
all_pins[20]	2848859	1			T22	103		T23	1		T24	1
all_pins[21]	2848859	1			T22	103		T23	1		T24	1
all_pins[22]	2848859	1			T22	103		T23	1		T24	1
all_pins[23]	2848859	1			T22	103		T23	1		T24	1
all_pins[24]	2848859	1			T22	103		T23	1		T24	1
all_pins[25]	2848859	1			T22	103		T23	1		T24	1
all_pins[26]	2848859	1			T22	103		T23	1		T24	1
all_pins[27]	2848859	1			T22	103		T23	1		T24	1
all_pins[28]	2848859	1			T22	103		T23	1		T24	1
all_pins[29]	2848859	1			T22	103		T23	1		T24	1
all_pins[30]	2848859	1			T22	103		T23	1		T24	1
all_pins[31]	2848859	1			T22	103		T23	1		T24	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	56648762	1			T22	1699		T23	32		T24	32
values[0x1]	34514726	1			T22	1597		T25	244349		T27	1358
transitions[0x0=>0x1]	20661076	1			T22	807		T25	146666		T27	803
transitions[0x1=>0x0]	20660922	1			T22	807		T25	146666		T27	802

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1774445	1			T22	55		T23	1		T24	1
all_pins[0]	values[0x1]	1074414	1			T22	48		T25	76995		T27	51
all_pins[0]	transitions[0x0=>0x1]	664075	1			T22	25		T25	47465		T27	38
all_pins[0]	transitions[0x1=>0x0]	668999	1			T22	26		T25	47067		T27	12
all_pins[1]	values[0x0]	1778849	1			T22	53		T23	1		T24	1
all_pins[1]	values[0x1]	1070010	1			T22	50		T25	74478		T27	32
all_pins[1]	transitions[0x0=>0x1]	641861	1			T22	31		T25	44877		T27	17
all_pins[1]	transitions[0x1=>0x0]	646265	1			T22	29		T25	47394		T27	36
all_pins[2]	values[0x0]	1771171	1			T22	51		T23	1		T24	1
all_pins[2]	values[0x1]	1077688	1			T22	52		T25	75004		T27	58
all_pins[2]	transitions[0x0=>0x1]	647911	1			T22	26		T25	45618		T27	38
all_pins[2]	transitions[0x1=>0x0]	640233	1			T22	24		T25	45092		T27	12
all_pins[3]	values[0x0]	1771530	1			T22	59		T23	1		T24	1
all_pins[3]	values[0x1]	1077329	1			T22	44		T25	77118		T27	49
all_pins[3]	transitions[0x0=>0x1]	643987	1			T22	23		T25	46875		T27	31
all_pins[3]	transitions[0x1=>0x0]	644346	1			T22	31		T25	44761		T27	40
all_pins[4]	values[0x0]	1773534	1			T22	57		T23	1		T24	1
all_pins[4]	values[0x1]	1075325	1			T22	46		T25	76132		T27	29
all_pins[4]	transitions[0x0=>0x1]	643521	1			T22	22		T25	45572		T27	20
all_pins[4]	transitions[0x1=>0x0]	645525	1			T22	20		T25	46558		T27	40
all_pins[5]	values[0x0]	1771484	1			T22	55		T23	1		T24	1
all_pins[5]	values[0x1]	1077375	1			T22	48		T25	76068		T27	49
all_pins[5]	transitions[0x0=>0x1]	645110	1			T22	27		T25	45718		T27	33
all_pins[5]	transitions[0x1=>0x0]	643060	1			T22	25		T25	45782		T27	13
all_pins[6]	values[0x0]	1768280	1			T22	45		T23	1		T24	1
all_pins[6]	values[0x1]	1080579	1			T22	58		T25	75611		T27	24
all_pins[6]	transitions[0x0=>0x1]	647265	1			T22	29		T25	45886		T27	10
all_pins[6]	transitions[0x1=>0x0]	644061	1			T22	19		T25	46343		T27	35
all_pins[7]	values[0x0]	1769840	1			T22	56		T23	1		T24	1
all_pins[7]	values[0x1]	1079019	1			T22	47		T25	75788		T27	48
all_pins[7]	transitions[0x0=>0x1]	645062	1			T22	20		T25	46099		T27	35
all_pins[7]	transitions[0x1=>0x0]	646622	1			T22	31		T25	45922		T27	11
all_pins[8]	values[0x0]	1771538	1			T22	55		T23	1		T24	1
all_pins[8]	values[0x1]	1077321	1			T22	48		T25	76220		T27	44
all_pins[8]	transitions[0x0=>0x1]	643428	1			T22	26		T25	45607		T27	19
all_pins[8]	transitions[0x1=>0x0]	645126	1			T22	25		T25	45175		T27	23
all_pins[9]	values[0x0]	1770327	1			T22	45		T23	1		T24	1
all_pins[9]	values[0x1]	1078532	1			T22	58		T25	76780		T27	45
all_pins[9]	transitions[0x0=>0x1]	644262	1			T22	31		T25	46270		T27	23
all_pins[9]	transitions[0x1=>0x0]	643051	1			T22	21		T25	45710		T27	22
all_pins[10]	values[0x0]	1770603	1			T22	47		T23	1		T24	1
all_pins[10]	values[0x1]	1078256	1			T22	56		T25	76869		T27	35
all_pins[10]	transitions[0x0=>0x1]	645048	1			T22	24		T25	45602		T27	16
all_pins[10]	transitions[0x1=>0x0]	645324	1			T22	26		T25	45513		T27	26
all_pins[11]	values[0x0]	1768118	1			T22	54		T23	1		T24	1
all_pins[11]	values[0x1]	1080741	1			T22	49		T25	75718		T27	29
all_pins[11]	transitions[0x0=>0x1]	647694	1			T22	23		T25	45883		T27	22
all_pins[11]	transitions[0x1=>0x0]	645209	1			T22	30		T25	47034		T27	28
all_pins[12]	values[0x0]	1769387	1			T22	49		T23	1		T24	1
all_pins[12]	values[0x1]	1079472	1			T22	54		T25	78323		T27	35
all_pins[12]	transitions[0x0=>0x1]	643912	1			T22	27		T25	46889		T27	25
all_pins[12]	transitions[0x1=>0x0]	645181	1			T22	22		T25	44284		T27	19
all_pins[13]	values[0x0]	1769394	1			T22	51		T23	1		T24	1
all_pins[13]	values[0x1]	1079465	1			T22	52		T25	76651		T27	33
all_pins[13]	transitions[0x0=>0x1]	645380	1			T22	24		T25	45189		T27	27
all_pins[13]	transitions[0x1=>0x0]	645387	1			T22	26		T25	46861		T27	29
all_pins[14]	values[0x0]	1772499	1			T22	63		T23	1		T24	1
all_pins[14]	values[0x1]	1076360	1			T22	40		T25	76551		T27	64
all_pins[14]	transitions[0x0=>0x1]	643106	1			T22	19		T25	46028		T27	38
all_pins[14]	transitions[0x1=>0x0]	646211	1			T22	31		T25	46128		T27	7
all_pins[15]	values[0x0]	1771323	1			T22	47		T23	1		T24	1
all_pins[15]	values[0x1]	1077536	1			T22	56		T25	76625		T27	53
all_pins[15]	transitions[0x0=>0x1]	645280	1			T22	36		T25	45933		T27	17
all_pins[15]	transitions[0x1=>0x0]	644104	1			T22	20		T25	45859		T27	28
all_pins[16]	values[0x0]	1767576	1			T22	57		T23	1		T24	1
all_pins[16]	values[0x1]	1081283	1			T22	46		T25	76460		T27	22
all_pins[16]	transitions[0x0=>0x1]	648357	1			T22	22		T25	45615		T27	8
all_pins[16]	transitions[0x1=>0x0]	644610	1			T22	32		T25	45780		T27	39
all_pins[17]	values[0x0]	1764908	1			T22	62		T23	1		T24	1
all_pins[17]	values[0x1]	1083951	1			T22	41		T25	77279		T27	49
all_pins[17]	transitions[0x0=>0x1]	647348	1			T22	23		T25	46110		T27	35
all_pins[17]	transitions[0x1=>0x0]	644680	1			T22	28		T25	45291		T27	8
all_pins[18]	values[0x0]	1774261	1			T22	61		T23	1		T24	1
all_pins[18]	values[0x1]	1074598	1			T22	42		T25	77112		T27	37
all_pins[18]	transitions[0x0=>0x1]	638741	1			T22	23		T25	45703		T27	28
all_pins[18]	transitions[0x1=>0x0]	648094	1			T22	22		T25	45870		T27	40
all_pins[19]	values[0x0]	1766016	1			T22	51		T23	1		T24	1
all_pins[19]	values[0x1]	1082843	1			T22	52		T25	75257		T27	60
all_pins[19]	transitions[0x0=>0x1]	649183	1			T22	29		T25	44267		T27	39
all_pins[19]	transitions[0x1=>0x0]	640938	1			T22	19		T25	46122		T27	16
all_pins[20]	values[0x0]	1768702	1			T22	50		T23	1		T24	1
all_pins[20]	values[0x1]	1080157	1			T22	53		T25	77001		T27	43
all_pins[20]	transitions[0x0=>0x1]	643433	1			T22	21		T25	45913		T27	12
all_pins[20]	transitions[0x1=>0x0]	646119	1			T22	20		T25	44169		T27	29
all_pins[21]	values[0x0]	1773826	1			T22	48		T23	1		T24	1
all_pins[21]	values[0x1]	1075033	1			T22	55		T25	75778		T27	46
all_pins[21]	transitions[0x0=>0x1]	642361	1			T22	24		T25	45143		T27	23
all_pins[21]	transitions[0x1=>0x0]	647485	1			T22	22		T25	46366		T27	20
all_pins[22]	values[0x0]	1767140	1			T22	53		T23	1		T24	1
all_pins[22]	values[0x1]	1081719	1			T22	50		T25	77560		T27	39
all_pins[22]	transitions[0x0=>0x1]	648878	1			T22	26		T25	46644		T27	28
all_pins[22]	transitions[0x1=>0x0]	642192	1			T22	31		T25	44862		T27	35
all_pins[23]	values[0x0]	1768656	1			T22	57		T23	1		T24	1
all_pins[23]	values[0x1]	1080203	1			T22	46		T25	75373		T27	42
all_pins[23]	transitions[0x0=>0x1]	643537	1			T22	26		T25	44539		T27	26
all_pins[23]	transitions[0x1=>0x0]	645053	1			T22	30		T25	46726		T27	23
all_pins[24]	values[0x0]	1767206	1			T22	56		T23	1		T24	1
all_pins[24]	values[0x1]	1081653	1			T22	47		T25	75563		T27	48
all_pins[24]	transitions[0x0=>0x1]	646661	1			T22	25		T25	45405		T27	21
all_pins[24]	transitions[0x1=>0x0]	645211	1			T22	24		T25	45215		T27	15
all_pins[25]	values[0x0]	1766674	1			T22	49		T23	1		T24	1
all_pins[25]	values[0x1]	1082185	1			T22	54		T25	75517		T27	77
all_pins[25]	transitions[0x0=>0x1]	647427	1			T22	29		T25	46151		T27	54
all_pins[25]	transitions[0x1=>0x0]	646895	1			T22	22		T25	46197		T27	25
all_pins[26]	values[0x0]	1772628	1			T22	54		T23	1		T24	1
all_pins[26]	values[0x1]	1076231	1			T22	49		T25	76523		T27	51
all_pins[26]	transitions[0x0=>0x1]	642042	1			T22	21		T25	46379		T27	16
all_pins[26]	transitions[0x1=>0x0]	647996	1			T22	26		T25	45373		T27	42
all_pins[27]	values[0x0]	1770437	1			T22	56		T23	1		T24	1
all_pins[27]	values[0x1]	1078422	1			T22	47		T25	75922		T27	28
all_pins[27]	transitions[0x0=>0x1]	646416	1			T22	22		T25	45702		T27	11
all_pins[27]	transitions[0x1=>0x0]	644225	1			T22	24		T25	46303		T27	34
all_pins[28]	values[0x0]	1768441	1			T22	51		T23	1		T24	1
all_pins[28]	values[0x1]	1080418	1			T22	52		T25	76857		T27	13
all_pins[28]	transitions[0x0=>0x1]	645606	1			T22	31		T25	45922		T27	13
all_pins[28]	transitions[0x1=>0x0]	643610	1			T22	26		T25	44987		T27	28
all_pins[29]	values[0x0]	1768335	1			T22	52		T23	1		T24	1
all_pins[29]	values[0x1]	1080524	1			T22	51		T25	77286		T27	44
all_pins[29]	transitions[0x0=>0x1]	643938	1			T22	23		T25	46239		T27	37
all_pins[29]	transitions[0x1=>0x0]	643832	1			T22	24		T25	45810		T27	6
all_pins[30]	values[0x0]	1772267	1			T22	46		T23	1		T24	1
all_pins[30]	values[0x1]	1076592	1			T22	57		T25	76483		T27	55
all_pins[30]	transitions[0x0=>0x1]	643806	1			T22	27		T25	45637		T27	35
all_pins[30]	transitions[0x1=>0x0]	647738	1			T22	21		T25	46440		T27	24
all_pins[31]	values[0x0]	1769367	1			T22	54		T23	1		T24	1
all_pins[31]	values[0x1]	1079492	1			T22	49		T25	76597		T27	26
all_pins[31]	transitions[0x0=>0x1]	646440	1			T22	22		T25	45782		T27	8
all_pins[31]	transitions[0x1=>0x0]	643540	1			T22	30		T25	45668		T27	37