Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	10138968	1			T22	52136		T23	332		T24	374
all_values[1]	10138968	1			T22	52136		T23	332		T24	374
all_values[2]	10138968	1			T22	52136		T23	332		T24	374
all_values[3]	10138968	1			T22	52136		T23	332		T24	374
all_values[4]	10138968	1			T22	52136		T23	332		T24	374
all_values[5]	10138968	1			T22	52136		T23	332		T24	374
all_values[6]	10138968	1			T22	52136		T23	332		T24	374
all_values[7]	10138968	1			T22	52136		T23	332		T24	374
all_values[8]	10138968	1			T22	52136		T23	332		T24	374
all_values[9]	10138968	1			T22	52136		T23	332		T24	374
all_values[10]	10138968	1			T22	52136		T23	332		T24	374
all_values[11]	10138968	1			T22	52136		T23	332		T24	374
all_values[12]	10138968	1			T22	52136		T23	332		T24	374
all_values[13]	10138968	1			T22	52136		T23	332		T24	374
all_values[14]	10138968	1			T22	52136		T23	332		T24	374
all_values[15]	10138968	1			T22	52136		T23	332		T24	374
all_values[16]	10138968	1			T22	52136		T23	332		T24	374
all_values[17]	10138968	1			T22	52136		T23	332		T24	374
all_values[18]	10138968	1			T22	52136		T23	332		T24	374
all_values[19]	10138968	1			T22	52136		T23	332		T24	374
all_values[20]	10138968	1			T22	52136		T23	332		T24	374
all_values[21]	10138968	1			T22	52136		T23	332		T24	374
all_values[22]	10138968	1			T22	52136		T23	332		T24	374
all_values[23]	10138968	1			T22	52136		T23	332		T24	374
all_values[24]	10138968	1			T22	52136		T23	332		T24	374
all_values[25]	10138968	1			T22	52136		T23	332		T24	374
all_values[26]	10138968	1			T22	52136		T23	332		T24	374
all_values[27]	10138968	1			T22	52136		T23	332		T24	374
all_values[28]	10138968	1			T22	52136		T23	332		T24	374
all_values[29]	10138968	1			T22	52136		T23	332		T24	374
all_values[30]	10138968	1			T22	52136		T23	332		T24	374
all_values[31]	10138968	1			T22	52136		T23	332		T24	374

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197049771

1

T22

166835

T23

10624

T24

11968

auto[1]

127397205

1

T25

896050

T27

3192

T30

355335

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94135486

1

T22

166835

T23

10624

T24

11968

auto[1]

230311490

1

T25

161881

T27

4994

T30

639572

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321118674

1

T22

166835

T23

10624

T24

11968

auto[1]

3328302

1

T25

212041

T30

94140

T1

610

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2550075	1			T22	52136		T23	332		T24	374
all_values[0]	auto[0]	auto[0]	auto[1]	3564071	1			T25	247250		T27	65		T30	97449
all_values[0]	auto[0]	auto[1]	auto[0]	396850	1			T25	28847		T27	18		T30	11149
all_values[0]	auto[0]	auto[1]	auto[1]	3524222	1			T25	250171		T27	97		T30	98988
all_values[0]	auto[1]	auto[0]	auto[1]	52472	1			T25	3320		T30	1547		T1	13
all_values[0]	auto[1]	auto[1]	auto[1]	51278	1			T25	3184		T30	1449		T1	5
all_values[1]	auto[0]	auto[0]	auto[0]	2555707	1			T22	52136		T23	332		T24	374
all_values[1]	auto[0]	auto[0]	auto[1]	3613085	1			T25	262866		T27	82		T30	102880
all_values[1]	auto[0]	auto[1]	auto[0]	384217	1			T25	25293		T27	22		T30	10371
all_values[1]	auto[0]	auto[1]	auto[1]	3482049	1			T25	235943		T27	65		T30	94615
all_values[1]	auto[1]	auto[0]	auto[1]	52342	1			T25	3284		T30	1448		T1	8
all_values[1]	auto[1]	auto[1]	auto[1]	51568	1			T25	3224		T30	1486		T1	9
all_values[2]	auto[0]	auto[0]	auto[0]	2549582	1			T22	52136		T23	332		T24	374
all_values[2]	auto[0]	auto[0]	auto[1]	3572404	1			T25	251435		T27	59		T30	96734
all_values[2]	auto[0]	auto[1]	auto[0]	390243	1			T25	25292		T27	16		T30	12399
all_values[2]	auto[0]	auto[1]	auto[1]	3522795	1			T25	249208		T27	99		T30	98740
all_values[2]	auto[1]	auto[0]	auto[1]	51913	1			T25	3455		T30	1442		T1	6
all_values[2]	auto[1]	auto[1]	auto[1]	52031	1			T25	3133		T30	1548		T1	15
all_values[3]	auto[0]	auto[0]	auto[0]	2553021	1			T22	52136		T23	332		T24	374
all_values[3]	auto[0]	auto[0]	auto[1]	3529743	1			T25	249645		T27	75		T30	96561
all_values[3]	auto[0]	auto[1]	auto[0]	395383	1			T25	27313		T27	8		T30	10722
all_values[3]	auto[0]	auto[1]	auto[1]	3556936	1			T25	249866		T27	97		T30	100701
all_values[3]	auto[1]	auto[0]	auto[1]	52284	1			T25	3352		T30	1534		T1	7
all_values[3]	auto[1]	auto[1]	auto[1]	51601	1			T25	3295		T30	1412		T1	12
all_values[4]	auto[0]	auto[0]	auto[0]	2546705	1			T22	52136		T23	332		T24	374
all_values[4]	auto[0]	auto[0]	auto[1]	3572940	1			T25	244547		T27	79		T30	92334
all_values[4]	auto[0]	auto[1]	auto[0]	385045	1			T25	28446		T27	25		T30	10832
all_values[4]	auto[0]	auto[1]	auto[1]	3530177	1			T25	254049		T27	61		T30	103695
all_values[4]	auto[1]	auto[0]	auto[1]	52703	1			T25	3330		T30	1460		T1	10
all_values[4]	auto[1]	auto[1]	auto[1]	51398	1			T25	3312		T30	1492		T1	11
all_values[5]	auto[0]	auto[0]	auto[0]	2549924	1			T22	52136		T23	332		T24	374
all_values[5]	auto[0]	auto[0]	auto[1]	3567012	1			T25	246110		T27	82		T30	100235
all_values[5]	auto[0]	auto[1]	auto[0]	386781	1			T25	27574		T27	18		T30	11345
all_values[5]	auto[0]	auto[1]	auto[1]	3531034	1			T25	253208		T27	85		T30	96648
all_values[5]	auto[1]	auto[0]	auto[1]	52282	1			T25	3314		T30	1478		T1	13
all_values[5]	auto[1]	auto[1]	auto[1]	51935	1			T25	3330		T30	1466		T1	10
all_values[6]	auto[0]	auto[0]	auto[0]	2552248	1			T22	52136		T23	332		T24	374
all_values[6]	auto[0]	auto[0]	auto[1]	3561544	1			T25	248432		T27	84		T30	105069
all_values[6]	auto[0]	auto[1]	auto[0]	396007	1			T25	26268		T27	27		T30	11286
all_values[6]	auto[0]	auto[1]	auto[1]	3524801	1			T25	250954		T27	56		T30	91951
all_values[6]	auto[1]	auto[0]	auto[1]	52204	1			T25	3392		T30	1477		T1	8
all_values[6]	auto[1]	auto[1]	auto[1]	52164	1			T25	3236		T30	1402		T1	13
all_values[7]	auto[0]	auto[0]	auto[0]	2550857	1			T22	52136		T23	332		T24	374
all_values[7]	auto[0]	auto[0]	auto[1]	3549714	1			T25	249913		T27	38		T30	101697
all_values[7]	auto[0]	auto[1]	auto[0]	389877	1			T25	26944		T27	36		T30	10811
all_values[7]	auto[0]	auto[1]	auto[1]	3544337	1			T25	247897		T27	96		T30	95507
all_values[7]	auto[1]	auto[0]	auto[1]	52586	1			T25	3325		T30	1444		T1	10
all_values[7]	auto[1]	auto[1]	auto[1]	51597	1			T25	3316		T30	1484		T1	8
all_values[8]	auto[0]	auto[0]	auto[0]	2551719	1			T22	52136		T23	332		T24	374
all_values[8]	auto[0]	auto[0]	auto[1]	3553988	1			T25	248324		T27	86		T30	93552
all_values[8]	auto[0]	auto[1]	auto[0]	402564	1			T25	28120		T27	15		T30	12430
all_values[8]	auto[0]	auto[1]	auto[1]	3526180	1			T25	247305		T27	80		T30	101810
all_values[8]	auto[1]	auto[0]	auto[1]	52448	1			T25	3315		T30	1611		T1	12
all_values[8]	auto[1]	auto[1]	auto[1]	52069	1			T25	3310		T30	1418		T1	6
all_values[9]	auto[0]	auto[0]	auto[0]	2559483	1			T22	52136		T23	332		T24	374
all_values[9]	auto[0]	auto[0]	auto[1]	3528580	1			T25	239707		T27	94		T30	97537
all_values[9]	auto[0]	auto[1]	auto[0]	382497	1			T25	26249		T27	9		T30	10491
all_values[9]	auto[0]	auto[1]	auto[1]	3563964	1			T25	261067		T27	83		T30	100165
all_values[9]	auto[1]	auto[0]	auto[1]	52424	1			T25	3335		T30	1435		T1	8
all_values[9]	auto[1]	auto[1]	auto[1]	52020	1			T25	3256		T30	1503		T1	11
all_values[10]	auto[0]	auto[0]	auto[0]	2555002	1			T22	52136		T23	332		T24	374
all_values[10]	auto[0]	auto[0]	auto[1]	3540924	1			T25	249051		T27	88		T30	99531
all_values[10]	auto[0]	auto[1]	auto[0]	388210	1			T25	26182		T27	21		T30	9958
all_values[10]	auto[0]	auto[1]	auto[1]	3550540	1			T25	250950		T27	63		T30	98802
all_values[10]	auto[1]	auto[0]	auto[1]	52342	1			T25	3234		T30	1459		T1	11
all_values[10]	auto[1]	auto[1]	auto[1]	51950	1			T25	3331		T30	1485		T1	13
all_values[11]	auto[0]	auto[0]	auto[0]	2547984	1			T22	52136		T23	332		T24	374
all_values[11]	auto[0]	auto[0]	auto[1]	3540955	1			T25	250047		T27	108		T30	99144
all_values[11]	auto[0]	auto[1]	auto[0]	392522	1			T25	26010		T27	16		T30	10024
all_values[11]	auto[0]	auto[1]	auto[1]	3553267	1			T25	250047		T27	51		T30	99072
all_values[11]	auto[1]	auto[0]	auto[1]	52546	1			T25	3462		T30	1511		T1	14
all_values[11]	auto[1]	auto[1]	auto[1]	51694	1			T25	3281		T30	1460		T1	11
all_values[12]	auto[0]	auto[0]	auto[0]	2548494	1			T22	52136		T23	332		T24	374
all_values[12]	auto[0]	auto[0]	auto[1]	3539672	1			T25	244748		T27	66		T30	91902
all_values[12]	auto[0]	auto[1]	auto[0]	388814	1			T25	26601		T27	26		T30	10943
all_values[12]	auto[0]	auto[1]	auto[1]	3557653	1			T25	255037		T27	80		T30	103938
all_values[12]	auto[1]	auto[0]	auto[1]	52548	1			T25	3261		T30	1464		T1	11
all_values[12]	auto[1]	auto[1]	auto[1]	51787	1			T25	3321		T30	1472		T1	6
all_values[13]	auto[0]	auto[0]	auto[0]	2555653	1			T22	52136		T23	332		T24	374
all_values[13]	auto[0]	auto[0]	auto[1]	3559839	1			T25	258081		T27	85		T30	93625
all_values[13]	auto[0]	auto[1]	auto[0]	388899	1			T25	25288		T27	15		T30	9965
all_values[13]	auto[0]	auto[1]	auto[1]	3530347	1			T25	243168		T27	56		T30	103217
all_values[13]	auto[1]	auto[0]	auto[1]	52406	1			T25	3346		T30	1462		T1	7
all_values[13]	auto[1]	auto[1]	auto[1]	51824	1			T25	3289		T30	1465		T1	12
all_values[14]	auto[0]	auto[0]	auto[0]	2548089	1			T22	52136		T23	332		T24	374
all_values[14]	auto[0]	auto[0]	auto[1]	3562412	1			T25	253138		T27	65		T30	98624
all_values[14]	auto[0]	auto[1]	auto[0]	391276	1			T25	26217		T27	22		T30	11733
all_values[14]	auto[0]	auto[1]	auto[1]	3532567	1			T25	248415		T27	105		T30	98008
all_values[14]	auto[1]	auto[0]	auto[1]	52736	1			T25	3287		T30	1435		T1	8
all_values[14]	auto[1]	auto[1]	auto[1]	51888	1			T25	3311		T30	1519		T1	11
all_values[15]	auto[0]	auto[0]	auto[0]	2552836	1			T22	52136		T23	332		T24	374
all_values[15]	auto[0]	auto[0]	auto[1]	3541543	1			T25	248819		T27	81		T30	96388
all_values[15]	auto[0]	auto[1]	auto[0]	392348	1			T25	27149		T27	28		T30	10594
all_values[15]	auto[0]	auto[1]	auto[1]	3548616	1			T25	248618		T27	81		T30	100738
all_values[15]	auto[1]	auto[0]	auto[1]	51748	1			T25	3322		T30	1525		T1	9
all_values[15]	auto[1]	auto[1]	auto[1]	51877	1			T25	3277		T30	1462		T1	10
all_values[16]	auto[0]	auto[0]	auto[0]	2554455	1			T22	52136		T23	332		T24	374
all_values[16]	auto[0]	auto[0]	auto[1]	3558905	1			T25	249050		T27	142		T30	100185
all_values[16]	auto[0]	auto[1]	auto[0]	386000	1			T25	26435		T27	10		T30	11919
all_values[16]	auto[0]	auto[1]	auto[1]	3535712	1			T25	249083		T27	41		T30	96351
all_values[16]	auto[1]	auto[0]	auto[1]	52090	1			T25	3342		T30	1478		T1	6
all_values[16]	auto[1]	auto[1]	auto[1]	51806	1			T25	3388		T30	1530		T1	12
all_values[17]	auto[0]	auto[0]	auto[0]	2545565	1			T22	52136		T23	332		T24	374
all_values[17]	auto[0]	auto[0]	auto[1]	3538537	1			T25	242828		T27	59		T30	102110
all_values[17]	auto[0]	auto[1]	auto[0]	392763	1			T25	27153		T27	16		T30	11392
all_values[17]	auto[0]	auto[1]	auto[1]	3558474	1			T25	255894		T27	100		T30	94044
all_values[17]	auto[1]	auto[0]	auto[1]	51954	1			T25	3362		T30	1430		T1	6
all_values[17]	auto[1]	auto[1]	auto[1]	51675	1			T25	3220		T30	1440		T1	12
all_values[18]	auto[0]	auto[0]	auto[0]	2549117	1			T22	52136		T23	332		T24	374
all_values[18]	auto[0]	auto[0]	auto[1]	3578207	1			T25	250189		T27	99		T30	98826
all_values[18]	auto[0]	auto[1]	auto[0]	391805	1			T25	26736		T27	23		T30	10039
all_values[18]	auto[0]	auto[1]	auto[1]	3516034	1			T25	250791		T27	56		T30	99473
all_values[18]	auto[1]	auto[0]	auto[1]	52146	1			T25	3314		T30	1512		T1	9
all_values[18]	auto[1]	auto[1]	auto[1]	51659	1			T25	3210		T30	1440		T1	9
all_values[19]	auto[0]	auto[0]	auto[0]	2545637	1			T22	52136		T23	332		T24	374
all_values[19]	auto[0]	auto[0]	auto[1]	3545796	1			T25	246983		T27	67		T30	99200
all_values[19]	auto[0]	auto[1]	auto[0]	388805	1			T25	26846		T27	28		T30	10618
all_values[19]	auto[0]	auto[1]	auto[1]	3554926	1			T25	253287		T27	98		T30	99293
all_values[19]	auto[1]	auto[0]	auto[1]	52275	1			T25	3379		T30	1449		T1	7
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User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal