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Group Instance : intr_state_cov_obj_pin20
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin20

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin20
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin21
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin21

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin21
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin22
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin22

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin22
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin23
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin23

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin23
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin24
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin24

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin24
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin25
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin25

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin25
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin26
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin26

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin26
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin27
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin27

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin27
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin28
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin28

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin28
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin29
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin29

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin29
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin30
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin30

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin30
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin31
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin31

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin31
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin5
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin6

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin6
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin7
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin8
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : intr_state_cov_obj_pin9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance intr_state_cov_obj_pin9

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance intr_state_cov_obj_pin9
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin10
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin10

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin10
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin11
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin11

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin11
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin12
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin12

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin12
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin13
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin13

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin13
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin14
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin14

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin14
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin15
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin15

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin15
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin16
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin16

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin16
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin17
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin17

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin17
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin18
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin18

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin18
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2


Group Instance : masked_oe_lower_cov_obj_pin19
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance masked_oe_lower_cov_obj_pin19

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00


Variables for Group Instance masked_oe_lower_cov_obj_pin19
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_transitions 2 0 2 100.00 100 1 1 0
cp_value 2 0 2 100.00 100 1 1 2

Go back
Group Instances:
intr_state_cov_obj_pin20
intr_state_cov_obj_pin21
intr_state_cov_obj_pin22
intr_state_cov_obj_pin23
intr_state_cov_obj_pin24
intr_state_cov_obj_pin25
intr_state_cov_obj_pin26
intr_state_cov_obj_pin27
intr_state_cov_obj_pin28
intr_state_cov_obj_pin29
intr_state_cov_obj_pin3
intr_state_cov_obj_pin30
intr_state_cov_obj_pin31
intr_state_cov_obj_pin4
intr_state_cov_obj_pin5
intr_state_cov_obj_pin6
intr_state_cov_obj_pin7
intr_state_cov_obj_pin8
intr_state_cov_obj_pin9
masked_oe_lower_cov_obj_pin0
masked_oe_lower_cov_obj_pin1
masked_oe_lower_cov_obj_pin10
masked_oe_lower_cov_obj_pin11
masked_oe_lower_cov_obj_pin12
masked_oe_lower_cov_obj_pin13
masked_oe_lower_cov_obj_pin14
masked_oe_lower_cov_obj_pin15
masked_oe_lower_cov_obj_pin16
masked_oe_lower_cov_obj_pin17
masked_oe_lower_cov_obj_pin18
masked_oe_lower_cov_obj_pin19

Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1049535 1 T25 74408 T27 16 T30 29372
rising 1049672 1 T25 74408 T27 17 T30 29372


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6404174 1 T22 52136 T23 332 T24 374
auto[1] 4009929 1 T25 279868 T27 87 T30 112087


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1045996 1 T25 75085 T27 18 T30 28555
rising 1046128 1 T25 75085 T27 18 T30 28555


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6424578 1 T22 52136 T23 332 T24 374
auto[1] 3989530 1 T25 283373 T27 89 T30 112021


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1047431 1 T25 75431 T27 15 T30 28167
rising 1047552 1 T25 75431 T27 15 T30 28167


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6410220 1 T22 52136 T23 332 T24 374
auto[1] 4004882 1 T25 283273 T27 109 T30 110569


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1044231 1 T25 74717 T27 26 T30 28391
rising 1044354 1 T25 74717 T27 27 T30 28391


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6421122 1 T22 52136 T23 332 T24 374
auto[1] 3993301 1 T25 281731 T27 92 T30 108224


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1047012 1 T25 75792 T27 14 T30 28282
rising 1047137 1 T25 75792 T27 14 T30 28282


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6396617 1 T22 52136 T23 332 T24 374
auto[1] 4017893 1 T25 277831 T27 129 T30 107933


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1045750 1 T25 75047 T27 21 T30 28776
rising 1045868 1 T25 75047 T27 22 T30 28776


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6420852 1 T22 52136 T23 332 T24 374
auto[1] 3993192 1 T25 282010 T27 105 T30 109461


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1044819 1 T25 75640 T27 16 T30 27975
rising 1044943 1 T25 75640 T27 17 T30 27975


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6411857 1 T22 52136 T23 332 T24 374
auto[1] 4002930 1 T25 281411 T27 118 T30 111130


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1046195 1 T25 74234 T27 20 T30 28441
rising 1046309 1 T25 74234 T27 21 T30 28441


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6395810 1 T22 52136 T23 332 T24 374
auto[1] 4018410 1 T25 282987 T27 72 T30 112125


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1043787 1 T25 74259 T27 16 T30 28067
rising 1043915 1 T25 74259 T27 16 T30 28067


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6401495 1 T22 52136 T23 332 T24 374
auto[1] 4013232 1 T25 283134 T27 69 T30 112608


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1048340 1 T25 75178 T27 17 T30 28439
rising 1048479 1 T25 75178 T27 17 T30 28439


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6419771 1 T22 52136 T23 332 T24 374
auto[1] 3994779 1 T25 283353 T27 64 T30 111877


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1044858 1 T25 75950 T27 21 T30 28021
rising 1044978 1 T25 75950 T27 22 T30 28021


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6413172 1 T22 52136 T23 332 T24 374
auto[1] 4001208 1 T25 280068 T27 99 T30 108477


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1044580 1 T25 75646 T27 20 T30 28794
rising 1044710 1 T25 75646 T27 21 T30 28794


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6412834 1 T22 52136 T23 332 T24 374
auto[1] 4001469 1 T25 285565 T27 110 T30 110032


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1043597 1 T25 74311 T27 21 T30 28413
rising 1043731 1 T25 74311 T27 21 T30 28413


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6415159 1 T22 52136 T23 332 T24 374
auto[1] 3999074 1 T25 276211 T27 119 T30 111682


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1046564 1 T25 75094 T27 17 T30 28078
rising 1046685 1 T25 75094 T27 17 T30 28078


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6392631 1 T22 52136 T23 332 T24 374
auto[1] 4021434 1 T25 283014 T27 81 T30 112711


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1048071 1 T25 74581 T27 21 T30 28588
rising 1048196 1 T25 74581 T27 22 T30 28588


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6415785 1 T22 52136 T23 332 T24 374
auto[1] 3999088 1 T25 285145 T27 103 T30 109558


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1046778 1 T25 75536 T27 18 T30 28191
rising 1046894 1 T25 75536 T27 18 T30 28191


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6415962 1 T22 52136 T23 332 T24 374
auto[1] 3997940 1 T25 281640 T27 90 T30 112224


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1046265 1 T25 75245 T27 21 T30 28140
rising 1046396 1 T25 75245 T27 22 T30 28140


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6405282 1 T22 52136 T23 332 T24 374
auto[1] 4009031 1 T25 279866 T27 70 T30 111291


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1044993 1 T25 75212 T27 22 T30 27931
rising 1045117 1 T25 75212 T27 22 T30 27931


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6424863 1 T22 52136 T23 332 T24 374
auto[1] 3989241 1 T25 276685 T27 99 T30 107657


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 1045566 1 T25 75100 T27 24 T30 28484
rising 1045687 1 T25 75100 T27 24 T30 28484


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6406193 1 T22 52136 T23 332 T24 374
auto[1] 4007459 1 T25 286421 T27 116 T30 113470


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69743 1 T24 12 T25 4190 T28 2
rising 69742 1 T24 11 T25 4191 T28 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139155 1 T24 23 T25 8543 T28 5
auto[1] 139938 1 T24 22 T25 8571 T28 4


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69586 1 T24 9 T25 4255 T28 4
rising 69561 1 T24 9 T25 4254 T28 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 140274 1 T24 18 T25 8577 T28 4
auto[1] 138819 1 T24 27 T25 8537 T28 5


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69605 1 T24 13 T25 4248 T28 2
rising 69598 1 T24 13 T25 4248 T28 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139783 1 T24 23 T25 8569 T28 2
auto[1] 139310 1 T24 22 T25 8545 T28 7


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69831 1 T24 12 T25 4311 T28 3
rising 69818 1 T24 13 T25 4310 T28 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139470 1 T24 23 T25 8586 T28 6
auto[1] 139623 1 T24 22 T25 8528 T28 3


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69634 1 T24 13 T25 4298 T28 2
rising 69620 1 T24 13 T25 4299 T28 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139208 1 T24 21 T25 8541 T28 7
auto[1] 139885 1 T24 24 T25 8573 T28 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69602 1 T24 10 T25 4321 T28 2
rising 69613 1 T24 10 T25 4321 T28 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139954 1 T24 30 T25 8701 T28 4
auto[1] 139139 1 T24 15 T25 8413 T28 5


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69849 1 T24 10 T25 4295 T28 3
rising 69855 1 T24 9 T25 4296 T28 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139798 1 T24 17 T25 8645 T28 4
auto[1] 139295 1 T24 28 T25 8469 T28 5


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69629 1 T24 10 T25 4289 T28 1
rising 69647 1 T24 10 T25 4289 T28 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139856 1 T24 25 T25 8528 T28 7
auto[1] 139237 1 T24 20 T25 8586 T28 2


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69838 1 T24 12 T25 4291 T28 2
rising 69835 1 T24 13 T25 4291 T28 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139223 1 T24 23 T25 8466 T28 4
auto[1] 139870 1 T24 22 T25 8648 T28 5


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69722 1 T24 10 T25 4278 T28 2
rising 69711 1 T24 11 T25 4279 T28 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139527 1 T24 24 T25 8621 T28 5
auto[1] 139566 1 T24 21 T25 8493 T28 4


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69638 1 T24 12 T25 4249 T28 2
rising 69670 1 T24 12 T25 4249 T28 2


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139397 1 T24 20 T25 8618 T28 6
auto[1] 139696 1 T24 25 T25 8496 T28 3


Summary for Variable cp_transitions

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_transitions

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
falling 69674 1 T24 10 T25 4244 T28 2
rising 69671 1 T24 10 T25 4244 T28 1


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139310 1 T24 26 T25 8505 T28 5
auto[1] 139783 1 T24 19 T25 8609 T28 4

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%