Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[1]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[2]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[3]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[4]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[5]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[6]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[7]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[8]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[9]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[10]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[11]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[12]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[13]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[14]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[15]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[16]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[17]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[18]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[19]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[20]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[21]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[22]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[23]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[24]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[25]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[26]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[27]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[28]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[29]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[30]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[31]	10001940	1			T22	52136		T23	592		T24	715

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

184914496

1

T22

840126

T23

13799

T24

18197

auto[1]

135147584

1

T22

828226

T23

5145

T24

4683

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

260347318

1

T22

166835

T23

10926

T24

16982

auto[1]

59714762

1

T23

8018

T24

5898

T25

357874

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

242794421

1

T22

166835

T23

10678

T24

11522

auto[1]

77267659

1

T23

8266

T24

11358

T25

459595

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	3719880	1			T22	25671		T23	172		T24	220
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	2927765	1			T22	26465		T23	33		T24	22
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	941803	1			T23	127		T24	89		T25	56340
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1119786	1			T23	138		T24	258		T25	81066
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	362856	1			T24	31		T25	5626		T28	14
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	929850	1			T23	122		T24	95		T25	56187
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	3720211	1			T22	26308		T23	135		T24	176
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	2929887	1			T22	25828		T23	38		T24	34
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	931461	1			T23	128		T24	128		T25	54946
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1126304	1			T23	106		T24	265		T25	82700
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	362657	1			T24	37		T25	5499		T28	1
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	931420	1			T23	185		T24	75		T25	55476
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	3711649	1			T22	27111		T23	190		T24	191
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	2931037	1			T22	25025		T23	26		T24	12
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	937480	1			T23	110		T24	55		T25	56263
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1124356	1			T23	127		T24	278		T25	82057
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	361919	1			T24	49		T25	5320		T28	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	935499	1			T23	139		T24	130		T25	55035
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	3719696	1			T22	26845		T23	169		T24	212
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	2926299	1			T22	25291		T23	34		T24	35
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	936836	1			T23	141		T24	58		T25	56236
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1125527	1			T23	138		T24	267		T25	82423
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	362490	1			T24	30		T25	5475		T28	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	931092	1			T23	110		T24	113		T25	55600
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	3721375	1			T22	25761		T23	163		T24	214
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	2929910	1			T22	26375		T23	40		T24	24
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	938041	1			T23	130		T24	121		T25	56395
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1119387	1			T23	142		T24	209		T25	81217
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	360973	1			T24	23		T25	5466		T28	24
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	932254	1			T23	117		T24	124		T25	55792
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	3716317	1			T22	26828		T23	154		T24	207
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	2929488	1			T22	25308		T23	32		T24	21
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	939588	1			T23	144		T24	62		T25	56836
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1126092	1			T23	119		T24	314		T25	83064
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	362503	1			T24	43		T25	5650		T28	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	927952	1			T23	143		T24	68		T25	55694
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	3718025	1			T22	27039		T23	176		T24	276
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	2928083	1			T22	25097		T23	27		T24	28
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	942237	1			T23	181		T24	111		T25	56007
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1119370	1			T23	108		T24	198		T25	81493
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	361467	1			T24	27		T25	5330		T28	25
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	932758	1			T23	100		T24	75		T25	54824
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	3710803	1			T22	25732		T23	183		T24	286
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	2939368	1			T22	26404		T23	31		T24	29
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	939809	1			T23	104		T24	114		T25	56540
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1119126	1			T23	119		T24	196		T25	81901
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	359802	1			T24	36		T25	5801		T30	2658
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	933032	1			T23	155		T24	54		T25	55559
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	3726913	1			T22	25468		T23	165		T24	176
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	2923817	1			T22	26668		T23	41		T24	30
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	934170	1			T23	134		T24	64		T25	56551
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1127651	1			T23	146		T24	266		T25	81977
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	359546	1			T24	42		T25	5484		T28	11
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	929843	1			T23	106		T24	137		T25	54843
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	3710953	1			T22	26591		T23	186		T24	190
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	2932165	1			T22	25545		T23	37		T24	26
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	938563	1			T23	110		T24	100		T25	55576
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1124999	1			T23	137		T24	273		T25	82698
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	361249	1			T24	52		T25	5566		T28	13
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	934011	1			T23	122		T24	74		T25	56122
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	3724036	1			T22	25121		T23	190		T24	274
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	2922388	1			T22	27015		T23	36		T24	24
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	937673	1			T23	88		T24	78		T25	55296
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1126642	1			T23	121		T24	226		T25	83317
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	362930	1			T24	42		T25	5813		T28	18
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	928271	1			T23	157		T24	71		T25	56163
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	3717214	1			T22	24632		T23	183		T24	226
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	2929309	1			T22	27504		T23	33		T24	27
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	938108	1			T23	116		T24	87		T25	56566
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1122326	1			T23	144		T24	256		T25	82241
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	361629	1			T24	29		T25	5500		T28	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	933354	1			T23	116		T24	90		T25	55859
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	3718611	1			T22	26599		T23	180		T24	278
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	2933863	1			T22	25537		T23	37		T24	34
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	936816	1			T23	123		T24	105		T25	56055
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1120704	1			T23	144		T24	167		T25	82346
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	361913	1			T24	23		T25	5578		T28	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	930033	1			T23	108		T24	108		T25	56348
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	3710957	1			T22	27009		T23	146		T24	230
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	2938128	1			T22	25127		T23	28		T24	16
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	939695	1			T23	112		T24	81		T25	55279
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1124140	1			T23	154		T24	253		T25	82617
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	361723	1			T24	36		T25	5614		T28	17
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	927297	1			T23	152		T24	99		T25	57157
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	3717709	1			T22	27537		T23	157		T24	178
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	2929589	1			T22	24599		T23	36		T24	23
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	943068	1			T23	124		T24	99		T25	56571
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1119930	1			T23	130		T24	257		T25	80777
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	359776	1			T24	31		T25	5487		T28	8
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	931868	1			T23	145		T24	127		T25	56480
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	3721912	1			T22	26796		T23	201		T24	269
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	2930013	1			T22	25340		T23	37		T24	29
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	940675	1			T23	130		T24	138		T25	55997
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1121880	1			T23	102		T24	192		T25	82200
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	361849	1			T24	27		T25	5634		T28	18
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	925611	1			T23	122		T24	60		T25	55620
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	3713386	1			T22	25089		T23	177		T24	209
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	2936195	1			T22	27047		T23	33		T24	27
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	936782	1			T23	148		T24	113		T25	55833
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1125774	1			T23	114		T24	253		T25	82327
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	363339	1			T24	27		T25	5684		T28	7
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	926464	1			T23	120		T24	86		T25	55736
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	3710281	1			T22	25279		T23	158		T24	198
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	2942102	1			T22	26857		T23	36		T24	21
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	937677	1			T23	135		T24	74		T25	55320
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1124557	1			T23	149		T24	281		T25	82218
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	362213	1			T24	34		T25	5601		T28	17
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	925110	1			T23	114		T24	107		T25	55559
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	3728734	1			T22	26073		T23	178		T24	222
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	2925613	1			T22	26063		T23	38		T24	17
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	936455	1			T23	94		T24	75		T25	56247
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1123406	1			T23	148		T24	269		T25	81915
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	364241	1			T24	42		T25	5513		T28	20
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	923491	1			T23	134		T24	90		T25	55290
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	3706198	1			T22	26218		T23	152		T24	229
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	2939244	1			T22	25918		T23	34		T24	28
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	938469	1			T23	143		T24	93		T25	55566
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1124666	1			T23	135		T24	229		T25	82373
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	360761	1			T24	28		T25	5602		T28	6
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	932602	1			T23	128		T24	108		T25	56930
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	3720998	1			T22	26315		T23	172		T24	298
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	2929705	1			T22	25821		T23	32		T24	34
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	935464	1			T23	124		T24	112		T25	55834
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1122026	1			T23	140		T24	163		T25	81212
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	361005	1			T24	25		T25	5545		T28	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	932742	1			T23	124		T24	83		T25	56450
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	3715446	1			T22	26908		T23	173		T24	283
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	2932930	1			T22	25228		T23	38		T24	39
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	936596	1			T23	145		T24	100		T25	55922
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1130001	1			T23	128		T24	215		T25	82383
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	362851	1			T24	24		T25	5798		T28	8
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	924116	1			T23	108		T24	54		T25	55681
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	3724521	1			T22	27696		T23	186		T24	255
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	2928212	1			T22	24440		T23	33		T24	42
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	935004	1			T23	114		T24	113		T25	55387
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1126422	1			T23	133		T24	205		T25	83937
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	363666	1			T24	18		T25	5649		T28	5
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	924115	1			T23	126		T24	82		T25	55415
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	3717262	1			T22	26241		T23	269		T24	244
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	2932716	1			T22	25895		T23	28		T24	32
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	937414	1			T23	100		T24	132		T25	56349
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1123580	1			T23	122		T24	222		T25	81806
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	363015	1			T24	24		T25	5749		T30	2678
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	927953	1			T23	73		T24	61		T25	55214
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	3701412	1			T22	24468		T23	182		T24	225
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	2943744	1			T22	27668		T23	32		T24	30
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	934979	1			T23	132		T24	101		T25	55784
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1128769	1			T23	133		T24	244		T25	82648
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	364964	1			T24	27		T25	5635		T28	21
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	928072	1			T23	113		T24	88		T25	55857
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	3716604	1			T22	26753		T23	166		T24	234
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	2941358	1			T22	25383		T23	40		T24	31
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	933372	1			T23	116		T24	101		T25	56309
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1124267	1			T23	145		T24	269		T25	81994
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	361481	1			T24	24		T25	5624		T28	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	924858	1			T23	125		T24	56		T25	56546
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	3727822	1			T22	27707		T23	160		T24	217
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	2926380	1			T22	24429		T23	36		T24	26
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	934785	1			T23	137		T24	105		T25	56522
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1122514	1			T23	128		T24	244		T25	81852
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	363183	1			T24	29		T25	5576		T28	7
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	927256	1			T23	131		T24	94		T25	55190
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	3722825	1			T22	27018		T23	205		T24	235
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	2927223	1			T22	25118		T23	32		T24	36
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	937529	1			T23	111		T24	106		T25	56671
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1127149	1			T23	134		T24	228		T25	82337
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	361109	1			T24	25		T25	5575		T28	26
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	926105	1			T23	110		T24	85		T25	55346
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	3715040	1			T22	26820		T23	192		T24	297
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	2942225	1			T22	25316		T23	33		T24	37
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	940088	1			T23	88		T24	113		T25	56397
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1117322	1			T23	142		T24	190		T25	81498
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	361563	1			T24	16		T25	5423		T28	22
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	925702	1			T23	137		T24	62		T25	55734
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	3714562	1			T22	24910		T23	172		T24	240
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	2938284	1			T22	27226		T23	38		T24	33
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	936912	1			T23	98		T24	58		T25	56335
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1124596	1			T23	142		T24	260		T25	80948
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	360547	1			T24	20		T25	5486		T28	8
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	927039	1			T23	142		T24	104		T25	56748
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	3725327	1			T22	24482		T23	136		T24	271
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	2931814	1			T22	27654		T23	38		T24	35
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	931201	1			T23	163		T24	85		T25	55070
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1126632	1			T23	119		T24	192		T25	83598
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	361402	1			T24	11		T25	6017		T28	30
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	925564	1			T23	136		T24	121		T25	56101
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	3713447	1			T22	27101		T23	173		T24	280
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	2943443	1			T22	25035		T23	35		T24	24
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	933248	1			T23	125		T24	105		T25	55235
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1122471	1			T23	136		T24	242		T25	83279
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	361901	1			T24	23		T25	5713		T28	6
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	927430	1			T23	123		T24	41		T25	55950

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal