Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[1]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[2]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[3]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[4]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[5]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[6]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[7]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[8]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[9]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[10]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[11]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[12]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[13]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[14]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[15]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[16]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[17]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[18]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[19]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[20]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[21]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[22]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[23]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[24]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[25]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[26]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[27]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[28]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[29]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[30]	10001940	1			T22	52136		T23	592		T24	715
bins_for_gpio_bits[31]	10001940	1			T22	52136		T23	592		T24	715

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

184914496

1

T22

840126

T23

13799

T24

18197

auto[1]

135147584

1

T22

828226

T23

5145

T24

4683

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

184906720

1

T22

840126

T23

13789

T24

18187

auto[1]

135155360

1

T22

828226

T23

5155

T24

4693

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	5613731	1			T22	25671		T23	407		T24	547
bins_for_gpio_bits[0]	auto[0]	auto[1]	167460	1			T23	30		T24	20		T25	9824
bins_for_gpio_bits[0]	auto[1]	auto[0]	167738	1			T23	30		T24	20		T25	9825
bins_for_gpio_bits[0]	auto[1]	auto[1]	4053011	1			T22	26465		T23	125		T24	128
bins_for_gpio_bits[1]	auto[0]	auto[0]	5610700	1			T22	26308		T23	332		T24	553
bins_for_gpio_bits[1]	auto[0]	auto[1]	167047	1			T23	36		T24	15		T25	9736
bins_for_gpio_bits[1]	auto[1]	auto[0]	167276	1			T23	37		T24	16		T25	9737
bins_for_gpio_bits[1]	auto[1]	auto[1]	4056917	1			T22	25828		T23	187		T24	131
bins_for_gpio_bits[2]	auto[0]	auto[0]	5605796	1			T22	27111		T23	396		T24	499
bins_for_gpio_bits[2]	auto[0]	auto[1]	167448	1			T23	30		T24	24		T25	9796
bins_for_gpio_bits[2]	auto[1]	auto[0]	167689	1			T23	31		T24	25		T25	9798
bins_for_gpio_bits[2]	auto[1]	auto[1]	4061007	1			T22	25025		T23	135		T24	167
bins_for_gpio_bits[3]	auto[0]	auto[0]	5614570	1			T22	26845		T23	418		T24	516
bins_for_gpio_bits[3]	auto[0]	auto[1]	167282	1			T23	30		T24	21		T25	9810
bins_for_gpio_bits[3]	auto[1]	auto[0]	167489	1			T23	30		T24	21		T25	9810
bins_for_gpio_bits[3]	auto[1]	auto[1]	4052599	1			T22	25291		T23	114		T24	157
bins_for_gpio_bits[4]	auto[0]	auto[0]	5611107	1			T22	25761		T23	409		T24	521
bins_for_gpio_bits[4]	auto[0]	auto[1]	167448	1			T23	26		T24	22		T25	9869
bins_for_gpio_bits[4]	auto[1]	auto[0]	167696	1			T23	26		T24	23		T25	9872
bins_for_gpio_bits[4]	auto[1]	auto[1]	4055689	1			T22	26375		T23	131		T24	149
bins_for_gpio_bits[5]	auto[0]	auto[0]	5614370	1			T22	26828		T23	383		T24	570
bins_for_gpio_bits[5]	auto[0]	auto[1]	167361	1			T23	34		T24	13		T25	9898
bins_for_gpio_bits[5]	auto[1]	auto[0]	167627	1			T23	34		T24	13		T25	9898
bins_for_gpio_bits[5]	auto[1]	auto[1]	4052582	1			T22	25308		T23	141		T24	119
bins_for_gpio_bits[6]	auto[0]	auto[0]	5612408	1			T22	27039		T23	433		T24	572
bins_for_gpio_bits[6]	auto[0]	auto[1]	167014	1			T23	32		T24	13		T25	9674
bins_for_gpio_bits[6]	auto[1]	auto[0]	167224	1			T23	32		T24	13		T25	9675
bins_for_gpio_bits[6]	auto[1]	auto[1]	4055294	1			T22	25097		T23	95		T24	117
bins_for_gpio_bits[7]	auto[0]	auto[0]	5602136	1			T22	25732		T23	377		T24	582
bins_for_gpio_bits[7]	auto[0]	auto[1]	167371	1			T23	29		T24	13		T25	9862
bins_for_gpio_bits[7]	auto[1]	auto[0]	167602	1			T23	29		T24	14		T25	9863
bins_for_gpio_bits[7]	auto[1]	auto[1]	4064831	1			T22	26404		T23	157		T24	106
bins_for_gpio_bits[8]	auto[0]	auto[0]	5621388	1			T22	25468		T23	412		T24	488
bins_for_gpio_bits[8]	auto[0]	auto[1]	167108	1			T23	33		T24	17		T25	9710
bins_for_gpio_bits[8]	auto[1]	auto[0]	167346	1			T23	33		T24	18		T25	9710
bins_for_gpio_bits[8]	auto[1]	auto[1]	4046098	1			T22	26668		T23	114		T24	192
bins_for_gpio_bits[9]	auto[0]	auto[0]	5606906	1			T22	26591		T23	398		T24	546
bins_for_gpio_bits[9]	auto[0]	auto[1]	167396	1			T23	35		T24	17		T25	9773
bins_for_gpio_bits[9]	auto[1]	auto[0]	167609	1			T23	35		T24	17		T25	9774
bins_for_gpio_bits[9]	auto[1]	auto[1]	4060029	1			T22	25545		T23	124		T24	135
bins_for_gpio_bits[10]	auto[0]	auto[0]	5620861	1			T22	25121		T23	365		T24	562
bins_for_gpio_bits[10]	auto[0]	auto[1]	167295	1			T23	33		T24	16		T25	9944
bins_for_gpio_bits[10]	auto[1]	auto[0]	167490	1			T23	34		T24	16		T25	9944
bins_for_gpio_bits[10]	auto[1]	auto[1]	4046294	1			T22	27015		T23	160		T24	121
bins_for_gpio_bits[11]	auto[0]	auto[0]	5610119	1			T22	24632		T23	411		T24	555
bins_for_gpio_bits[11]	auto[0]	auto[1]	167303	1			T23	32		T24	14		T25	9917
bins_for_gpio_bits[11]	auto[1]	auto[0]	167529	1			T23	32		T24	14		T25	9917
bins_for_gpio_bits[11]	auto[1]	auto[1]	4056989	1			T22	27504		T23	117		T24	132
bins_for_gpio_bits[12]	auto[0]	auto[0]	5609211	1			T22	26599		T23	418		T24	537
bins_for_gpio_bits[12]	auto[0]	auto[1]	166696	1			T23	29		T24	13		T25	9887
bins_for_gpio_bits[12]	auto[1]	auto[0]	166920	1			T23	29		T24	13		T25	9889
bins_for_gpio_bits[12]	auto[1]	auto[1]	4059113	1			T22	25537		T23	116		T24	152
bins_for_gpio_bits[13]	auto[0]	auto[0]	5607756	1			T22	27009		T23	373		T24	548
bins_for_gpio_bits[13]	auto[0]	auto[1]	166802	1			T23	39		T24	16		T25	10065
bins_for_gpio_bits[13]	auto[1]	auto[0]	167036	1			T23	39		T24	16		T25	10067
bins_for_gpio_bits[13]	auto[1]	auto[1]	4060346	1			T22	25127		T23	141		T24	135
bins_for_gpio_bits[14]	auto[0]	auto[0]	5612997	1			T22	27537		T23	378		T24	516
bins_for_gpio_bits[14]	auto[0]	auto[1]	167467	1			T23	32		T24	17		T25	9886
bins_for_gpio_bits[14]	auto[1]	auto[0]	167710	1			T23	33		T24	18		T25	9886
bins_for_gpio_bits[14]	auto[1]	auto[1]	4053766	1			T22	24599		T23	149		T24	164
bins_for_gpio_bits[15]	auto[0]	auto[0]	5617629	1			T22	26796		T23	405		T24	584
bins_for_gpio_bits[15]	auto[0]	auto[1]	166592	1			T23	28		T24	15		T25	9836
bins_for_gpio_bits[15]	auto[1]	auto[0]	166838	1			T23	28		T24	15		T25	9836
bins_for_gpio_bits[15]	auto[1]	auto[1]	4050881	1			T22	25340		T23	131		T24	101
bins_for_gpio_bits[16]	auto[0]	auto[0]	5608579	1			T22	25089		T23	404		T24	561
bins_for_gpio_bits[16]	auto[0]	auto[1]	167096	1			T23	35		T24	13		T25	9797
bins_for_gpio_bits[16]	auto[1]	auto[0]	167363	1			T23	35		T24	14		T25	9798
bins_for_gpio_bits[16]	auto[1]	auto[1]	4058902	1			T22	27047		T23	118		T24	127
bins_for_gpio_bits[17]	auto[0]	auto[0]	5605257	1			T22	25279		T23	410		T24	533
bins_for_gpio_bits[17]	auto[0]	auto[1]	167023	1			T23	32		T24	20		T25	9761
bins_for_gpio_bits[17]	auto[1]	auto[0]	167258	1			T23	32		T24	20		T25	9761
bins_for_gpio_bits[17]	auto[1]	auto[1]	4062402	1			T22	26857		T23	118		T24	142
bins_for_gpio_bits[18]	auto[0]	auto[0]	5621119	1			T22	26073		T23	385		T24	550
bins_for_gpio_bits[18]	auto[0]	auto[1]	167226	1			T23	35		T24	16		T25	9785
bins_for_gpio_bits[18]	auto[1]	auto[0]	167476	1			T23	35		T24	16		T25	9788
bins_for_gpio_bits[18]	auto[1]	auto[1]	4046119	1			T22	26063		T23	137		T24	133
bins_for_gpio_bits[19]	auto[0]	auto[0]	5601095	1			T22	26218		T23	393		T24	534
bins_for_gpio_bits[19]	auto[0]	auto[1]	168000	1			T23	37		T24	17		T25	9988
bins_for_gpio_bits[19]	auto[1]	auto[0]	168238	1			T23	37		T24	17		T25	9988
bins_for_gpio_bits[19]	auto[1]	auto[1]	4064607	1			T22	25918		T23	125		T24	147
bins_for_gpio_bits[20]	auto[0]	auto[0]	5610392	1			T22	26315		T23	403		T24	560
bins_for_gpio_bits[20]	auto[0]	auto[1]	167875	1			T23	33		T24	12		T25	9969
bins_for_gpio_bits[20]	auto[1]	auto[0]	168096	1			T23	33		T24	13		T25	9969
bins_for_gpio_bits[20]	auto[1]	auto[1]	4055577	1			T22	25821		T23	123		T24	130
bins_for_gpio_bits[21]	auto[0]	auto[0]	5614080	1			T22	26908		T23	406		T24	585
bins_for_gpio_bits[21]	auto[0]	auto[1]	167744	1			T23	40		T24	12		T25	9802
bins_for_gpio_bits[21]	auto[1]	auto[0]	167963	1			T23	40		T24	13		T25	9805
bins_for_gpio_bits[21]	auto[1]	auto[1]	4052153	1			T22	25228		T23	106		T24	105
bins_for_gpio_bits[22]	auto[0]	auto[0]	5618721	1			T22	27696		T23	404		T24	556
bins_for_gpio_bits[22]	auto[0]	auto[1]	166974	1			T23	29		T24	17		T25	9896
bins_for_gpio_bits[22]	auto[1]	auto[0]	167226	1			T23	29		T24	17		T25	9896
bins_for_gpio_bits[22]	auto[1]	auto[1]	4049019	1			T22	24440		T23	130		T24	125
bins_for_gpio_bits[23]	auto[0]	auto[0]	5610472	1			T22	26241		T23	471		T24	583
bins_for_gpio_bits[23]	auto[0]	auto[1]	167537	1			T23	19		T24	15		T25	9816
bins_for_gpio_bits[23]	auto[1]	auto[0]	167784	1			T23	20		T24	15		T25	9818
bins_for_gpio_bits[23]	auto[1]	auto[1]	4056147	1			T22	25895		T23	82		T24	102
bins_for_gpio_bits[24]	auto[0]	auto[0]	5597482	1			T22	24468		T23	418		T24	555
bins_for_gpio_bits[24]	auto[0]	auto[1]	167422	1			T23	28		T24	15		T25	9927
bins_for_gpio_bits[24]	auto[1]	auto[0]	167678	1			T23	29		T24	15		T25	9928
bins_for_gpio_bits[24]	auto[1]	auto[1]	4069358	1			T22	27668		T23	117		T24	130
bins_for_gpio_bits[25]	auto[0]	auto[0]	5606956	1			T22	26753		T23	393		T24	590
bins_for_gpio_bits[25]	auto[0]	auto[1]	167027	1			T23	33		T24	14		T25	9838
bins_for_gpio_bits[25]	auto[1]	auto[0]	167287	1			T23	34		T24	14		T25	9840
bins_for_gpio_bits[25]	auto[1]	auto[1]	4060670	1			T22	25383		T23	132		T24	97
bins_for_gpio_bits[26]	auto[0]	auto[0]	5618085	1			T22	27707		T23	397		T24	545
bins_for_gpio_bits[26]	auto[0]	auto[1]	166751	1			T23	27		T24	21		T25	9721
bins_for_gpio_bits[26]	auto[1]	auto[0]	167036	1			T23	28		T24	21		T25	9723
bins_for_gpio_bits[26]	auto[1]	auto[1]	4050068	1			T22	24429		T23	140		T24	128
bins_for_gpio_bits[27]	auto[0]	auto[0]	5620049	1			T22	27018		T23	420		T24	552
bins_for_gpio_bits[27]	auto[0]	auto[1]	167193	1			T23	30		T24	16		T25	9853
bins_for_gpio_bits[27]	auto[1]	auto[0]	167454	1			T23	30		T24	17		T25	9853
bins_for_gpio_bits[27]	auto[1]	auto[1]	4047244	1			T22	25118		T23	112		T24	130
bins_for_gpio_bits[28]	auto[0]	auto[0]	5605032	1			T22	26820		T23	393		T24	586
bins_for_gpio_bits[28]	auto[0]	auto[1]	167120	1			T23	28		T24	14		T25	9860
bins_for_gpio_bits[28]	auto[1]	auto[0]	167418	1			T23	29		T24	14		T25	9861
bins_for_gpio_bits[28]	auto[1]	auto[1]	4062370	1			T22	25316		T23	142		T24	101
bins_for_gpio_bits[29]	auto[0]	auto[0]	5607662	1			T22	24910		T23	380		T24	539
bins_for_gpio_bits[29]	auto[0]	auto[1]	168148	1			T23	32		T24	19		T25	9926
bins_for_gpio_bits[29]	auto[1]	auto[0]	168408	1			T23	32		T24	19		T25	9928
bins_for_gpio_bits[29]	auto[1]	auto[1]	4057722	1			T22	27226		T23	148		T24	138
bins_for_gpio_bits[30]	auto[0]	auto[0]	5615711	1			T22	24482		T23	386		T24	526
bins_for_gpio_bits[30]	auto[0]	auto[1]	167231	1			T23	32		T24	22		T25	9854
bins_for_gpio_bits[30]	auto[1]	auto[0]	167449	1			T23	32		T24	22		T25	9855
bins_for_gpio_bits[30]	auto[1]	auto[1]	4051549	1			T22	27654		T23	142		T24	145
bins_for_gpio_bits[31]	auto[0]	auto[0]	5601637	1			T22	27101		T23	401		T24	617
bins_for_gpio_bits[31]	auto[0]	auto[1]	167249	1			T23	32		T24	10		T25	9910
bins_for_gpio_bits[31]	auto[1]	auto[0]	167529	1			T23	33		T24	10		T25	9910
bins_for_gpio_bits[31]	auto[1]	auto[1]	4065525	1			T22	25035		T23	126		T24	78