Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6166618 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3972350 |
1 |
|
|
T25 |
282202 |
|
T27 |
115 |
|
T30 |
111586 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9629693 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
509275 |
1 |
|
|
T25 |
37926 |
|
T27 |
4 |
|
T30 |
12757 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6163747 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3975221 |
1 |
|
|
T25 |
287520 |
|
T27 |
87 |
|
T30 |
104984 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1743289 |
1 |
|
|
T25 |
124680 |
|
T27 |
47 |
|
T30 |
45094 |
| auto[1] |
auto[0] |
auto[1] |
256659 |
1 |
|
|
T25 |
18713 |
|
T27 |
1 |
|
T30 |
6030 |
| auto[1] |
auto[1] |
auto[0] |
1722657 |
1 |
|
|
T25 |
124914 |
|
T27 |
36 |
|
T30 |
47133 |
| auto[1] |
auto[1] |
auto[1] |
252616 |
1 |
|
|
T25 |
19213 |
|
T27 |
3 |
|
T30 |
6727 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6221134 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3917834 |
1 |
|
|
T25 |
264460 |
|
T27 |
87 |
|
T30 |
106472 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9627835 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
511133 |
1 |
|
|
T25 |
36968 |
|
T27 |
4 |
|
T30 |
14638 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6155844 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3983124 |
1 |
|
|
T25 |
279000 |
|
T27 |
100 |
|
T30 |
113884 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1757968 |
1 |
|
|
T25 |
125293 |
|
T27 |
43 |
|
T30 |
50192 |
| auto[1] |
auto[0] |
auto[1] |
259362 |
1 |
|
|
T25 |
19134 |
|
T27 |
3 |
|
T30 |
7399 |
| auto[1] |
auto[1] |
auto[0] |
1714023 |
1 |
|
|
T25 |
116739 |
|
T27 |
53 |
|
T30 |
49054 |
| auto[1] |
auto[1] |
auto[1] |
251771 |
1 |
|
|
T25 |
17834 |
|
T27 |
1 |
|
T30 |
7239 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6148268 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3990700 |
1 |
|
|
T25 |
280463 |
|
T27 |
84 |
|
T30 |
110245 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9626440 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
512528 |
1 |
|
|
T25 |
37002 |
|
T27 |
4 |
|
T30 |
14907 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6152781 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3986187 |
1 |
|
|
T25 |
279811 |
|
T27 |
91 |
|
T30 |
117054 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1724480 |
1 |
|
|
T25 |
117538 |
|
T27 |
50 |
|
T30 |
50021 |
| auto[1] |
auto[0] |
auto[1] |
253410 |
1 |
|
|
T25 |
17971 |
|
T27 |
2 |
|
T30 |
7270 |
| auto[1] |
auto[1] |
auto[0] |
1749179 |
1 |
|
|
T25 |
125271 |
|
T27 |
37 |
|
T30 |
52126 |
| auto[1] |
auto[1] |
auto[1] |
259118 |
1 |
|
|
T25 |
19031 |
|
T27 |
2 |
|
T30 |
7637 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6141485 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3997483 |
1 |
|
|
T25 |
279338 |
|
T27 |
67 |
|
T30 |
110556 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9627974 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
510994 |
1 |
|
|
T25 |
36405 |
|
T27 |
5 |
|
T30 |
13996 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6156110 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3982858 |
1 |
|
|
T25 |
277880 |
|
T27 |
82 |
|
T30 |
112339 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1733659 |
1 |
|
|
T25 |
121993 |
|
T27 |
50 |
|
T30 |
47183 |
| auto[1] |
auto[0] |
auto[1] |
254483 |
1 |
|
|
T25 |
18391 |
|
T27 |
3 |
|
T30 |
6466 |
| auto[1] |
auto[1] |
auto[0] |
1738205 |
1 |
|
|
T25 |
119482 |
|
T27 |
27 |
|
T30 |
51160 |
| auto[1] |
auto[1] |
auto[1] |
256511 |
1 |
|
|
T25 |
18014 |
|
T27 |
2 |
|
T30 |
7530 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6140714 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3998254 |
1 |
|
|
T25 |
284959 |
|
T27 |
106 |
|
T30 |
116353 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9624445 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
514523 |
1 |
|
|
T25 |
36319 |
|
T27 |
3 |
|
T30 |
14091 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6134843 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
4004125 |
1 |
|
|
T25 |
275785 |
|
T27 |
90 |
|
T30 |
112464 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1740424 |
1 |
|
|
T25 |
118369 |
|
T27 |
33 |
|
T30 |
45248 |
| auto[1] |
auto[0] |
auto[1] |
256153 |
1 |
|
|
T25 |
17707 |
|
T30 |
6306 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1749178 |
1 |
|
|
T25 |
121097 |
|
T27 |
54 |
|
T30 |
53125 |
| auto[1] |
auto[1] |
auto[1] |
258370 |
1 |
|
|
T25 |
18612 |
|
T27 |
3 |
|
T30 |
7785 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6167898 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3971070 |
1 |
|
|
T25 |
271745 |
|
T27 |
71 |
|
T30 |
114647 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9631808 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
507160 |
1 |
|
|
T25 |
36753 |
|
T27 |
5 |
|
T30 |
13703 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6183577 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3955391 |
1 |
|
|
T25 |
278280 |
|
T27 |
140 |
|
T30 |
110056 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1731166 |
1 |
|
|
T25 |
123881 |
|
T27 |
91 |
|
T30 |
44276 |
| auto[1] |
auto[0] |
auto[1] |
254026 |
1 |
|
|
T25 |
18874 |
|
T27 |
3 |
|
T30 |
6076 |
| auto[1] |
auto[1] |
auto[0] |
1717065 |
1 |
|
|
T25 |
117646 |
|
T27 |
44 |
|
T30 |
52077 |
| auto[1] |
auto[1] |
auto[1] |
253134 |
1 |
|
|
T25 |
17879 |
|
T27 |
2 |
|
T30 |
7627 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6163237 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3975731 |
1 |
|
|
T25 |
277943 |
|
T27 |
127 |
|
T30 |
111260 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9624805 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
514163 |
1 |
|
|
T25 |
37957 |
|
T27 |
2 |
|
T30 |
13108 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6141639 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3997329 |
1 |
|
|
T25 |
284123 |
|
T27 |
88 |
|
T30 |
104761 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1744135 |
1 |
|
|
T25 |
123464 |
|
T27 |
37 |
|
T30 |
45399 |
| auto[1] |
auto[0] |
auto[1] |
257710 |
1 |
|
|
T25 |
18931 |
|
T27 |
1 |
|
T30 |
6586 |
| auto[1] |
auto[1] |
auto[0] |
1739031 |
1 |
|
|
T25 |
122702 |
|
T27 |
49 |
|
T30 |
46254 |
| auto[1] |
auto[1] |
auto[1] |
256453 |
1 |
|
|
T25 |
19026 |
|
T27 |
1 |
|
T30 |
6522 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6146127 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3992841 |
1 |
|
|
T25 |
279044 |
|
T27 |
109 |
|
T30 |
112794 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9627698 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
511270 |
1 |
|
|
T25 |
37998 |
|
T27 |
1 |
|
T30 |
14115 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6153669 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3985299 |
1 |
|
|
T25 |
288732 |
|
T27 |
96 |
|
T30 |
112760 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1727647 |
1 |
|
|
T25 |
125427 |
|
T27 |
42 |
|
T30 |
48495 |
| auto[1] |
auto[0] |
auto[1] |
254831 |
1 |
|
|
T25 |
18931 |
|
T30 |
6874 |
|
T1 |
2 |
| auto[1] |
auto[1] |
auto[0] |
1746382 |
1 |
|
|
T25 |
125307 |
|
T27 |
53 |
|
T30 |
50150 |
| auto[1] |
auto[1] |
auto[1] |
256439 |
1 |
|
|
T25 |
19067 |
|
T27 |
1 |
|
T30 |
7241 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6165450 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3973518 |
1 |
|
|
T25 |
278906 |
|
T27 |
51 |
|
T30 |
109800 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9624980 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
513988 |
1 |
|
|
T25 |
38686 |
|
T27 |
2 |
|
T30 |
14000 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6140370 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3998598 |
1 |
|
|
T25 |
290024 |
|
T27 |
72 |
|
T30 |
111586 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1744009 |
1 |
|
|
T25 |
125154 |
|
T27 |
50 |
|
T30 |
49190 |
| auto[1] |
auto[0] |
auto[1] |
257185 |
1 |
|
|
T25 |
19344 |
|
T27 |
2 |
|
T30 |
7180 |
| auto[1] |
auto[1] |
auto[0] |
1740601 |
1 |
|
|
T25 |
126184 |
|
T27 |
20 |
|
T30 |
48396 |
| auto[1] |
auto[1] |
auto[1] |
256803 |
1 |
|
|
T25 |
19342 |
|
T30 |
6820 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6136056 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
4002912 |
1 |
|
|
T25 |
286267 |
|
T27 |
116 |
|
T30 |
106876 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9632035 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
506933 |
1 |
|
|
T25 |
36846 |
|
T27 |
3 |
|
T30 |
13102 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6179879 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3959089 |
1 |
|
|
T25 |
279737 |
|
T27 |
78 |
|
T30 |
104843 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1731820 |
1 |
|
|
T25 |
119499 |
|
T27 |
31 |
|
T30 |
46576 |
| auto[1] |
auto[0] |
auto[1] |
254901 |
1 |
|
|
T25 |
18185 |
|
T27 |
1 |
|
T30 |
6680 |
| auto[1] |
auto[1] |
auto[0] |
1720336 |
1 |
|
|
T25 |
123392 |
|
T27 |
44 |
|
T30 |
45165 |
| auto[1] |
auto[1] |
auto[1] |
252032 |
1 |
|
|
T25 |
18661 |
|
T27 |
2 |
|
T30 |
6422 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6179470 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3959498 |
1 |
|
|
T25 |
280737 |
|
T27 |
79 |
|
T30 |
110952 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9629754 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
509214 |
1 |
|
|
T25 |
36376 |
|
T27 |
3 |
|
T30 |
14539 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6170748 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3968220 |
1 |
|
|
T25 |
275922 |
|
T27 |
94 |
|
T30 |
115418 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1747843 |
1 |
|
|
T25 |
119256 |
|
T27 |
51 |
|
T30 |
52207 |
| auto[1] |
auto[0] |
auto[1] |
256899 |
1 |
|
|
T25 |
18130 |
|
T27 |
3 |
|
T30 |
7546 |
| auto[1] |
auto[1] |
auto[0] |
1711163 |
1 |
|
|
T25 |
120290 |
|
T27 |
40 |
|
T30 |
48672 |
| auto[1] |
auto[1] |
auto[1] |
252315 |
1 |
|
|
T25 |
18246 |
|
T30 |
6993 |
|
T1 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6143708 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3995260 |
1 |
|
|
T25 |
283431 |
|
T27 |
126 |
|
T30 |
111384 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9626367 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
512601 |
1 |
|
|
T25 |
37395 |
|
T27 |
3 |
|
T30 |
13234 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6153112 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3985856 |
1 |
|
|
T25 |
282607 |
|
T27 |
96 |
|
T30 |
106897 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1732189 |
1 |
|
|
T25 |
120307 |
|
T27 |
22 |
|
T30 |
46592 |
| auto[1] |
auto[0] |
auto[1] |
255654 |
1 |
|
|
T25 |
18259 |
|
T27 |
1 |
|
T30 |
6673 |
| auto[1] |
auto[1] |
auto[0] |
1741066 |
1 |
|
|
T25 |
124905 |
|
T27 |
71 |
|
T30 |
47071 |
| auto[1] |
auto[1] |
auto[1] |
256947 |
1 |
|
|
T25 |
19136 |
|
T27 |
2 |
|
T30 |
6561 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6173899 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3965069 |
1 |
|
|
T25 |
277633 |
|
T27 |
115 |
|
T30 |
112687 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9630576 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
508392 |
1 |
|
|
T25 |
35397 |
|
T27 |
3 |
|
T30 |
13366 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6172747 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3966221 |
1 |
|
|
T25 |
272623 |
|
T27 |
57 |
|
T30 |
106325 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1738894 |
1 |
|
|
T25 |
119929 |
|
T27 |
30 |
|
T30 |
46741 |
| auto[1] |
auto[0] |
auto[1] |
255329 |
1 |
|
|
T25 |
17825 |
|
T27 |
3 |
|
T30 |
6705 |
| auto[1] |
auto[1] |
auto[0] |
1718935 |
1 |
|
|
T25 |
117297 |
|
T27 |
24 |
|
T30 |
46218 |
| auto[1] |
auto[1] |
auto[1] |
253063 |
1 |
|
|
T25 |
17572 |
|
T30 |
6661 |
|
T1 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6136829 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
4002139 |
1 |
|
|
T25 |
283743 |
|
T27 |
111 |
|
T30 |
109238 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9626283 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
512685 |
1 |
|
|
T25 |
36402 |
|
T27 |
2 |
|
T30 |
13893 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6158516 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3980452 |
1 |
|
|
T25 |
278185 |
|
T27 |
72 |
|
T30 |
110361 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1734061 |
1 |
|
|
T25 |
117531 |
|
T27 |
38 |
|
T30 |
49024 |
| auto[1] |
auto[0] |
auto[1] |
255627 |
1 |
|
|
T25 |
17493 |
|
T30 |
7040 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1733706 |
1 |
|
|
T25 |
124252 |
|
T27 |
32 |
|
T30 |
47444 |
| auto[1] |
auto[1] |
auto[1] |
257058 |
1 |
|
|
T25 |
18909 |
|
T27 |
2 |
|
T30 |
6853 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6151194 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3987774 |
1 |
|
|
T25 |
281790 |
|
T27 |
133 |
|
T30 |
111766 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9629669 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
509299 |
1 |
|
|
T25 |
36319 |
|
T27 |
3 |
|
T30 |
13321 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6171903 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3967065 |
1 |
|
|
T25 |
276928 |
|
T27 |
92 |
|
T30 |
106412 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1729496 |
1 |
|
|
T25 |
119959 |
|
T27 |
28 |
|
T30 |
46813 |
| auto[1] |
auto[0] |
auto[1] |
253528 |
1 |
|
|
T25 |
18092 |
|
T30 |
6704 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
1728270 |
1 |
|
|
T25 |
120650 |
|
T27 |
61 |
|
T30 |
46278 |
| auto[1] |
auto[1] |
auto[1] |
255771 |
1 |
|
|
T25 |
18227 |
|
T27 |
3 |
|
T30 |
6617 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6156243 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3982725 |
1 |
|
|
T25 |
286189 |
|
T27 |
92 |
|
T30 |
107979 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9627185 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
511783 |
1 |
|
|
T25 |
35833 |
|
T27 |
4 |
|
T30 |
13520 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6149711 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3989257 |
1 |
|
|
T25 |
273781 |
|
T27 |
101 |
|
T30 |
109082 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1749897 |
1 |
|
|
T25 |
117063 |
|
T27 |
52 |
|
T30 |
49426 |
| auto[1] |
auto[0] |
auto[1] |
257651 |
1 |
|
|
T25 |
17437 |
|
T27 |
2 |
|
T30 |
7071 |
| auto[1] |
auto[1] |
auto[0] |
1727577 |
1 |
|
|
T25 |
120885 |
|
T27 |
45 |
|
T30 |
46136 |
| auto[1] |
auto[1] |
auto[1] |
254132 |
1 |
|
|
T25 |
18396 |
|
T27 |
2 |
|
T30 |
6449 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6130995 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
4007973 |
1 |
|
|
T25 |
275931 |
|
T27 |
106 |
|
T30 |
114128 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9625867 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
513101 |
1 |
|
|
T25 |
37045 |
|
T27 |
4 |
|
T30 |
14363 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6143609 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3995359 |
1 |
|
|
T25 |
281187 |
|
T27 |
121 |
|
T30 |
114627 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1744272 |
1 |
|
|
T25 |
123917 |
|
T27 |
45 |
|
T30 |
50139 |
| auto[1] |
auto[0] |
auto[1] |
257183 |
1 |
|
|
T25 |
18835 |
|
T27 |
1 |
|
T30 |
7277 |
| auto[1] |
auto[1] |
auto[0] |
1737986 |
1 |
|
|
T25 |
120225 |
|
T27 |
72 |
|
T30 |
50125 |
| auto[1] |
auto[1] |
auto[1] |
255918 |
1 |
|
|
T25 |
18210 |
|
T27 |
3 |
|
T30 |
7086 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6163845 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3975123 |
1 |
|
|
T25 |
274243 |
|
T27 |
113 |
|
T30 |
106849 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9629045 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
509923 |
1 |
|
|
T25 |
37230 |
|
T27 |
5 |
|
T30 |
12688 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6167353 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3971615 |
1 |
|
|
T25 |
280770 |
|
T27 |
94 |
|
T30 |
103614 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1738092 |
1 |
|
|
T25 |
125810 |
|
T27 |
36 |
|
T30 |
46651 |
| auto[1] |
auto[0] |
auto[1] |
256608 |
1 |
|
|
T25 |
19333 |
|
T27 |
2 |
|
T30 |
6618 |
| auto[1] |
auto[1] |
auto[0] |
1723600 |
1 |
|
|
T25 |
117730 |
|
T27 |
53 |
|
T30 |
44275 |
| auto[1] |
auto[1] |
auto[1] |
253315 |
1 |
|
|
T25 |
17897 |
|
T27 |
3 |
|
T30 |
6070 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6136684 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
4002284 |
1 |
|
|
T25 |
276289 |
|
T27 |
145 |
|
T30 |
111646 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9624521 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
514447 |
1 |
|
|
T25 |
36859 |
|
T27 |
2 |
|
T30 |
13920 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6146467 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3992501 |
1 |
|
|
T25 |
279376 |
|
T27 |
79 |
|
T30 |
110751 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1742181 |
1 |
|
|
T25 |
123528 |
|
T27 |
24 |
|
T30 |
49510 |
| auto[1] |
auto[0] |
auto[1] |
257154 |
1 |
|
|
T25 |
19045 |
|
T30 |
7266 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1735873 |
1 |
|
|
T25 |
118989 |
|
T27 |
53 |
|
T30 |
47321 |
| auto[1] |
auto[1] |
auto[1] |
257293 |
1 |
|
|
T25 |
17814 |
|
T27 |
2 |
|
T30 |
6654 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |