Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6136829 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
4002139 |
1 |
|
|
T25 |
283743 |
|
T27 |
111 |
|
T30 |
109238 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8438752 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
1700216 |
1 |
|
|
T25 |
110355 |
|
T27 |
41 |
|
T30 |
40999 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6151878 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3987090 |
1 |
|
|
T25 |
283091 |
|
T27 |
99 |
|
T30 |
110233 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1129890 |
1 |
|
|
T25 |
86577 |
|
T27 |
27 |
|
T30 |
35719 |
| auto[1] |
auto[0] |
auto[1] |
842690 |
1 |
|
|
T25 |
54063 |
|
T27 |
19 |
|
T30 |
20387 |
| auto[1] |
auto[1] |
auto[0] |
1156984 |
1 |
|
|
T25 |
86159 |
|
T27 |
31 |
|
T30 |
33515 |
| auto[1] |
auto[1] |
auto[1] |
857526 |
1 |
|
|
T25 |
56292 |
|
T27 |
22 |
|
T30 |
20612 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |