dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6167187 1 T22 52136 T23 332 T24 374
auto[1] 3971781 1 T25 281214 T27 74 T30 109236


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9626661 1 T22 52136 T23 332 T24 374
auto[1] 512307 1 T25 36853 T27 6 T30 13839


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 6154618 1 T22 52136 T23 332 T24 374
auto[1] 3984350 1 T25 278929 T27 91 T30 110941


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 1739574 1 T25 119010 T27 40 T30 48949
auto[1] auto[0] auto[1] 256975 1 T25 17881 T27 2 T30 7091
auto[1] auto[1] auto[0] 1732469 1 T25 123066 T27 45 T30 48153
auto[1] auto[1] auto[1] 255332 1 T25 18972 T27 4 T30 6748


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%