Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6172348 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
3966620 |
1 |
|
|
T25 |
285807 |
|
T27 |
86 |
|
T30 |
116019 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9623725 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
515243 |
1 |
|
|
T25 |
35932 |
|
T27 |
6 |
|
T30 |
14039 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6133979 |
1 |
|
|
T22 |
52136 |
|
T23 |
332 |
|
T24 |
374 |
| auto[1] |
4004989 |
1 |
|
|
T25 |
273443 |
|
T27 |
119 |
|
T30 |
111937 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1757632 |
1 |
|
|
T25 |
119111 |
|
T27 |
64 |
|
T30 |
46114 |
| auto[1] |
auto[0] |
auto[1] |
259231 |
1 |
|
|
T25 |
18024 |
|
T27 |
3 |
|
T30 |
6434 |
| auto[1] |
auto[1] |
auto[0] |
1732114 |
1 |
|
|
T25 |
118400 |
|
T27 |
49 |
|
T30 |
51784 |
| auto[1] |
auto[1] |
auto[1] |
256012 |
1 |
|
|
T25 |
17908 |
|
T27 |
3 |
|
T30 |
7605 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |