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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 934
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T760 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2858630208 May 14 01:14:05 PM PDT 24 May 14 01:14:12 PM PDT 24 588759864 ps
T761 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3016953266 May 14 01:14:13 PM PDT 24 May 14 01:14:17 PM PDT 24 67008916 ps
T762 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2162725995 May 14 01:14:10 PM PDT 24 May 14 01:14:15 PM PDT 24 35553587 ps
T763 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2746038047 May 14 01:13:54 PM PDT 24 May 14 01:13:58 PM PDT 24 134043749 ps
T764 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1882225644 May 14 01:14:08 PM PDT 24 May 14 01:14:13 PM PDT 24 49270497 ps
T765 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2733093126 May 14 01:14:08 PM PDT 24 May 14 01:14:12 PM PDT 24 15821185 ps
T766 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1140296978 May 14 01:14:17 PM PDT 24 May 14 01:14:20 PM PDT 24 60125677 ps
T767 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3544458386 May 14 01:14:13 PM PDT 24 May 14 01:14:17 PM PDT 24 52958293 ps
T768 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4185767305 May 14 01:14:05 PM PDT 24 May 14 01:14:10 PM PDT 24 20545593 ps
T769 /workspace/coverage/cover_reg_top/27.gpio_intr_test.3016545633 May 14 01:14:08 PM PDT 24 May 14 01:14:13 PM PDT 24 18507031 ps
T770 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2313224636 May 14 01:13:59 PM PDT 24 May 14 01:14:04 PM PDT 24 34772844 ps
T771 /workspace/coverage/cover_reg_top/7.gpio_intr_test.411831026 May 14 01:13:56 PM PDT 24 May 14 01:14:00 PM PDT 24 11290829 ps
T92 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1168571918 May 14 01:14:08 PM PDT 24 May 14 01:14:12 PM PDT 24 53161555 ps
T93 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.742595804 May 14 01:14:01 PM PDT 24 May 14 01:14:07 PM PDT 24 17193520 ps
T94 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3797511435 May 14 01:14:02 PM PDT 24 May 14 01:14:08 PM PDT 24 48307524 ps
T772 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3437260338 May 14 01:14:12 PM PDT 24 May 14 01:14:16 PM PDT 24 19207759 ps
T773 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3309376327 May 14 01:14:13 PM PDT 24 May 14 01:14:17 PM PDT 24 218915031 ps
T774 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3056145316 May 14 01:13:57 PM PDT 24 May 14 01:14:01 PM PDT 24 21115760 ps
T775 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2874695233 May 14 01:14:07 PM PDT 24 May 14 01:14:11 PM PDT 24 38590321 ps
T776 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.783082304 May 14 01:14:02 PM PDT 24 May 14 01:14:09 PM PDT 24 694674412 ps
T777 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.920546722 May 14 01:14:06 PM PDT 24 May 14 01:14:11 PM PDT 24 56555258 ps
T778 /workspace/coverage/cover_reg_top/12.gpio_intr_test.2415199561 May 14 01:14:01 PM PDT 24 May 14 01:14:05 PM PDT 24 15870790 ps
T779 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.725417572 May 14 01:14:02 PM PDT 24 May 14 01:14:09 PM PDT 24 123866215 ps
T780 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.340606511 May 14 01:13:55 PM PDT 24 May 14 01:13:58 PM PDT 24 91850565 ps
T106 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1796728920 May 14 01:14:10 PM PDT 24 May 14 01:14:15 PM PDT 24 460610869 ps
T85 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2410776474 May 14 01:13:56 PM PDT 24 May 14 01:13:59 PM PDT 24 12044787 ps
T781 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3309501336 May 14 01:14:01 PM PDT 24 May 14 01:14:06 PM PDT 24 16251526 ps
T782 /workspace/coverage/cover_reg_top/24.gpio_intr_test.627315974 May 14 01:14:08 PM PDT 24 May 14 01:14:12 PM PDT 24 20502928 ps
T43 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3619902927 May 14 01:13:48 PM PDT 24 May 14 01:13:51 PM PDT 24 740774892 ps
T783 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2254868102 May 14 01:14:22 PM PDT 24 May 14 01:14:24 PM PDT 24 11059133 ps
T784 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2423504345 May 14 01:14:12 PM PDT 24 May 14 01:14:17 PM PDT 24 111816462 ps
T80 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3547968893 May 14 01:14:03 PM PDT 24 May 14 01:14:08 PM PDT 24 134476122 ps
T785 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2622511038 May 14 01:14:06 PM PDT 24 May 14 01:14:11 PM PDT 24 122801741 ps
T786 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1807895716 May 14 01:14:05 PM PDT 24 May 14 01:14:10 PM PDT 24 46122822 ps
T787 /workspace/coverage/cover_reg_top/21.gpio_intr_test.845587396 May 14 01:14:09 PM PDT 24 May 14 01:14:14 PM PDT 24 44881840 ps
T788 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1662490539 May 14 01:13:58 PM PDT 24 May 14 01:14:03 PM PDT 24 12615555 ps
T789 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1940365715 May 14 01:14:07 PM PDT 24 May 14 01:14:12 PM PDT 24 233926456 ps
T86 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2365798018 May 14 01:13:55 PM PDT 24 May 14 01:13:59 PM PDT 24 112610759 ps
T790 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2563719301 May 14 01:14:18 PM PDT 24 May 14 01:14:22 PM PDT 24 49343256 ps
T791 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2375033266 May 14 01:14:08 PM PDT 24 May 14 01:14:15 PM PDT 24 133215765 ps
T792 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4151255035 May 14 01:14:09 PM PDT 24 May 14 01:14:14 PM PDT 24 42021885 ps
T793 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1981894259 May 14 01:14:16 PM PDT 24 May 14 01:14:19 PM PDT 24 18381064 ps
T794 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1581555199 May 14 01:14:09 PM PDT 24 May 14 01:14:14 PM PDT 24 47969143 ps
T795 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2948863123 May 14 01:14:01 PM PDT 24 May 14 01:14:06 PM PDT 24 19789996 ps
T796 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2029410057 May 14 01:13:56 PM PDT 24 May 14 01:13:58 PM PDT 24 53900512 ps
T797 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3334194845 May 14 01:13:59 PM PDT 24 May 14 01:14:04 PM PDT 24 48845021 ps
T798 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1003782543 May 14 01:14:02 PM PDT 24 May 14 01:14:08 PM PDT 24 42587887 ps
T799 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3526373052 May 14 01:14:16 PM PDT 24 May 14 01:14:19 PM PDT 24 24188928 ps
T800 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.615338386 May 14 01:13:56 PM PDT 24 May 14 01:14:01 PM PDT 24 321572195 ps
T801 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4162388941 May 14 01:14:01 PM PDT 24 May 14 01:14:07 PM PDT 24 105814146 ps
T802 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1832088363 May 14 01:14:09 PM PDT 24 May 14 01:14:13 PM PDT 24 33349902 ps
T803 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.603214372 May 14 01:13:56 PM PDT 24 May 14 01:14:02 PM PDT 24 202038066 ps
T804 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3353023954 May 14 01:14:21 PM PDT 24 May 14 01:14:24 PM PDT 24 27883902 ps
T805 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.706426661 May 14 01:14:04 PM PDT 24 May 14 01:14:10 PM PDT 24 37425119 ps
T806 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1786690035 May 14 01:13:57 PM PDT 24 May 14 01:14:02 PM PDT 24 70135635 ps
T807 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2568583391 May 14 01:14:09 PM PDT 24 May 14 01:14:13 PM PDT 24 41034229 ps
T808 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.96192218 May 14 01:14:01 PM PDT 24 May 14 01:14:09 PM PDT 24 661092623 ps
T809 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.125169870 May 14 01:13:59 PM PDT 24 May 14 01:14:04 PM PDT 24 468098115 ps
T810 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1522090932 May 14 01:13:57 PM PDT 24 May 14 01:14:02 PM PDT 24 42929106 ps
T811 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.697861512 May 14 01:14:01 PM PDT 24 May 14 01:14:06 PM PDT 24 37412405 ps
T812 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3238184800 May 14 01:13:57 PM PDT 24 May 14 01:14:01 PM PDT 24 46249934 ps
T813 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2653278056 May 14 01:14:06 PM PDT 24 May 14 01:14:12 PM PDT 24 49173214 ps
T814 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1446179227 May 14 01:14:09 PM PDT 24 May 14 01:14:13 PM PDT 24 117250766 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4138425222 May 14 01:14:06 PM PDT 24 May 14 01:14:10 PM PDT 24 93379987 ps
T816 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1006553878 May 14 01:14:09 PM PDT 24 May 14 01:14:14 PM PDT 24 16722859 ps
T817 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2848048164 May 14 01:13:58 PM PDT 24 May 14 01:14:02 PM PDT 24 13202324 ps
T81 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2424827714 May 14 01:14:01 PM PDT 24 May 14 01:14:06 PM PDT 24 22527251 ps
T818 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1148716588 May 14 01:14:01 PM PDT 24 May 14 01:14:06 PM PDT 24 93306436 ps
T819 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3790075084 May 14 01:14:01 PM PDT 24 May 14 01:14:06 PM PDT 24 45313777 ps
T820 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.517795409 May 14 01:13:56 PM PDT 24 May 14 01:13:59 PM PDT 24 141515058 ps
T821 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3800492691 May 14 01:13:53 PM PDT 24 May 14 01:13:56 PM PDT 24 54792853 ps
T822 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3917307394 May 14 01:14:18 PM PDT 24 May 14 01:14:21 PM PDT 24 11135550 ps
T823 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3131482562 May 14 01:14:09 PM PDT 24 May 14 01:14:14 PM PDT 24 37948859 ps
T824 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3326744823 May 14 01:14:07 PM PDT 24 May 14 01:14:13 PM PDT 24 89253317 ps
T825 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.461033654 May 14 01:13:57 PM PDT 24 May 14 01:14:06 PM PDT 24 652611191 ps
T826 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.943578564 May 14 01:14:09 PM PDT 24 May 14 01:14:14 PM PDT 24 84895152 ps
T827 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3448639531 May 14 01:14:10 PM PDT 24 May 14 01:14:15 PM PDT 24 13746498 ps
T828 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2549540520 May 14 01:14:10 PM PDT 24 May 14 01:14:15 PM PDT 24 32676626 ps
T829 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.856108366 May 14 01:13:53 PM PDT 24 May 14 01:13:55 PM PDT 24 61161180 ps
T830 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.465060748 May 14 01:13:59 PM PDT 24 May 14 01:14:04 PM PDT 24 127348720 ps
T831 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4173452899 May 14 01:14:04 PM PDT 24 May 14 01:14:09 PM PDT 24 42545062 ps
T832 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3639432204 May 14 01:14:02 PM PDT 24 May 14 01:14:07 PM PDT 24 26963034 ps
T833 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2743801800 May 14 01:13:57 PM PDT 24 May 14 01:14:01 PM PDT 24 51448235 ps
T834 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.4149857436 May 14 01:14:12 PM PDT 24 May 14 01:14:17 PM PDT 24 102897515 ps
T835 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2286182708 May 14 01:14:18 PM PDT 24 May 14 01:14:23 PM PDT 24 193189231 ps
T836 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3023268948 May 14 01:14:26 PM PDT 24 May 14 01:14:29 PM PDT 24 35569349 ps
T837 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3913320313 May 14 01:14:25 PM PDT 24 May 14 01:14:28 PM PDT 24 312725650 ps
T838 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4161279507 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 254111001 ps
T839 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1904358614 May 14 01:14:25 PM PDT 24 May 14 01:14:28 PM PDT 24 141149787 ps
T840 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.541619258 May 14 01:14:29 PM PDT 24 May 14 01:14:32 PM PDT 24 698203207 ps
T841 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.925619960 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 75904515 ps
T842 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3331617806 May 14 01:14:20 PM PDT 24 May 14 01:14:24 PM PDT 24 369483849 ps
T843 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.58829755 May 14 01:14:20 PM PDT 24 May 14 01:14:24 PM PDT 24 184043318 ps
T844 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4182400874 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 116416155 ps
T845 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3185830708 May 14 01:14:19 PM PDT 24 May 14 01:14:24 PM PDT 24 70239872 ps
T846 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2870421896 May 14 01:14:27 PM PDT 24 May 14 01:14:30 PM PDT 24 66334330 ps
T847 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1566350451 May 14 01:14:19 PM PDT 24 May 14 01:14:23 PM PDT 24 57454971 ps
T848 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2551929623 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 49657192 ps
T849 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3447388860 May 14 01:14:27 PM PDT 24 May 14 01:14:32 PM PDT 24 92330243 ps
T850 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3896945110 May 14 01:14:21 PM PDT 24 May 14 01:14:25 PM PDT 24 184583505 ps
T851 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2389387981 May 14 01:14:16 PM PDT 24 May 14 01:14:20 PM PDT 24 318123491 ps
T852 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1405914420 May 14 01:14:20 PM PDT 24 May 14 01:14:24 PM PDT 24 148276254 ps
T853 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.507251152 May 14 01:14:18 PM PDT 24 May 14 01:14:22 PM PDT 24 108980524 ps
T854 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2799485057 May 14 01:14:26 PM PDT 24 May 14 01:14:29 PM PDT 24 46741583 ps
T855 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1886705850 May 14 01:14:34 PM PDT 24 May 14 01:14:37 PM PDT 24 322734745 ps
T856 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3934549887 May 14 01:14:24 PM PDT 24 May 14 01:14:26 PM PDT 24 1238277398 ps
T857 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3611798906 May 14 01:14:33 PM PDT 24 May 14 01:14:36 PM PDT 24 52096049 ps
T858 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.221466238 May 14 01:14:28 PM PDT 24 May 14 01:14:32 PM PDT 24 31238500 ps
T859 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3126337890 May 14 01:14:22 PM PDT 24 May 14 01:14:25 PM PDT 24 188944393 ps
T860 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3951789091 May 14 01:14:26 PM PDT 24 May 14 01:14:30 PM PDT 24 682749974 ps
T861 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2880855353 May 14 01:14:16 PM PDT 24 May 14 01:14:20 PM PDT 24 77465185 ps
T862 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3197921430 May 14 01:14:17 PM PDT 24 May 14 01:14:20 PM PDT 24 210843083 ps
T863 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3053166677 May 14 01:14:26 PM PDT 24 May 14 01:14:28 PM PDT 24 33459830 ps
T864 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2724322184 May 14 01:14:26 PM PDT 24 May 14 01:14:30 PM PDT 24 101630393 ps
T865 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2470081306 May 14 01:14:29 PM PDT 24 May 14 01:14:33 PM PDT 24 279034609 ps
T866 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.906015658 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 75927958 ps
T867 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2909174748 May 14 01:14:26 PM PDT 24 May 14 01:14:29 PM PDT 24 85723673 ps
T868 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2640462697 May 14 01:14:28 PM PDT 24 May 14 01:14:32 PM PDT 24 35886196 ps
T869 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.439218465 May 14 01:14:17 PM PDT 24 May 14 01:14:20 PM PDT 24 93229480 ps
T870 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1446251532 May 14 01:14:19 PM PDT 24 May 14 01:14:23 PM PDT 24 207725311 ps
T871 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.911747028 May 14 01:14:18 PM PDT 24 May 14 01:14:23 PM PDT 24 59576589 ps
T872 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1726692873 May 14 01:14:28 PM PDT 24 May 14 01:14:32 PM PDT 24 424438413 ps
T873 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1279783862 May 14 01:14:23 PM PDT 24 May 14 01:14:26 PM PDT 24 60437419 ps
T874 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1258822221 May 14 01:14:21 PM PDT 24 May 14 01:14:24 PM PDT 24 48064718 ps
T875 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1432618058 May 14 01:14:29 PM PDT 24 May 14 01:14:32 PM PDT 24 245349562 ps
T876 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2387696723 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 153152108 ps
T877 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3349163598 May 14 01:14:26 PM PDT 24 May 14 01:14:29 PM PDT 24 36043907 ps
T878 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1908412166 May 14 01:14:18 PM PDT 24 May 14 01:14:22 PM PDT 24 383368478 ps
T879 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1806764108 May 14 01:14:17 PM PDT 24 May 14 01:14:21 PM PDT 24 69846735 ps
T880 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1346452524 May 14 01:14:29 PM PDT 24 May 14 01:14:33 PM PDT 24 1154548718 ps
T881 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.639185275 May 14 01:14:18 PM PDT 24 May 14 01:14:21 PM PDT 24 122170226 ps
T882 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1932289505 May 14 01:14:26 PM PDT 24 May 14 01:14:33 PM PDT 24 112258566 ps
T883 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.451782852 May 14 01:14:25 PM PDT 24 May 14 01:14:28 PM PDT 24 71993238 ps
T884 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1081590776 May 14 01:14:25 PM PDT 24 May 14 01:14:28 PM PDT 24 765741452 ps
T885 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.247210055 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 442651318 ps
T886 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2319570639 May 14 01:14:25 PM PDT 24 May 14 01:14:28 PM PDT 24 135897664 ps
T887 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2113137321 May 14 01:14:18 PM PDT 24 May 14 01:14:22 PM PDT 24 234752138 ps
T888 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.66030387 May 14 01:14:17 PM PDT 24 May 14 01:14:20 PM PDT 24 75816823 ps
T889 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2835147142 May 14 01:14:17 PM PDT 24 May 14 01:14:20 PM PDT 24 70190657 ps
T890 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4139443616 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 247925627 ps
T891 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3286426870 May 14 01:14:22 PM PDT 24 May 14 01:14:25 PM PDT 24 123044246 ps
T892 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.713890989 May 14 01:14:26 PM PDT 24 May 14 01:14:29 PM PDT 24 191697720 ps
T893 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3718676661 May 14 01:14:30 PM PDT 24 May 14 01:14:33 PM PDT 24 38700288 ps
T894 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1795917708 May 14 01:14:18 PM PDT 24 May 14 01:14:21 PM PDT 24 380706480 ps
T895 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1041388582 May 14 01:14:35 PM PDT 24 May 14 01:14:38 PM PDT 24 80415511 ps
T896 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2334122852 May 14 01:14:29 PM PDT 24 May 14 01:14:32 PM PDT 24 28100344 ps
T897 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3739677409 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 167840104 ps
T898 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.446954888 May 14 01:14:28 PM PDT 24 May 14 01:14:32 PM PDT 24 65373777 ps
T899 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.749151698 May 14 01:14:17 PM PDT 24 May 14 01:14:21 PM PDT 24 26247269 ps
T900 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.982345413 May 14 01:14:29 PM PDT 24 May 14 01:14:33 PM PDT 24 197187303 ps
T901 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1515243626 May 14 01:14:24 PM PDT 24 May 14 01:14:27 PM PDT 24 317295649 ps
T902 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2062606825 May 14 01:14:26 PM PDT 24 May 14 01:14:30 PM PDT 24 38350949 ps
T903 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.885560035 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 146166487 ps
T904 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2503014901 May 14 01:14:32 PM PDT 24 May 14 01:14:34 PM PDT 24 32517826 ps
T905 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2704437396 May 14 01:14:28 PM PDT 24 May 14 01:14:32 PM PDT 24 215474149 ps
T906 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2296076694 May 14 01:14:17 PM PDT 24 May 14 01:14:21 PM PDT 24 93205204 ps
T907 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1668615648 May 14 01:14:18 PM PDT 24 May 14 01:14:22 PM PDT 24 77338067 ps
T908 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.907194801 May 14 01:14:33 PM PDT 24 May 14 01:14:36 PM PDT 24 51422898 ps
T909 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2691537087 May 14 01:14:26 PM PDT 24 May 14 01:14:29 PM PDT 24 67942291 ps
T910 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2250319082 May 14 01:14:30 PM PDT 24 May 14 01:14:33 PM PDT 24 163498606 ps
T911 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3347594667 May 14 01:14:23 PM PDT 24 May 14 01:14:26 PM PDT 24 40824535 ps
T912 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3415342121 May 14 01:14:26 PM PDT 24 May 14 01:14:29 PM PDT 24 149825283 ps
T913 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.460561179 May 14 01:14:24 PM PDT 24 May 14 01:14:26 PM PDT 24 46024156 ps
T914 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4235957247 May 14 01:14:18 PM PDT 24 May 14 01:14:22 PM PDT 24 124201468 ps
T915 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3025037183 May 14 01:14:19 PM PDT 24 May 14 01:14:23 PM PDT 24 54245559 ps
T916 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2346236661 May 14 01:14:26 PM PDT 24 May 14 01:14:29 PM PDT 24 213448629 ps
T917 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.492857958 May 14 01:14:17 PM PDT 24 May 14 01:14:22 PM PDT 24 99808755 ps
T918 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3586246318 May 14 01:14:34 PM PDT 24 May 14 01:14:37 PM PDT 24 363015254 ps
T919 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2263621198 May 14 01:14:27 PM PDT 24 May 14 01:14:30 PM PDT 24 64451778 ps
T920 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.683450472 May 14 01:14:30 PM PDT 24 May 14 01:14:33 PM PDT 24 52760219 ps
T921 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1020526511 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 154320538 ps
T922 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2490343095 May 14 01:14:25 PM PDT 24 May 14 01:14:27 PM PDT 24 65729093 ps
T923 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3212912452 May 14 01:14:18 PM PDT 24 May 14 01:14:22 PM PDT 24 72930594 ps
T924 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3713609658 May 14 01:14:21 PM PDT 24 May 14 01:14:24 PM PDT 24 257208619 ps
T925 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4048352708 May 14 01:14:18 PM PDT 24 May 14 01:14:22 PM PDT 24 73314899 ps
T926 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.284026194 May 14 01:14:19 PM PDT 24 May 14 01:14:23 PM PDT 24 305465624 ps
T927 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2252910209 May 14 01:14:27 PM PDT 24 May 14 01:14:30 PM PDT 24 235425995 ps
T928 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1622744786 May 14 01:14:25 PM PDT 24 May 14 01:14:27 PM PDT 24 62189072 ps
T929 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.686734624 May 14 01:14:25 PM PDT 24 May 14 01:14:28 PM PDT 24 61318987 ps
T930 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2184216584 May 14 01:14:17 PM PDT 24 May 14 01:14:21 PM PDT 24 199801601 ps
T931 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2337683570 May 14 01:14:19 PM PDT 24 May 14 01:14:23 PM PDT 24 33508919 ps
T932 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.379169919 May 14 01:14:27 PM PDT 24 May 14 01:14:31 PM PDT 24 32284119 ps
T933 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1029672839 May 14 01:14:26 PM PDT 24 May 14 01:14:30 PM PDT 24 93509407 ps
T934 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2179041093 May 14 01:14:18 PM PDT 24 May 14 01:14:21 PM PDT 24 63158282 ps

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.779364535
Short name T25
Test name
Test status
Simulation time 52059147056 ps
CPU time 1466.92 seconds
Started May 14 01:15:45 PM PDT 24
Finished May 14 01:40:18 PM PDT 24
Peak memory 198320 kb
Host smart-a642c76a-a5b9-4ede-b18c-515e338cf444
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=779364535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.779364535
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.3677796179
Short name T107
Test name
Test status
Simulation time 48676214 ps
CPU time 1.97 seconds
Started May 14 01:15:13 PM PDT 24
Finished May 14 01:15:18 PM PDT 24
Peak memory 198084 kb
Host smart-dcb47645-203a-4a36-bcfb-de74b5100330
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677796179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.3677796179
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.63511071
Short name T22
Test name
Test status
Simulation time 2008707998 ps
CPU time 26.13 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 197956 kb
Host smart-0141aa0b-be61-483d-b61a-7f7397676a7c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63511071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stress
.63511071
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3188870592
Short name T69
Test name
Test status
Simulation time 39982610 ps
CPU time 0.63 seconds
Started May 14 01:13:50 PM PDT 24
Finished May 14 01:13:52 PM PDT 24
Peak memory 194864 kb
Host smart-62faa673-6fa5-42d0-95c6-7d257d23e155
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188870592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3188870592
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1839592178
Short name T35
Test name
Test status
Simulation time 149408535 ps
CPU time 1.12 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 197964 kb
Host smart-61f72960-5426-4c53-90cc-150a8c817239
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839592178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1839592178
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3136922855
Short name T1
Test name
Test status
Simulation time 253590591 ps
CPU time 1.8 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:20 PM PDT 24
Peak memory 197948 kb
Host smart-e4062682-60b4-4b71-b427-5fbfe67297a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136922855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3136922855
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2488326821
Short name T209
Test name
Test status
Simulation time 34133936 ps
CPU time 0.59 seconds
Started May 14 01:15:03 PM PDT 24
Finished May 14 01:15:06 PM PDT 24
Peak memory 194112 kb
Host smart-fd3f20a0-2884-4142-85c4-7b2191796dfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488326821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2488326821
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.4194798565
Short name T48
Test name
Test status
Simulation time 101019028 ps
CPU time 0.99 seconds
Started May 14 01:14:44 PM PDT 24
Finished May 14 01:14:47 PM PDT 24
Peak memory 214984 kb
Host smart-ef4f30eb-abf5-4beb-bfda-0077e656ac3c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194798565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.4194798565
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.3161871518
Short name T41
Test name
Test status
Simulation time 288175482 ps
CPU time 1.52 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:13:59 PM PDT 24
Peak memory 197924 kb
Host smart-9e47f47c-67c6-4a8a-af00-1ef555362a58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161871518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.3161871518
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3653672005
Short name T89
Test name
Test status
Simulation time 67350173 ps
CPU time 0.71 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:02 PM PDT 24
Peak memory 194540 kb
Host smart-79a07682-ba9a-423c-a902-0acfd206310f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653672005 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3653672005
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3210687085
Short name T46
Test name
Test status
Simulation time 281772286 ps
CPU time 1.15 seconds
Started May 14 01:14:13 PM PDT 24
Finished May 14 01:14:18 PM PDT 24
Peak memory 197972 kb
Host smart-43438588-e9bd-47cb-ab89-68355e6b640c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210687085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3210687085
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3800492691
Short name T821
Test name
Test status
Simulation time 54792853 ps
CPU time 0.8 seconds
Started May 14 01:13:53 PM PDT 24
Finished May 14 01:13:56 PM PDT 24
Peak memory 195984 kb
Host smart-6f583fbb-984d-4673-9a64-89cac01372de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800492691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3800492691
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.96192218
Short name T808
Test name
Test status
Simulation time 661092623 ps
CPU time 3.47 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:09 PM PDT 24
Peak memory 197804 kb
Host smart-4fc80d8d-1630-4925-864e-5ef88cb4cee4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96192218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.96192218
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.3255860106
Short name T105
Test name
Test status
Simulation time 21534867 ps
CPU time 0.61 seconds
Started May 14 01:14:07 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 194960 kb
Host smart-8410a586-2ae9-4d2f-ae74-802f3dc1e895
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255860106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.3255860106
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3931290827
Short name T737
Test name
Test status
Simulation time 37871114 ps
CPU time 1.03 seconds
Started May 14 01:13:51 PM PDT 24
Finished May 14 01:13:54 PM PDT 24
Peak memory 197880 kb
Host smart-20e969a8-57e6-4743-b1c7-d6333d2aa1a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931290827 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3931290827
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3736075628
Short name T731
Test name
Test status
Simulation time 20351407 ps
CPU time 0.62 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 193688 kb
Host smart-4557dfda-5266-4316-a1fc-8367737c37ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736075628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3736075628
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.856108366
Short name T829
Test name
Test status
Simulation time 61161180 ps
CPU time 0.75 seconds
Started May 14 01:13:53 PM PDT 24
Finished May 14 01:13:55 PM PDT 24
Peak memory 196172 kb
Host smart-34736528-8a1a-42d9-916a-fc813b08ffea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856108366 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.856108366
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1056403392
Short name T729
Test name
Test status
Simulation time 374860296 ps
CPU time 1.46 seconds
Started May 14 01:14:06 PM PDT 24
Finished May 14 01:14:11 PM PDT 24
Peak memory 197928 kb
Host smart-a4c366e4-0596-42c1-a6b0-6b140ce09a4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056403392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1056403392
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.3619902927
Short name T43
Test name
Test status
Simulation time 740774892 ps
CPU time 0.95 seconds
Started May 14 01:13:48 PM PDT 24
Finished May 14 01:13:51 PM PDT 24
Peak memory 196940 kb
Host smart-653a149d-78e2-4155-b986-cfe50ecfbe08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619902927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.3619902927
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2841172453
Short name T71
Test name
Test status
Simulation time 26138367 ps
CPU time 0.64 seconds
Started May 14 01:14:02 PM PDT 24
Finished May 14 01:14:07 PM PDT 24
Peak memory 194168 kb
Host smart-196b757b-488a-4367-a128-3f2720998885
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841172453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2841172453
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.461033654
Short name T825
Test name
Test status
Simulation time 652611191 ps
CPU time 2.93 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 196964 kb
Host smart-002e7154-0143-4985-9f4d-7c6c1287af23
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461033654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.461033654
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2358943726
Short name T738
Test name
Test status
Simulation time 46959720 ps
CPU time 0.62 seconds
Started May 14 01:14:00 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 194400 kb
Host smart-5491946d-0373-40ce-8d54-cf0391652060
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358943726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2358943726
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1522090932
Short name T810
Test name
Test status
Simulation time 42929106 ps
CPU time 1.08 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:02 PM PDT 24
Peak memory 197952 kb
Host smart-794b09f1-d77a-467a-9dbf-2f17eea2ba8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522090932 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1522090932
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.920546722
Short name T777
Test name
Test status
Simulation time 56555258 ps
CPU time 0.62 seconds
Started May 14 01:14:06 PM PDT 24
Finished May 14 01:14:11 PM PDT 24
Peak memory 194620 kb
Host smart-3835996a-4dfe-4c82-9d82-0bdade3c377e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920546722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.920546722
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1308446851
Short name T740
Test name
Test status
Simulation time 22154458 ps
CPU time 0.6 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:13:58 PM PDT 24
Peak memory 194240 kb
Host smart-cb4e6a3e-46cc-4466-bacc-d1e6f5785ab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308446851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1308446851
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1942391444
Short name T746
Test name
Test status
Simulation time 187689940 ps
CPU time 2.39 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:05 PM PDT 24
Peak memory 197956 kb
Host smart-4f7fad7d-9861-4f13-91ae-615d791380e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942391444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1942391444
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2622511038
Short name T785
Test name
Test status
Simulation time 122801741 ps
CPU time 1.11 seconds
Started May 14 01:14:06 PM PDT 24
Finished May 14 01:14:11 PM PDT 24
Peak memory 197948 kb
Host smart-eab582b9-c6fa-45b7-b1fa-02603ce4debc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622511038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2622511038
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2162725995
Short name T762
Test name
Test status
Simulation time 35553587 ps
CPU time 1.18 seconds
Started May 14 01:14:10 PM PDT 24
Finished May 14 01:14:15 PM PDT 24
Peak memory 198028 kb
Host smart-cf999200-c541-497b-b1ca-1a61de29f1d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162725995 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2162725995
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2424827714
Short name T81
Test name
Test status
Simulation time 22527251 ps
CPU time 0.65 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 195508 kb
Host smart-5f8d8174-907b-42c4-b07f-3b124a990c6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424827714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2424827714
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3431534215
Short name T756
Test name
Test status
Simulation time 19204753 ps
CPU time 0.66 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 193648 kb
Host smart-1227476a-1b30-44af-8446-d7fc3d397790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431534215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3431534215
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1168571918
Short name T92
Test name
Test status
Simulation time 53161555 ps
CPU time 0.75 seconds
Started May 14 01:14:08 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 196360 kb
Host smart-dadf2155-15e5-41cc-a4ca-73e7816b6fa9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168571918 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1168571918
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2948863123
Short name T795
Test name
Test status
Simulation time 19789996 ps
CPU time 1.01 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 197796 kb
Host smart-c4e194b0-4032-415c-82e2-4c3cae487441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948863123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2948863123
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.4162388941
Short name T801
Test name
Test status
Simulation time 105814146 ps
CPU time 1.54 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:07 PM PDT 24
Peak memory 197964 kb
Host smart-0b8d5f99-eca3-4691-83ca-34bd522af44f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162388941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.4162388941
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2313224636
Short name T770
Test name
Test status
Simulation time 34772844 ps
CPU time 1.03 seconds
Started May 14 01:13:59 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 197856 kb
Host smart-91399f1a-0d0d-47d8-b489-482bbee634ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313224636 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2313224636
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3437260338
Short name T772
Test name
Test status
Simulation time 19207759 ps
CPU time 0.56 seconds
Started May 14 01:14:12 PM PDT 24
Finished May 14 01:14:16 PM PDT 24
Peak memory 194540 kb
Host smart-9e87bade-277e-410b-a738-2d411bc60d3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437260338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3437260338
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.26145272
Short name T735
Test name
Test status
Simulation time 15826080 ps
CPU time 0.65 seconds
Started May 14 01:14:05 PM PDT 24
Finished May 14 01:14:10 PM PDT 24
Peak memory 194276 kb
Host smart-25bd00a3-6d05-4b09-801a-eca22489b219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26145272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.26145272
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.742595804
Short name T93
Test name
Test status
Simulation time 17193520 ps
CPU time 0.81 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:07 PM PDT 24
Peak memory 196512 kb
Host smart-3608a18d-a077-4d5d-af31-7f298f5e0b78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742595804 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.742595804
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3370248391
Short name T722
Test name
Test status
Simulation time 106438245 ps
CPU time 1.98 seconds
Started May 14 01:14:04 PM PDT 24
Finished May 14 01:14:11 PM PDT 24
Peak memory 197908 kb
Host smart-fc29dc64-5a95-4fd4-8823-7457ddeca2be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370248391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3370248391
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3791191138
Short name T45
Test name
Test status
Simulation time 85939800 ps
CPU time 1.24 seconds
Started May 14 01:13:59 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 197928 kb
Host smart-308d7aaa-94af-43db-b9c0-ff55054b3ba0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791191138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3791191138
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4034027353
Short name T734
Test name
Test status
Simulation time 27870098 ps
CPU time 0.81 seconds
Started May 14 01:14:12 PM PDT 24
Finished May 14 01:14:17 PM PDT 24
Peak memory 197912 kb
Host smart-197d3ebe-95f8-45c8-a85a-29389b2ba679
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034027353 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.4034027353
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3304321378
Short name T68
Test name
Test status
Simulation time 21617051 ps
CPU time 0.63 seconds
Started May 14 01:14:10 PM PDT 24
Finished May 14 01:14:15 PM PDT 24
Peak memory 195424 kb
Host smart-2e7ac13e-291d-4baa-ada9-f7eac26d6b78
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304321378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3304321378
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2415199561
Short name T778
Test name
Test status
Simulation time 15870790 ps
CPU time 0.6 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:05 PM PDT 24
Peak memory 193544 kb
Host smart-d8213576-e8ac-4968-bb9d-96577cc38570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415199561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2415199561
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3797511435
Short name T94
Test name
Test status
Simulation time 48307524 ps
CPU time 0.64 seconds
Started May 14 01:14:02 PM PDT 24
Finished May 14 01:14:08 PM PDT 24
Peak memory 194204 kb
Host smart-40660de2-f70e-411c-a195-b09708692569
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797511435 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3797511435
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.706426661
Short name T805
Test name
Test status
Simulation time 37425119 ps
CPU time 1.01 seconds
Started May 14 01:14:04 PM PDT 24
Finished May 14 01:14:10 PM PDT 24
Peak memory 197896 kb
Host smart-ffc78904-70d9-475b-a5e0-5ff528eeef47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706426661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.706426661
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3281055305
Short name T36
Test name
Test status
Simulation time 48308658 ps
CPU time 0.91 seconds
Started May 14 01:14:11 PM PDT 24
Finished May 14 01:14:16 PM PDT 24
Peak memory 196908 kb
Host smart-87b024c1-23e7-48c7-9bb0-7d10349b6deb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281055305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3281055305
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.943578564
Short name T826
Test name
Test status
Simulation time 84895152 ps
CPU time 0.76 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 197832 kb
Host smart-735ef595-9e21-4e5a-9aed-c0dff7bd26cd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943578564 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.943578564
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2556212588
Short name T79
Test name
Test status
Simulation time 16593214 ps
CPU time 0.61 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 194368 kb
Host smart-da3d1fd0-85d6-4661-b151-a03359084fe3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556212588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2556212588
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1062370798
Short name T744
Test name
Test status
Simulation time 14905232 ps
CPU time 0.63 seconds
Started May 14 01:14:05 PM PDT 24
Finished May 14 01:14:10 PM PDT 24
Peak memory 194248 kb
Host smart-49e5e695-630a-4221-a539-ed55e7380be8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062370798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1062370798
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.4221744030
Short name T76
Test name
Test status
Simulation time 46875286 ps
CPU time 0.75 seconds
Started May 14 01:14:00 PM PDT 24
Finished May 14 01:14:05 PM PDT 24
Peak memory 195860 kb
Host smart-fc6cc193-0d93-491e-9dbe-04770a090aae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221744030 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.4221744030
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.783082304
Short name T776
Test name
Test status
Simulation time 694674412 ps
CPU time 2.03 seconds
Started May 14 01:14:02 PM PDT 24
Finished May 14 01:14:09 PM PDT 24
Peak memory 197796 kb
Host smart-52ecce54-306e-43a3-ad63-120de4aefe03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783082304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.783082304
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.465060748
Short name T830
Test name
Test status
Simulation time 127348720 ps
CPU time 0.84 seconds
Started May 14 01:13:59 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 197140 kb
Host smart-c263e9b1-86b9-4c57-91b2-04ebbc1a1161
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465060748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.465060748
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3016953266
Short name T761
Test name
Test status
Simulation time 67008916 ps
CPU time 0.65 seconds
Started May 14 01:14:13 PM PDT 24
Finished May 14 01:14:17 PM PDT 24
Peak memory 196452 kb
Host smart-6f109a2a-d077-410a-89f3-459a9b694cd2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016953266 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3016953266
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.912875486
Short name T78
Test name
Test status
Simulation time 16255885 ps
CPU time 0.62 seconds
Started May 14 01:14:11 PM PDT 24
Finished May 14 01:14:16 PM PDT 24
Peak memory 194564 kb
Host smart-b9baccde-19fc-4ae5-bed4-b4c074e3636b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912875486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.912875486
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1148716588
Short name T818
Test name
Test status
Simulation time 93306436 ps
CPU time 0.58 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 193556 kb
Host smart-b164131a-a404-4155-bb79-8da5892d3214
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148716588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1148716588
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3309501336
Short name T781
Test name
Test status
Simulation time 16251526 ps
CPU time 0.74 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 195928 kb
Host smart-a4a3771a-d184-4689-b733-9fea1c01825f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309501336 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3309501336
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.894354367
Short name T716
Test name
Test status
Simulation time 107856434 ps
CPU time 1.34 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 197912 kb
Host smart-3a86cf80-902d-4d6f-a7f2-002ad0d5d20b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894354367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.894354367
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.4149857436
Short name T834
Test name
Test status
Simulation time 102897515 ps
CPU time 1.19 seconds
Started May 14 01:14:12 PM PDT 24
Finished May 14 01:14:17 PM PDT 24
Peak memory 198012 kb
Host smart-24f18b0b-205a-4676-9f57-388748034968
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149857436 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.4149857436
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3547968893
Short name T80
Test name
Test status
Simulation time 134476122 ps
CPU time 0.6 seconds
Started May 14 01:14:03 PM PDT 24
Finished May 14 01:14:08 PM PDT 24
Peak memory 194636 kb
Host smart-a3556e15-05e4-4227-9e86-6459c4b29724
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547968893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3547968893
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3888463005
Short name T715
Test name
Test status
Simulation time 36857600 ps
CPU time 0.58 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 193504 kb
Host smart-fb0feb8b-d7e6-4810-af6c-156dc3c0aad7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888463005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3888463005
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3131482562
Short name T823
Test name
Test status
Simulation time 37948859 ps
CPU time 0.84 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 196796 kb
Host smart-94f17ccd-4d1d-4b3a-a80f-07c3e3ef679c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131482562 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3131482562
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2858630208
Short name T760
Test name
Test status
Simulation time 588759864 ps
CPU time 2.08 seconds
Started May 14 01:14:05 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 197936 kb
Host smart-b413db20-1e8a-4d4c-9a71-bbdbfda0e98d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858630208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2858630208
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.4173452899
Short name T831
Test name
Test status
Simulation time 42545062 ps
CPU time 1.03 seconds
Started May 14 01:14:04 PM PDT 24
Finished May 14 01:14:09 PM PDT 24
Peak memory 197944 kb
Host smart-e8de368c-6c89-4a53-90fa-e2d3bef477e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173452899 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.4173452899
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3639432204
Short name T832
Test name
Test status
Simulation time 26963034 ps
CPU time 0.59 seconds
Started May 14 01:14:02 PM PDT 24
Finished May 14 01:14:07 PM PDT 24
Peak memory 194560 kb
Host smart-05489cfb-1595-4cbb-a977-5cd9a2c525e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639432204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3639432204
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3544458386
Short name T767
Test name
Test status
Simulation time 52958293 ps
CPU time 0.62 seconds
Started May 14 01:14:13 PM PDT 24
Finished May 14 01:14:17 PM PDT 24
Peak memory 194276 kb
Host smart-9fa04158-2a0c-4b8d-aa69-d02e6aaf04ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544458386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3544458386
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1070375507
Short name T87
Test name
Test status
Simulation time 51006027 ps
CPU time 0.7 seconds
Started May 14 01:14:05 PM PDT 24
Finished May 14 01:14:10 PM PDT 24
Peak memory 194572 kb
Host smart-609e4f74-f036-45e2-a4fc-acaf6e7353d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070375507 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1070375507
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2653278056
Short name T813
Test name
Test status
Simulation time 49173214 ps
CPU time 2.39 seconds
Started May 14 01:14:06 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 197980 kb
Host smart-f2f0e4b5-2fbe-40da-aa02-36a0d9fb0373
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653278056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2653278056
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1884645571
Short name T44
Test name
Test status
Simulation time 112314939 ps
CPU time 1.45 seconds
Started May 14 01:14:12 PM PDT 24
Finished May 14 01:14:17 PM PDT 24
Peak memory 197992 kb
Host smart-9328eb1c-4043-416f-9548-874e5ab39a5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884645571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1884645571
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.4151255035
Short name T792
Test name
Test status
Simulation time 42021885 ps
CPU time 0.95 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 197912 kb
Host smart-c91230bf-6e0b-45a3-b7fb-7e79b46cff15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151255035 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.4151255035
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.4185767305
Short name T768
Test name
Test status
Simulation time 20545593 ps
CPU time 0.62 seconds
Started May 14 01:14:05 PM PDT 24
Finished May 14 01:14:10 PM PDT 24
Peak memory 194964 kb
Host smart-ab7df163-fc76-46a6-b7e1-addcc88cb8be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185767305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.4185767305
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1832088363
Short name T802
Test name
Test status
Simulation time 33349902 ps
CPU time 0.66 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:13 PM PDT 24
Peak memory 193608 kb
Host smart-ac0d450b-4535-4fff-ae6f-7849dda25f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832088363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1832088363
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.4138425222
Short name T815
Test name
Test status
Simulation time 93379987 ps
CPU time 0.67 seconds
Started May 14 01:14:06 PM PDT 24
Finished May 14 01:14:10 PM PDT 24
Peak memory 195708 kb
Host smart-984779f8-120d-4915-9ce6-17ad03f6fd84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138425222 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.4138425222
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2375033266
Short name T791
Test name
Test status
Simulation time 133215765 ps
CPU time 2.72 seconds
Started May 14 01:14:08 PM PDT 24
Finished May 14 01:14:15 PM PDT 24
Peak memory 197976 kb
Host smart-be12f044-9c49-4d7b-ae07-7385f7a68526
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375033266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2375033266
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1796728920
Short name T106
Test name
Test status
Simulation time 460610869 ps
CPU time 1.45 seconds
Started May 14 01:14:10 PM PDT 24
Finished May 14 01:14:15 PM PDT 24
Peak memory 198216 kb
Host smart-a66a98a1-7997-43dc-8950-6d8e63eb0473
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796728920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1796728920
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.940116558
Short name T714
Test name
Test status
Simulation time 178818441 ps
CPU time 0.69 seconds
Started May 14 01:14:15 PM PDT 24
Finished May 14 01:14:19 PM PDT 24
Peak memory 197188 kb
Host smart-e685b2a9-cecb-4489-b985-c31297028b5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940116558 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.940116558
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.591211571
Short name T104
Test name
Test status
Simulation time 13328140 ps
CPU time 0.65 seconds
Started May 14 01:14:15 PM PDT 24
Finished May 14 01:14:18 PM PDT 24
Peak memory 195076 kb
Host smart-d0c0096d-0f40-4166-9f7a-fda4675894ad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591211571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.591211571
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2568583391
Short name T807
Test name
Test status
Simulation time 41034229 ps
CPU time 0.62 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:13 PM PDT 24
Peak memory 194256 kb
Host smart-10df7f94-8d50-4b5a-a29d-319d8024f370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568583391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2568583391
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2549540520
Short name T828
Test name
Test status
Simulation time 32676626 ps
CPU time 0.84 seconds
Started May 14 01:14:10 PM PDT 24
Finished May 14 01:14:15 PM PDT 24
Peak memory 196176 kb
Host smart-1ed943b6-25df-44ce-a7dd-1ef140c04c0c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549540520 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2549540520
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3326744823
Short name T824
Test name
Test status
Simulation time 89253317 ps
CPU time 2.01 seconds
Started May 14 01:14:07 PM PDT 24
Finished May 14 01:14:13 PM PDT 24
Peak memory 197904 kb
Host smart-a33aeb5e-0a64-40d7-a51b-34248c2cb9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326744823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3326744823
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2423504345
Short name T784
Test name
Test status
Simulation time 111816462 ps
CPU time 1.46 seconds
Started May 14 01:14:12 PM PDT 24
Finished May 14 01:14:17 PM PDT 24
Peak memory 197908 kb
Host smart-02353aae-8f3b-4438-aa22-bba37f313d24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423504345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2423504345
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3309376327
Short name T773
Test name
Test status
Simulation time 218915031 ps
CPU time 1.03 seconds
Started May 14 01:14:13 PM PDT 24
Finished May 14 01:14:17 PM PDT 24
Peak memory 197864 kb
Host smart-aefd224b-fa4d-4418-a9ed-4429f4833b30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309376327 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3309376327
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3448639531
Short name T827
Test name
Test status
Simulation time 13746498 ps
CPU time 0.61 seconds
Started May 14 01:14:10 PM PDT 24
Finished May 14 01:14:15 PM PDT 24
Peak memory 194464 kb
Host smart-2c6c79d2-3a31-40a9-8b04-6c5dde32871a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448639531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3448639531
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3332057647
Short name T742
Test name
Test status
Simulation time 138657960 ps
CPU time 0.56 seconds
Started May 14 01:14:08 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 193560 kb
Host smart-d2716dea-665d-42db-b270-9e9bb7c97572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332057647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3332057647
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.4128137694
Short name T73
Test name
Test status
Simulation time 17666156 ps
CPU time 0.76 seconds
Started May 14 01:14:12 PM PDT 24
Finished May 14 01:14:16 PM PDT 24
Peak memory 196052 kb
Host smart-71afdc20-916b-4e6a-b6c3-ac1f843715a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128137694 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.4128137694
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.782761408
Short name T720
Test name
Test status
Simulation time 106871487 ps
CPU time 2.14 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:15 PM PDT 24
Peak memory 197912 kb
Host smart-7790e25b-2984-429e-b401-5498b7bc6d6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782761408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.782761408
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2109655140
Short name T33
Test name
Test status
Simulation time 86217206 ps
CPU time 0.88 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 197220 kb
Host smart-c842f04f-e40e-4e81-8c9f-867e7646856b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109655140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2109655140
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2400824354
Short name T67
Test name
Test status
Simulation time 12331978 ps
CPU time 0.67 seconds
Started May 14 01:13:55 PM PDT 24
Finished May 14 01:13:58 PM PDT 24
Peak memory 194860 kb
Host smart-9091b196-c1f5-4774-9c9c-c208b7fda7a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400824354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2400824354
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2571390601
Short name T75
Test name
Test status
Simulation time 153386479 ps
CPU time 2.93 seconds
Started May 14 01:14:06 PM PDT 24
Finished May 14 01:14:13 PM PDT 24
Peak memory 197828 kb
Host smart-17fac90a-9b73-4e3d-bb74-61c2111e1dea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571390601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2571390601
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1940365715
Short name T789
Test name
Test status
Simulation time 233926456 ps
CPU time 0.63 seconds
Started May 14 01:14:07 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 194780 kb
Host smart-7ff6a5fa-1870-4735-a1e6-a994e0278565
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940365715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1940365715
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.139288075
Short name T733
Test name
Test status
Simulation time 40663703 ps
CPU time 0.98 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:14:00 PM PDT 24
Peak memory 197916 kb
Host smart-79648f4f-8f0c-4c80-bb23-9ee8b222df41
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139288075 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.139288075
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1807895716
Short name T786
Test name
Test status
Simulation time 46122822 ps
CPU time 0.56 seconds
Started May 14 01:14:05 PM PDT 24
Finished May 14 01:14:10 PM PDT 24
Peak memory 195204 kb
Host smart-33a2761d-a6ca-457f-98d7-0964334e98e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807895716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1807895716
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.382006239
Short name T718
Test name
Test status
Simulation time 159200495 ps
CPU time 0.57 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:13:58 PM PDT 24
Peak memory 193616 kb
Host smart-fdc36bb1-4d30-4d10-b354-d89b40f8c3c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382006239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.382006239
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3056145316
Short name T774
Test name
Test status
Simulation time 21115760 ps
CPU time 0.9 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:01 PM PDT 24
Peak memory 196488 kb
Host smart-84fd9755-dd13-40ae-9729-abaa52a35915
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056145316 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3056145316
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2879092332
Short name T753
Test name
Test status
Simulation time 24899230 ps
CPU time 1.32 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:14:00 PM PDT 24
Peak memory 197952 kb
Host smart-38e3e4b8-3979-4b8e-9a3b-4e4809d6aa30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879092332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2879092332
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1158270309
Short name T42
Test name
Test status
Simulation time 85394383 ps
CPU time 1.22 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:02 PM PDT 24
Peak memory 197980 kb
Host smart-3c7faa96-62ea-459e-8674-0249bc6d294d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158270309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1158270309
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.4197111587
Short name T723
Test name
Test status
Simulation time 22919260 ps
CPU time 0.63 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 193544 kb
Host smart-0281c29f-5e7c-443a-8adf-2d62014b08b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197111587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.4197111587
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.845587396
Short name T787
Test name
Test status
Simulation time 44881840 ps
CPU time 0.63 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 194232 kb
Host smart-804753ee-810f-43cc-8d59-720f11794bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845587396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.845587396
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1882225644
Short name T764
Test name
Test status
Simulation time 49270497 ps
CPU time 0.61 seconds
Started May 14 01:14:08 PM PDT 24
Finished May 14 01:14:13 PM PDT 24
Peak memory 193672 kb
Host smart-51c21b00-8077-4f7b-a7b7-96fc491213a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882225644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1882225644
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.196457981
Short name T724
Test name
Test status
Simulation time 40762703 ps
CPU time 0.61 seconds
Started May 14 01:14:08 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 193680 kb
Host smart-8a32e5f4-b8b4-44cc-bcbf-47d9496910bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196457981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.196457981
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.627315974
Short name T782
Test name
Test status
Simulation time 20502928 ps
CPU time 0.58 seconds
Started May 14 01:14:08 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 194252 kb
Host smart-f34b3801-529f-49c0-ba52-52ca2498dfb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627315974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.627315974
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2733093126
Short name T765
Test name
Test status
Simulation time 15821185 ps
CPU time 0.6 seconds
Started May 14 01:14:08 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 193544 kb
Host smart-73359ef8-631a-4896-8c79-0762aa202366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733093126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2733093126
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1745298675
Short name T739
Test name
Test status
Simulation time 18491419 ps
CPU time 0.62 seconds
Started May 14 01:14:15 PM PDT 24
Finished May 14 01:14:18 PM PDT 24
Peak memory 193576 kb
Host smart-c1593f67-2213-404a-9c62-8abd6e4bef34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745298675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1745298675
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3016545633
Short name T769
Test name
Test status
Simulation time 18507031 ps
CPU time 0.66 seconds
Started May 14 01:14:08 PM PDT 24
Finished May 14 01:14:13 PM PDT 24
Peak memory 194168 kb
Host smart-54639181-1bbd-47c9-b6f6-c6eb4bfc8b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016545633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3016545633
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1006553878
Short name T816
Test name
Test status
Simulation time 16722859 ps
CPU time 0.64 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 194260 kb
Host smart-077788e9-6307-4529-9638-96d14e4940a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006553878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1006553878
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3347902034
Short name T725
Test name
Test status
Simulation time 71757217 ps
CPU time 0.59 seconds
Started May 14 01:14:06 PM PDT 24
Finished May 14 01:14:10 PM PDT 24
Peak memory 193572 kb
Host smart-210190d0-a647-4ae6-8069-3e5453bf1968
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347902034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3347902034
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3363345794
Short name T745
Test name
Test status
Simulation time 60404466 ps
CPU time 0.85 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:03 PM PDT 24
Peak memory 195832 kb
Host smart-b6e8fee4-a829-4321-b264-0d7f4ea4ddca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363345794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3363345794
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2365798018
Short name T86
Test name
Test status
Simulation time 112610759 ps
CPU time 2.27 seconds
Started May 14 01:13:55 PM PDT 24
Finished May 14 01:13:59 PM PDT 24
Peak memory 196596 kb
Host smart-1f04c6cf-552d-4e8e-a529-6e20fba78fc2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365798018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2365798018
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3309551085
Short name T84
Test name
Test status
Simulation time 16631172 ps
CPU time 0.71 seconds
Started May 14 01:13:59 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 194844 kb
Host smart-2d5e8cc6-7839-4dec-af56-1ce362a4794e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309551085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3309551085
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.1981069257
Short name T751
Test name
Test status
Simulation time 22994874 ps
CPU time 0.73 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:00 PM PDT 24
Peak memory 197804 kb
Host smart-460bb0ee-56a1-40e2-ae3b-3b9a99227cad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981069257 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.1981069257
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2410776474
Short name T85
Test name
Test status
Simulation time 12044787 ps
CPU time 0.6 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:13:59 PM PDT 24
Peak memory 195000 kb
Host smart-0c69e7ba-dad3-4268-a1d5-b39de877efcc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410776474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2410776474
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.671084436
Short name T759
Test name
Test status
Simulation time 42150408 ps
CPU time 0.62 seconds
Started May 14 01:13:59 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 194284 kb
Host smart-208d0a68-b205-45fd-aefc-a64518c0d1d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671084436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.671084436
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.564207672
Short name T91
Test name
Test status
Simulation time 25644493 ps
CPU time 0.63 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:13:59 PM PDT 24
Peak memory 194700 kb
Host smart-6faa4f94-3c83-41b2-b2d9-3f44859e70c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564207672 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.564207672
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.603214372
Short name T803
Test name
Test status
Simulation time 202038066 ps
CPU time 2.16 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:14:02 PM PDT 24
Peak memory 198016 kb
Host smart-22399e6f-7eec-4e92-aca9-865ba204f3b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603214372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.603214372
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.1920179053
Short name T752
Test name
Test status
Simulation time 74282996 ps
CPU time 0.63 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 193616 kb
Host smart-d9c88b47-d2df-49a3-a3b3-f584490916f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920179053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.1920179053
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2092130491
Short name T713
Test name
Test status
Simulation time 25247570 ps
CPU time 0.6 seconds
Started May 14 01:14:07 PM PDT 24
Finished May 14 01:14:12 PM PDT 24
Peak memory 193628 kb
Host smart-a74216ef-0809-4378-9625-10ea3a3e8da2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092130491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2092130491
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1104251607
Short name T732
Test name
Test status
Simulation time 17211310 ps
CPU time 0.62 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 193604 kb
Host smart-324fe260-3c07-459c-9bef-92f21d9f4577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104251607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1104251607
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1021945772
Short name T741
Test name
Test status
Simulation time 23315582 ps
CPU time 0.61 seconds
Started May 14 01:14:11 PM PDT 24
Finished May 14 01:14:15 PM PDT 24
Peak memory 193568 kb
Host smart-94925139-4748-4772-98b7-8b81aca825fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021945772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1021945772
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1581555199
Short name T794
Test name
Test status
Simulation time 47969143 ps
CPU time 0.62 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:14 PM PDT 24
Peak memory 193636 kb
Host smart-577e844b-30a3-4d3f-bdee-6036f10b8a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581555199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1581555199
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3526373052
Short name T799
Test name
Test status
Simulation time 24188928 ps
CPU time 0.62 seconds
Started May 14 01:14:16 PM PDT 24
Finished May 14 01:14:19 PM PDT 24
Peak memory 194212 kb
Host smart-f5d25847-e274-4b70-a46b-815f27ee43c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526373052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3526373052
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3496150887
Short name T730
Test name
Test status
Simulation time 17976466 ps
CPU time 0.61 seconds
Started May 14 01:14:16 PM PDT 24
Finished May 14 01:14:19 PM PDT 24
Peak memory 193548 kb
Host smart-34980303-1e02-4be0-90d3-b9e95b425523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496150887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3496150887
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1629532374
Short name T757
Test name
Test status
Simulation time 13670947 ps
CPU time 0.64 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 193656 kb
Host smart-a02477b2-bdb2-49fe-969b-f139ca8eab73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629532374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1629532374
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3342644110
Short name T749
Test name
Test status
Simulation time 15981576 ps
CPU time 0.59 seconds
Started May 14 01:14:22 PM PDT 24
Finished May 14 01:14:25 PM PDT 24
Peak memory 194188 kb
Host smart-1a634484-6db4-4173-ba28-b8f1e3979da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342644110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3342644110
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1328277816
Short name T717
Test name
Test status
Simulation time 20843026 ps
CPU time 0.64 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 194300 kb
Host smart-6114950a-a7a5-455e-8527-78fbff9454ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328277816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1328277816
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3947547414
Short name T82
Test name
Test status
Simulation time 36047274 ps
CPU time 0.83 seconds
Started May 14 01:13:55 PM PDT 24
Finished May 14 01:13:58 PM PDT 24
Peak memory 196732 kb
Host smart-921ab8a2-d037-4a4f-b3fa-85d7706851a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947547414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3947547414
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4211905088
Short name T74
Test name
Test status
Simulation time 917755610 ps
CPU time 2.21 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:03 PM PDT 24
Peak memory 196520 kb
Host smart-49cf11b5-2f78-460b-855b-f95c923acc36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211905088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4211905088
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2809830008
Short name T728
Test name
Test status
Simulation time 16615394 ps
CPU time 0.64 seconds
Started May 14 01:14:03 PM PDT 24
Finished May 14 01:14:08 PM PDT 24
Peak memory 195036 kb
Host smart-44c2bf72-85c9-4445-810b-b93dd09ecc57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809830008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2809830008
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.340606511
Short name T780
Test name
Test status
Simulation time 91850565 ps
CPU time 0.81 seconds
Started May 14 01:13:55 PM PDT 24
Finished May 14 01:13:58 PM PDT 24
Peak memory 197936 kb
Host smart-41f0aa5a-1692-4f7e-b5bb-401e4ef58ed4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340606511 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.340606511
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2194719650
Short name T72
Test name
Test status
Simulation time 21353718 ps
CPU time 0.59 seconds
Started May 14 01:14:02 PM PDT 24
Finished May 14 01:14:08 PM PDT 24
Peak memory 193568 kb
Host smart-52504a8c-a2df-449d-bac8-453d41ba3b17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194719650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2194719650
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3185144930
Short name T758
Test name
Test status
Simulation time 50954986 ps
CPU time 0.62 seconds
Started May 14 01:14:00 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 194232 kb
Host smart-10a9aead-ebae-42cd-853b-cfd6c158218f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185144930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3185144930
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2874695233
Short name T775
Test name
Test status
Simulation time 38590321 ps
CPU time 0.69 seconds
Started May 14 01:14:07 PM PDT 24
Finished May 14 01:14:11 PM PDT 24
Peak memory 194272 kb
Host smart-b3822084-2933-419a-9ca2-3a237c88e3b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874695233 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2874695233
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1420218385
Short name T747
Test name
Test status
Simulation time 504946895 ps
CPU time 2.68 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 197916 kb
Host smart-45061da9-1191-4f23-bbe2-592f0bd10263
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420218385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1420218385
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1003782543
Short name T798
Test name
Test status
Simulation time 42587887 ps
CPU time 0.89 seconds
Started May 14 01:14:02 PM PDT 24
Finished May 14 01:14:08 PM PDT 24
Peak memory 197156 kb
Host smart-255d9995-1585-45e3-957c-daa1931d961b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003782543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1003782543
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3569226487
Short name T754
Test name
Test status
Simulation time 13684598 ps
CPU time 0.61 seconds
Started May 14 01:14:19 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 194228 kb
Host smart-9812050d-0eeb-48a6-857e-77ceacda8540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569226487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3569226487
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.576217176
Short name T750
Test name
Test status
Simulation time 15708576 ps
CPU time 0.64 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 193624 kb
Host smart-85739f2d-0bd0-4530-b993-7240f01dc970
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576217176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.576217176
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3353023954
Short name T804
Test name
Test status
Simulation time 27883902 ps
CPU time 0.65 seconds
Started May 14 01:14:21 PM PDT 24
Finished May 14 01:14:24 PM PDT 24
Peak memory 193628 kb
Host smart-23b839c3-994c-41f8-92fc-f4881ab14d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353023954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3353023954
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2254868102
Short name T783
Test name
Test status
Simulation time 11059133 ps
CPU time 0.64 seconds
Started May 14 01:14:22 PM PDT 24
Finished May 14 01:14:24 PM PDT 24
Peak memory 193660 kb
Host smart-b3b65a92-1728-4cdf-9662-337de288d617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254868102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2254868102
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1981894259
Short name T793
Test name
Test status
Simulation time 18381064 ps
CPU time 0.63 seconds
Started May 14 01:14:16 PM PDT 24
Finished May 14 01:14:19 PM PDT 24
Peak memory 193612 kb
Host smart-492cab9a-2149-43c5-be8b-1af192e4097e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981894259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1981894259
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2563719301
Short name T790
Test name
Test status
Simulation time 49343256 ps
CPU time 0.63 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 194332 kb
Host smart-52a02c4a-f588-4c57-944a-55cecca73bd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563719301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2563719301
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1140296978
Short name T766
Test name
Test status
Simulation time 60125677 ps
CPU time 0.58 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:20 PM PDT 24
Peak memory 193584 kb
Host smart-32bbaaca-7e4f-4604-ae91-92a1d7bac462
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140296978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1140296978
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2342982629
Short name T721
Test name
Test status
Simulation time 11959616 ps
CPU time 0.61 seconds
Started May 14 01:14:16 PM PDT 24
Finished May 14 01:14:19 PM PDT 24
Peak memory 193688 kb
Host smart-c8e7bf6a-e8b2-4760-bc65-4901ef94f6e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342982629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2342982629
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.820512393
Short name T743
Test name
Test status
Simulation time 14188755 ps
CPU time 0.6 seconds
Started May 14 01:14:21 PM PDT 24
Finished May 14 01:14:24 PM PDT 24
Peak memory 193576 kb
Host smart-1f35f3c9-2758-475e-89de-9d42e7dde92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820512393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.820512393
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3917307394
Short name T822
Test name
Test status
Simulation time 11135550 ps
CPU time 0.6 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 193848 kb
Host smart-1c0d9e19-c1eb-4d9b-a51c-2948febcdc49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917307394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3917307394
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1921857805
Short name T719
Test name
Test status
Simulation time 20303759 ps
CPU time 0.87 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:14:00 PM PDT 24
Peak memory 197876 kb
Host smart-5dfff19f-6e93-4e2b-a723-452daec444a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921857805 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1921857805
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2227513239
Short name T70
Test name
Test status
Simulation time 49118914 ps
CPU time 0.6 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:13:59 PM PDT 24
Peak memory 194560 kb
Host smart-673fc994-0a06-49d1-9e9b-4aead79b296b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227513239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2227513239
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3470670308
Short name T755
Test name
Test status
Simulation time 31678317 ps
CPU time 0.6 seconds
Started May 14 01:13:59 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 193616 kb
Host smart-d51cf4c1-940b-46d6-ac78-1c348cf6edb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470670308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3470670308
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1786690035
Short name T806
Test name
Test status
Simulation time 70135635 ps
CPU time 0.96 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:02 PM PDT 24
Peak memory 197360 kb
Host smart-9ef46323-ecb0-43c6-8330-cb92e01dfa42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786690035 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1786690035
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.725417572
Short name T779
Test name
Test status
Simulation time 123866215 ps
CPU time 2.22 seconds
Started May 14 01:14:02 PM PDT 24
Finished May 14 01:14:09 PM PDT 24
Peak memory 197888 kb
Host smart-1d49da0c-ed2f-4bba-b202-2ed3ad4557c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725417572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.725417572
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.3790075084
Short name T819
Test name
Test status
Simulation time 45313777 ps
CPU time 0.88 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 197204 kb
Host smart-c7a6ff11-369c-40d9-ad12-b9ee6043c92f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790075084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.3790075084
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.165757656
Short name T748
Test name
Test status
Simulation time 83054241 ps
CPU time 1.15 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:01 PM PDT 24
Peak memory 197936 kb
Host smart-9e6087f6-9d73-4b8b-950b-943f0bda73e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165757656 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.165757656
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1781611899
Short name T83
Test name
Test status
Simulation time 16445131 ps
CPU time 0.64 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:03 PM PDT 24
Peak memory 194628 kb
Host smart-0e160dfe-f85a-441a-ad26-9a482b0356e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781611899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1781611899
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.120143671
Short name T712
Test name
Test status
Simulation time 13776093 ps
CPU time 0.61 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:14:00 PM PDT 24
Peak memory 194220 kb
Host smart-ea2f7ded-731a-4945-8a10-b43f69c0d3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120143671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.120143671
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.217518997
Short name T88
Test name
Test status
Simulation time 217460346 ps
CPU time 0.61 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:13:59 PM PDT 24
Peak memory 194788 kb
Host smart-7ab5a43d-d6ee-4dab-9a69-64166c62b90c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217518997 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.217518997
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.615338386
Short name T800
Test name
Test status
Simulation time 321572195 ps
CPU time 2.06 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:14:01 PM PDT 24
Peak memory 198228 kb
Host smart-1cf4c2a0-2a29-4485-a57c-7247c73e9e47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615338386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.615338386
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.517795409
Short name T820
Test name
Test status
Simulation time 141515058 ps
CPU time 1.13 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:13:59 PM PDT 24
Peak memory 197920 kb
Host smart-ed82f7ea-06c6-406c-9e03-38d0951fd826
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517795409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.517795409
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3118513640
Short name T736
Test name
Test status
Simulation time 202625013 ps
CPU time 1.12 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:03 PM PDT 24
Peak memory 197804 kb
Host smart-c49e9397-9d89-454a-ba2d-265b42938b31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118513640 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3118513640
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2743801800
Short name T833
Test name
Test status
Simulation time 51448235 ps
CPU time 0.58 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:01 PM PDT 24
Peak memory 193468 kb
Host smart-462f8184-fda5-4e00-8551-684f4d4ae0a1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743801800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2743801800
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.411831026
Short name T771
Test name
Test status
Simulation time 11290829 ps
CPU time 0.61 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:14:00 PM PDT 24
Peak memory 193624 kb
Host smart-f734f7b7-c6c8-4380-bad9-ea74b53d4547
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411831026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.411831026
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.697861512
Short name T811
Test name
Test status
Simulation time 37412405 ps
CPU time 0.92 seconds
Started May 14 01:14:01 PM PDT 24
Finished May 14 01:14:06 PM PDT 24
Peak memory 196924 kb
Host smart-4fe833c0-7026-4150-91e5-1f48d8903706
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697861512 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.697861512
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2746038047
Short name T763
Test name
Test status
Simulation time 134043749 ps
CPU time 2.59 seconds
Started May 14 01:13:54 PM PDT 24
Finished May 14 01:13:58 PM PDT 24
Peak memory 197932 kb
Host smart-aac98e32-07eb-4142-9e99-3668c1a8595f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746038047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2746038047
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3334194845
Short name T797
Test name
Test status
Simulation time 48845021 ps
CPU time 0.95 seconds
Started May 14 01:13:59 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 197852 kb
Host smart-37a7b443-e6ba-408d-b5da-f55206e4fc6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334194845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3334194845
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2029410057
Short name T796
Test name
Test status
Simulation time 53900512 ps
CPU time 0.87 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:13:58 PM PDT 24
Peak memory 197820 kb
Host smart-0cc1aef7-b832-4b5d-a389-59383608ac9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029410057 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2029410057
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3982360366
Short name T77
Test name
Test status
Simulation time 98337116 ps
CPU time 0.57 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:01 PM PDT 24
Peak memory 193924 kb
Host smart-ebf95d1a-b9c8-4cf6-a4a1-7c48a3e3bdfe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982360366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3982360366
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2848048164
Short name T817
Test name
Test status
Simulation time 13202324 ps
CPU time 0.63 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:02 PM PDT 24
Peak memory 193692 kb
Host smart-7368574e-37b4-426c-a12f-cf2706de06f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848048164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2848048164
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3238184800
Short name T812
Test name
Test status
Simulation time 46249934 ps
CPU time 0.63 seconds
Started May 14 01:13:57 PM PDT 24
Finished May 14 01:14:01 PM PDT 24
Peak memory 195412 kb
Host smart-afdfca78-5397-4fc2-a27a-7665d85bea16
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238184800 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3238184800
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2308118092
Short name T711
Test name
Test status
Simulation time 577922571 ps
CPU time 2.99 seconds
Started May 14 01:13:56 PM PDT 24
Finished May 14 01:14:02 PM PDT 24
Peak memory 197980 kb
Host smart-1e076107-e55a-430e-a106-9ae11d97674a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308118092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2308118092
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.125169870
Short name T809
Test name
Test status
Simulation time 468098115 ps
CPU time 1.46 seconds
Started May 14 01:13:59 PM PDT 24
Finished May 14 01:14:04 PM PDT 24
Peak memory 197968 kb
Host smart-6737c7f7-c06d-49a3-ae2e-ee5a5a8b9d7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125169870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.gpio_tl_intg_err.125169870
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1446179227
Short name T814
Test name
Test status
Simulation time 117250766 ps
CPU time 0.84 seconds
Started May 14 01:14:09 PM PDT 24
Finished May 14 01:14:13 PM PDT 24
Peak memory 197888 kb
Host smart-b20b3500-b8e8-4850-b39d-ae34923aaf98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446179227 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1446179227
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1662490539
Short name T788
Test name
Test status
Simulation time 12615555 ps
CPU time 0.58 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:03 PM PDT 24
Peak memory 193252 kb
Host smart-f88dba6a-6da2-4c0b-84c8-b10d984b59e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662490539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1662490539
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3744886329
Short name T727
Test name
Test status
Simulation time 39929583 ps
CPU time 0.57 seconds
Started May 14 01:14:12 PM PDT 24
Finished May 14 01:14:16 PM PDT 24
Peak memory 193592 kb
Host smart-e855e0dc-fa92-4071-aff8-ff3551fe896c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744886329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3744886329
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.632762655
Short name T90
Test name
Test status
Simulation time 39221737 ps
CPU time 0.78 seconds
Started May 14 01:13:58 PM PDT 24
Finished May 14 01:14:02 PM PDT 24
Peak memory 196332 kb
Host smart-279115ee-65b1-40f2-8ade-615473f22466
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632762655 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.632762655
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.858819088
Short name T726
Test name
Test status
Simulation time 57742545 ps
CPU time 1.34 seconds
Started May 14 01:14:13 PM PDT 24
Finished May 14 01:14:17 PM PDT 24
Peak memory 197932 kb
Host smart-d65ea896-82b8-468a-9b2b-904f354e1205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858819088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.858819088
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3284114478
Short name T34
Test name
Test status
Simulation time 46247549 ps
CPU time 0.97 seconds
Started May 14 01:14:02 PM PDT 24
Finished May 14 01:14:07 PM PDT 24
Peak memory 197004 kb
Host smart-1b66f4e2-f163-4ec2-a030-e5320a6d9849
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284114478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3284114478
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2828136207
Short name T554
Test name
Test status
Simulation time 52918535 ps
CPU time 0.57 seconds
Started May 14 01:14:33 PM PDT 24
Finished May 14 01:14:36 PM PDT 24
Peak memory 194612 kb
Host smart-c2015f92-17ce-450c-82ca-e8d7525cc89c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828136207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2828136207
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2180292560
Short name T326
Test name
Test status
Simulation time 33147298 ps
CPU time 0.87 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 195508 kb
Host smart-832e90d5-2ca1-4803-b7c3-9c172717653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180292560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2180292560
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2730973199
Short name T441
Test name
Test status
Simulation time 1018538999 ps
CPU time 15.4 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 196944 kb
Host smart-dd8f5234-a50e-4d1b-9436-8c676fb2d708
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730973199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2730973199
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2316478043
Short name T20
Test name
Test status
Simulation time 281371489 ps
CPU time 1.18 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 196388 kb
Host smart-5b751bc7-5213-47df-8ed2-e76c53051928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316478043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2316478043
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1563474112
Short name T709
Test name
Test status
Simulation time 48090999 ps
CPU time 1.28 seconds
Started May 14 01:14:38 PM PDT 24
Finished May 14 01:14:42 PM PDT 24
Peak memory 197228 kb
Host smart-ea7cda20-9df1-4b30-88ec-50064cac7cd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563474112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1563474112
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1870492196
Short name T217
Test name
Test status
Simulation time 341582131 ps
CPU time 3.28 seconds
Started May 14 01:14:40 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 198044 kb
Host smart-acb7f250-3728-4965-a741-9cfb937c272a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870492196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1870492196
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4040715151
Short name T13
Test name
Test status
Simulation time 580728974 ps
CPU time 2.57 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:40 PM PDT 24
Peak memory 195788 kb
Host smart-f7d77a6c-7bbd-4b40-a838-bb188ae44b44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040715151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4040715151
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3536320089
Short name T176
Test name
Test status
Simulation time 47929744 ps
CPU time 0.99 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 196008 kb
Host smart-72091c75-f7ca-48e0-95dc-2d026075f3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536320089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3536320089
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3026779572
Short name T505
Test name
Test status
Simulation time 49337901 ps
CPU time 0.73 seconds
Started May 14 01:14:39 PM PDT 24
Finished May 14 01:14:42 PM PDT 24
Peak memory 194420 kb
Host smart-6db27d80-e49d-429a-b50d-0fe7b9ac25ac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026779572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3026779572
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1982507290
Short name T183
Test name
Test status
Simulation time 160706294 ps
CPU time 2.83 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:54 PM PDT 24
Peak memory 197924 kb
Host smart-2dfac14d-1ef2-4b99-8154-2095cff11068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982507290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1982507290
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.3140741094
Short name T272
Test name
Test status
Simulation time 57234998 ps
CPU time 1.19 seconds
Started May 14 01:14:33 PM PDT 24
Finished May 14 01:14:36 PM PDT 24
Peak memory 196568 kb
Host smart-28d1d47e-b468-43e7-8cc4-2b99aa2e37df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140741094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3140741094
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3106858317
Short name T187
Test name
Test status
Simulation time 33900782 ps
CPU time 1.07 seconds
Started May 14 01:14:37 PM PDT 24
Finished May 14 01:14:40 PM PDT 24
Peak memory 196384 kb
Host smart-96b491ca-b18f-4943-af1a-42f61f812608
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106858317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3106858317
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1685547119
Short name T296
Test name
Test status
Simulation time 37001391641 ps
CPU time 44.02 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:15:35 PM PDT 24
Peak memory 198136 kb
Host smart-5762f620-3fbe-450f-a4f4-12cab092acd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685547119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1685547119
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1707794699
Short name T245
Test name
Test status
Simulation time 28092570 ps
CPU time 0.57 seconds
Started May 14 01:14:40 PM PDT 24
Finished May 14 01:14:43 PM PDT 24
Peak memory 193848 kb
Host smart-0437e736-3067-4faf-9141-08d14d9e3642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707794699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1707794699
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1111548541
Short name T103
Test name
Test status
Simulation time 30677432 ps
CPU time 1 seconds
Started May 14 01:14:34 PM PDT 24
Finished May 14 01:14:37 PM PDT 24
Peak memory 195712 kb
Host smart-9c20d2a9-ca3d-4804-9784-af32a7543305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111548541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1111548541
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3507574694
Short name T654
Test name
Test status
Simulation time 457501620 ps
CPU time 23.57 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:15:16 PM PDT 24
Peak memory 195484 kb
Host smart-d02a6461-10b7-4ce2-a7c2-bd45b61e810e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507574694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3507574694
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.689829994
Short name T258
Test name
Test status
Simulation time 38469436 ps
CPU time 0.75 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 195964 kb
Host smart-432da7f6-4417-425e-8226-121561cdaa3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689829994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.689829994
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3755957992
Short name T347
Test name
Test status
Simulation time 161212765 ps
CPU time 0.88 seconds
Started May 14 01:14:37 PM PDT 24
Finished May 14 01:14:40 PM PDT 24
Peak memory 196532 kb
Host smart-30a888c0-084b-4788-9f21-fc752ddb219a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755957992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3755957992
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1892683554
Short name T53
Test name
Test status
Simulation time 37463191 ps
CPU time 1.52 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 196936 kb
Host smart-2576dd0c-93fb-455b-9567-24dbdea00fe0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892683554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1892683554
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.723207608
Short name T208
Test name
Test status
Simulation time 280799394 ps
CPU time 2.11 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:47 PM PDT 24
Peak memory 196732 kb
Host smart-ef06e056-6597-4c56-a82c-d333fd56f072
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723207608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.723207608
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.4137573745
Short name T54
Test name
Test status
Simulation time 213700690 ps
CPU time 1.06 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 195952 kb
Host smart-019a4769-4bc4-4b20-b05c-d46e735457f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137573745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.4137573745
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2826114631
Short name T637
Test name
Test status
Simulation time 41009229 ps
CPU time 0.73 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 194936 kb
Host smart-53c5bd15-c64e-47b8-b14c-d215fcdfac69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826114631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2826114631
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3992165683
Short name T535
Test name
Test status
Simulation time 233180132 ps
CPU time 2.85 seconds
Started May 14 01:14:41 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 197904 kb
Host smart-eb0f8fbf-c236-4461-a8bf-721238ae400e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992165683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3992165683
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2724190372
Short name T47
Test name
Test status
Simulation time 39779775 ps
CPU time 0.82 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:53 PM PDT 24
Peak memory 213696 kb
Host smart-86226c4c-033d-47fe-8f08-d21347561d03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724190372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2724190372
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.42973298
Short name T277
Test name
Test status
Simulation time 45289081 ps
CPU time 1.06 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 195544 kb
Host smart-91172d6c-7822-40b0-8bf5-6f02d133c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42973298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.42973298
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3189208461
Short name T240
Test name
Test status
Simulation time 34264309 ps
CPU time 1.02 seconds
Started May 14 01:14:38 PM PDT 24
Finished May 14 01:14:42 PM PDT 24
Peak memory 195668 kb
Host smart-6c8646b2-9944-4883-8c06-39edab91adbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189208461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3189208461
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.4207317249
Short name T476
Test name
Test status
Simulation time 15080163887 ps
CPU time 206.79 seconds
Started May 14 01:14:41 PM PDT 24
Finished May 14 01:18:10 PM PDT 24
Peak memory 198096 kb
Host smart-ba3fa0a5-85f4-461c-89bb-9f8a2c27baaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207317249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.4207317249
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2174612706
Short name T407
Test name
Test status
Simulation time 43569976 ps
CPU time 0.56 seconds
Started May 14 01:14:53 PM PDT 24
Finished May 14 01:14:57 PM PDT 24
Peak memory 193852 kb
Host smart-8a2556aa-7b57-48d3-b9a6-ec000ae8d8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174612706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2174612706
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3360633178
Short name T656
Test name
Test status
Simulation time 75877480 ps
CPU time 0.77 seconds
Started May 14 01:14:55 PM PDT 24
Finished May 14 01:15:00 PM PDT 24
Peak memory 195304 kb
Host smart-19fd3518-72e6-46c7-8e09-d63d1b859d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360633178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3360633178
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3180112758
Short name T95
Test name
Test status
Simulation time 1585126658 ps
CPU time 19.35 seconds
Started May 14 01:14:53 PM PDT 24
Finished May 14 01:15:16 PM PDT 24
Peak memory 197024 kb
Host smart-c89b6e3e-0160-45d9-880d-084dd83b797d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180112758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3180112758
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1323163609
Short name T16
Test name
Test status
Simulation time 101262063 ps
CPU time 0.62 seconds
Started May 14 01:14:50 PM PDT 24
Finished May 14 01:14:55 PM PDT 24
Peak memory 194556 kb
Host smart-f9243043-8d05-4c25-ae9b-13314655454e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323163609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1323163609
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.324638602
Short name T577
Test name
Test status
Simulation time 230458308 ps
CPU time 0.94 seconds
Started May 14 01:15:03 PM PDT 24
Finished May 14 01:15:07 PM PDT 24
Peak memory 195916 kb
Host smart-81a25767-4266-4099-9f62-fc5fc172ef80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324638602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.324638602
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2395865932
Short name T475
Test name
Test status
Simulation time 209255976 ps
CPU time 1.98 seconds
Started May 14 01:15:02 PM PDT 24
Finished May 14 01:15:06 PM PDT 24
Peak memory 198140 kb
Host smart-38cb15ab-131b-4c69-bc75-b0b234b9754a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395865932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2395865932
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3073653862
Short name T669
Test name
Test status
Simulation time 127662849 ps
CPU time 2.9 seconds
Started May 14 01:15:00 PM PDT 24
Finished May 14 01:15:05 PM PDT 24
Peak memory 196964 kb
Host smart-69648a06-1853-44af-b6c1-d16834a24955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073653862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3073653862
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2936879707
Short name T510
Test name
Test status
Simulation time 16784680 ps
CPU time 0.72 seconds
Started May 14 01:14:53 PM PDT 24
Finished May 14 01:14:58 PM PDT 24
Peak memory 194356 kb
Host smart-20e66ddc-8189-40c0-b19c-d303c45e03b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936879707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2936879707
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2160471030
Short name T393
Test name
Test status
Simulation time 152999056 ps
CPU time 1.16 seconds
Started May 14 01:14:59 PM PDT 24
Finished May 14 01:15:03 PM PDT 24
Peak memory 196688 kb
Host smart-abb131e0-449c-4455-bb69-343f53d4b9a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160471030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2160471030
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2988775006
Short name T368
Test name
Test status
Simulation time 2149826886 ps
CPU time 6.81 seconds
Started May 14 01:14:57 PM PDT 24
Finished May 14 01:15:07 PM PDT 24
Peak memory 197980 kb
Host smart-b07b72b9-c69c-482c-a68a-ca4f931628c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988775006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2988775006
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.635455891
Short name T196
Test name
Test status
Simulation time 201389335 ps
CPU time 0.93 seconds
Started May 14 01:15:02 PM PDT 24
Finished May 14 01:15:05 PM PDT 24
Peak memory 196972 kb
Host smart-2889b621-561e-44b8-86dd-52a8a5ecd2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635455891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.635455891
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3414062297
Short name T586
Test name
Test status
Simulation time 47171912 ps
CPU time 1.34 seconds
Started May 14 01:14:52 PM PDT 24
Finished May 14 01:14:58 PM PDT 24
Peak memory 196752 kb
Host smart-4b41eea4-82a2-4d8f-bac5-d71c14621ce3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414062297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3414062297
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3373181922
Short name T192
Test name
Test status
Simulation time 6144602039 ps
CPU time 152.7 seconds
Started May 14 01:14:52 PM PDT 24
Finished May 14 01:17:29 PM PDT 24
Peak memory 198144 kb
Host smart-89b88f29-f6a9-479b-ba3b-9e88dc971079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373181922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3373181922
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3270001446
Short name T64
Test name
Test status
Simulation time 134812120149 ps
CPU time 1828.71 seconds
Started May 14 01:14:53 PM PDT 24
Finished May 14 01:45:26 PM PDT 24
Peak memory 198232 kb
Host smart-66d98c46-e9da-4c1e-95df-f7c8ace36628
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3270001446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3270001446
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2930068602
Short name T439
Test name
Test status
Simulation time 23519077 ps
CPU time 0.62 seconds
Started May 14 01:14:53 PM PDT 24
Finished May 14 01:14:58 PM PDT 24
Peak memory 194604 kb
Host smart-5f6db295-dc6e-42c0-8844-657a87de033a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930068602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2930068602
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.175866341
Short name T619
Test name
Test status
Simulation time 12902721 ps
CPU time 0.58 seconds
Started May 14 01:14:58 PM PDT 24
Finished May 14 01:15:01 PM PDT 24
Peak memory 194000 kb
Host smart-ba4d9b86-c748-48fd-b1d9-5979e79d4eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175866341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.175866341
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.3368621913
Short name T371
Test name
Test status
Simulation time 268376785 ps
CPU time 8.92 seconds
Started May 14 01:14:59 PM PDT 24
Finished May 14 01:15:10 PM PDT 24
Peak memory 194864 kb
Host smart-15c19d23-a62d-4aab-bcb2-3451645225fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368621913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.3368621913
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2454728263
Short name T52
Test name
Test status
Simulation time 45941445 ps
CPU time 0.79 seconds
Started May 14 01:14:55 PM PDT 24
Finished May 14 01:15:00 PM PDT 24
Peak memory 195864 kb
Host smart-211d5626-f768-4aa6-9d21-2937059c5e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454728263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2454728263
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1253985180
Short name T158
Test name
Test status
Simulation time 73194190 ps
CPU time 1.24 seconds
Started May 14 01:14:53 PM PDT 24
Finished May 14 01:14:58 PM PDT 24
Peak memory 196712 kb
Host smart-f6a7f043-041c-401e-b457-387a093e3135
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253985180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1253985180
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2393395291
Short name T486
Test name
Test status
Simulation time 729533308 ps
CPU time 1.9 seconds
Started May 14 01:14:56 PM PDT 24
Finished May 14 01:15:01 PM PDT 24
Peak memory 198072 kb
Host smart-df9ed701-838f-4b25-a72b-342809fb5b2a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393395291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2393395291
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1775861903
Short name T497
Test name
Test status
Simulation time 257968534 ps
CPU time 1.61 seconds
Started May 14 01:15:01 PM PDT 24
Finished May 14 01:15:04 PM PDT 24
Peak memory 195960 kb
Host smart-69c7cde7-12ac-4b6e-b7a0-770694584684
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775861903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1775861903
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4083540056
Short name T540
Test name
Test status
Simulation time 43340540 ps
CPU time 0.63 seconds
Started May 14 01:14:58 PM PDT 24
Finished May 14 01:15:01 PM PDT 24
Peak memory 194264 kb
Host smart-8ac4ecb0-ee43-4e53-a6aa-2c313d2c1c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083540056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4083540056
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.766916018
Short name T112
Test name
Test status
Simulation time 58084365 ps
CPU time 1.14 seconds
Started May 14 01:15:00 PM PDT 24
Finished May 14 01:15:04 PM PDT 24
Peak memory 195828 kb
Host smart-b13d5ea3-24b6-49a1-92be-701fb314d177
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766916018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.766916018
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.311979699
Short name T506
Test name
Test status
Simulation time 372517018 ps
CPU time 1.42 seconds
Started May 14 01:14:51 PM PDT 24
Finished May 14 01:14:57 PM PDT 24
Peak memory 197952 kb
Host smart-0d9826d3-ede8-43f6-aa70-baf837f8dcce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311979699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.311979699
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2874492391
Short name T225
Test name
Test status
Simulation time 35462826 ps
CPU time 1.03 seconds
Started May 14 01:14:51 PM PDT 24
Finished May 14 01:14:57 PM PDT 24
Peak memory 195504 kb
Host smart-474d46de-f820-47f2-9761-96fcc0e03f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874492391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2874492391
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.578198643
Short name T634
Test name
Test status
Simulation time 367531033 ps
CPU time 1.4 seconds
Started May 14 01:15:13 PM PDT 24
Finished May 14 01:15:18 PM PDT 24
Peak memory 196872 kb
Host smart-722577bf-7ed2-49bc-83c4-eb01c2fac1a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578198643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.578198643
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.144647495
Short name T4
Test name
Test status
Simulation time 19215059927 ps
CPU time 219.72 seconds
Started May 14 01:15:01 PM PDT 24
Finished May 14 01:18:43 PM PDT 24
Peak memory 198076 kb
Host smart-8bbd1511-2675-4324-9360-033c30e611e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144647495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.144647495
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1598663885
Short name T702
Test name
Test status
Simulation time 19535985 ps
CPU time 0.55 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 194584 kb
Host smart-62b740d9-db0f-40a5-b424-8d05c1d898ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598663885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1598663885
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.449694159
Short name T536
Test name
Test status
Simulation time 23155734 ps
CPU time 0.65 seconds
Started May 14 01:14:57 PM PDT 24
Finished May 14 01:15:00 PM PDT 24
Peak memory 194020 kb
Host smart-7a228788-c839-483d-a134-44fc28b7e4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449694159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.449694159
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2650094755
Short name T460
Test name
Test status
Simulation time 2019527648 ps
CPU time 7.56 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:15:15 PM PDT 24
Peak memory 195516 kb
Host smart-fe519a9a-3ca6-4ad4-ba91-24ff36d5e3c4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650094755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2650094755
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.30899564
Short name T663
Test name
Test status
Simulation time 58869411 ps
CPU time 1.03 seconds
Started May 14 01:14:59 PM PDT 24
Finished May 14 01:15:02 PM PDT 24
Peak memory 196500 kb
Host smart-31572cce-563d-43a3-9327-3fd759cea7ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30899564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.30899564
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.56814554
Short name T635
Test name
Test status
Simulation time 61138533 ps
CPU time 0.82 seconds
Started May 14 01:15:00 PM PDT 24
Finished May 14 01:15:03 PM PDT 24
Peak memory 196176 kb
Host smart-8f9235f6-e74e-4478-999d-aa8d0ad6fa1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56814554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.56814554
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3064563663
Short name T425
Test name
Test status
Simulation time 245739910 ps
CPU time 2.96 seconds
Started May 14 01:15:12 PM PDT 24
Finished May 14 01:15:17 PM PDT 24
Peak memory 198116 kb
Host smart-2e824682-6b35-47bc-97fd-77dfc41ac639
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064563663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3064563663
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2756661144
Short name T560
Test name
Test status
Simulation time 81574123 ps
CPU time 1.02 seconds
Started May 14 01:15:03 PM PDT 24
Finished May 14 01:15:06 PM PDT 24
Peak memory 195488 kb
Host smart-42bb1c1a-1945-4d19-92ef-979d073fdbb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756661144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2756661144
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1204738614
Short name T342
Test name
Test status
Simulation time 39996770 ps
CPU time 0.9 seconds
Started May 14 01:14:56 PM PDT 24
Finished May 14 01:15:01 PM PDT 24
Peak memory 196016 kb
Host smart-73882dbc-5afb-4a3d-83ae-4b16637679c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204738614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1204738614
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.248869754
Short name T562
Test name
Test status
Simulation time 127943349 ps
CPU time 0.9 seconds
Started May 14 01:14:54 PM PDT 24
Finished May 14 01:14:59 PM PDT 24
Peak memory 196464 kb
Host smart-6ae7ce21-0c9d-40b5-96b4-6e3e1b0a9cb8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248869754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.248869754
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.529807271
Short name T263
Test name
Test status
Simulation time 83923238 ps
CPU time 1.54 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:12 PM PDT 24
Peak memory 197984 kb
Host smart-42f9f8e7-adc5-462d-9de8-b0601b1b9d6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529807271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.529807271
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1004150265
Short name T507
Test name
Test status
Simulation time 61187289 ps
CPU time 1.2 seconds
Started May 14 01:15:00 PM PDT 24
Finished May 14 01:15:04 PM PDT 24
Peak memory 196408 kb
Host smart-7bab492b-026e-4b5e-a4c0-ac7d23f2ce83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004150265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1004150265
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3972759159
Short name T376
Test name
Test status
Simulation time 38286524 ps
CPU time 1.21 seconds
Started May 14 01:14:52 PM PDT 24
Finished May 14 01:14:58 PM PDT 24
Peak memory 197100 kb
Host smart-e5e0dda5-4b29-4c4d-8b1e-898247367c20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972759159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3972759159
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2549297406
Short name T399
Test name
Test status
Simulation time 147056882823 ps
CPU time 170.09 seconds
Started May 14 01:15:06 PM PDT 24
Finished May 14 01:17:59 PM PDT 24
Peak memory 198128 kb
Host smart-42444b56-993e-4364-8a36-b40c09de499b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549297406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2549297406
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1255565160
Short name T351
Test name
Test status
Simulation time 35546091 ps
CPU time 0.79 seconds
Started May 14 01:15:03 PM PDT 24
Finished May 14 01:15:07 PM PDT 24
Peak memory 196184 kb
Host smart-287d0f53-c92d-4524-acc6-35d707db6e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255565160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1255565160
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.449228839
Short name T303
Test name
Test status
Simulation time 1031694925 ps
CPU time 12.64 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:15:25 PM PDT 24
Peak memory 197984 kb
Host smart-372972d4-bd2e-4800-af9e-0552323cf657
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449228839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.449228839
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2324921990
Short name T414
Test name
Test status
Simulation time 118305752 ps
CPU time 0.93 seconds
Started May 14 01:15:14 PM PDT 24
Finished May 14 01:15:18 PM PDT 24
Peak memory 197256 kb
Host smart-522f954b-89dc-4510-892f-2e6af3425ffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324921990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2324921990
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.4130206899
Short name T432
Test name
Test status
Simulation time 67634521 ps
CPU time 0.84 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:15:08 PM PDT 24
Peak memory 196108 kb
Host smart-2024221e-7e31-4161-84d9-94915ab708ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130206899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.4130206899
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.4227609580
Short name T320
Test name
Test status
Simulation time 38680595 ps
CPU time 1.59 seconds
Started May 14 01:15:04 PM PDT 24
Finished May 14 01:15:08 PM PDT 24
Peak memory 198088 kb
Host smart-3e02a2ea-60a8-49a4-9d28-fb4fb7d5085a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227609580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.4227609580
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3616333525
Short name T319
Test name
Test status
Simulation time 69812911 ps
CPU time 2.08 seconds
Started May 14 01:15:01 PM PDT 24
Finished May 14 01:15:05 PM PDT 24
Peak memory 198056 kb
Host smart-9d480489-f775-4c7f-aca3-8a753e7dffea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616333525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3616333525
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1107322880
Short name T374
Test name
Test status
Simulation time 38232341 ps
CPU time 0.95 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:12 PM PDT 24
Peak memory 196720 kb
Host smart-dc83a2e0-9df6-4e45-9479-b3e0f1116ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107322880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1107322880
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1742446181
Short name T115
Test name
Test status
Simulation time 1035904661 ps
CPU time 1.32 seconds
Started May 14 01:15:21 PM PDT 24
Finished May 14 01:15:24 PM PDT 24
Peak memory 196560 kb
Host smart-49e1e11d-6fae-476d-b836-7e059bb57d12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742446181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1742446181
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3418870434
Short name T401
Test name
Test status
Simulation time 110665115 ps
CPU time 5.09 seconds
Started May 14 01:15:10 PM PDT 24
Finished May 14 01:15:18 PM PDT 24
Peak memory 197948 kb
Host smart-a472c7f4-e7e1-4901-84df-6fd72c21f1e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418870434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3418870434
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2696645693
Short name T466
Test name
Test status
Simulation time 260342716 ps
CPU time 1.2 seconds
Started May 14 01:15:31 PM PDT 24
Finished May 14 01:15:35 PM PDT 24
Peak memory 195656 kb
Host smart-a2f53daa-4155-4290-a71f-d4c665796a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696645693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2696645693
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3051855599
Short name T129
Test name
Test status
Simulation time 336672150 ps
CPU time 0.98 seconds
Started May 14 01:15:10 PM PDT 24
Finished May 14 01:15:14 PM PDT 24
Peak memory 196500 kb
Host smart-c2153cfe-86db-4d00-bc7d-430558c067f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051855599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3051855599
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2093560188
Short name T381
Test name
Test status
Simulation time 6899770036 ps
CPU time 84.6 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:16:33 PM PDT 24
Peak memory 198104 kb
Host smart-cc7f13bc-6e0e-436b-83c5-35f4abbe435b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093560188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2093560188
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1579866457
Short name T149
Test name
Test status
Simulation time 51883869 ps
CPU time 0.57 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:15:08 PM PDT 24
Peak memory 194104 kb
Host smart-708b5aca-eb8f-4b44-ae5d-53e5c1272d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579866457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1579866457
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.535660375
Short name T132
Test name
Test status
Simulation time 28999267 ps
CPU time 0.86 seconds
Started May 14 01:15:01 PM PDT 24
Finished May 14 01:15:04 PM PDT 24
Peak memory 195720 kb
Host smart-1ef4f8c2-339c-4dc8-a256-25c6a1800fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535660375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.535660375
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1507971453
Short name T130
Test name
Test status
Simulation time 633285247 ps
CPU time 20.93 seconds
Started May 14 01:15:12 PM PDT 24
Finished May 14 01:15:36 PM PDT 24
Peak memory 196992 kb
Host smart-5e21ee2e-1ebf-4c5a-b8b9-2effa41a004e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507971453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1507971453
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1057064714
Short name T489
Test name
Test status
Simulation time 310846761 ps
CPU time 0.98 seconds
Started May 14 01:15:01 PM PDT 24
Finished May 14 01:15:04 PM PDT 24
Peak memory 197900 kb
Host smart-c2a9c2ba-cc73-4f09-b46c-edfc9e123706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057064714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1057064714
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.842634909
Short name T666
Test name
Test status
Simulation time 22098126 ps
CPU time 0.71 seconds
Started May 14 01:15:03 PM PDT 24
Finished May 14 01:15:06 PM PDT 24
Peak memory 194320 kb
Host smart-d29c5789-a96d-4846-996a-fc0154a337ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842634909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.842634909
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1317295756
Short name T422
Test name
Test status
Simulation time 160416322 ps
CPU time 3.14 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 198092 kb
Host smart-c95f0ddb-34a8-4b09-9ca9-0f62eaec0db0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317295756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1317295756
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.109220430
Short name T98
Test name
Test status
Simulation time 86532021 ps
CPU time 2.47 seconds
Started May 14 01:15:04 PM PDT 24
Finished May 14 01:15:09 PM PDT 24
Peak memory 197988 kb
Host smart-d97c311e-0a9c-4dd3-ac0b-6443ee7b2396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109220430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
109220430
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3101215885
Short name T496
Test name
Test status
Simulation time 256939124 ps
CPU time 1.37 seconds
Started May 14 01:15:11 PM PDT 24
Finished May 14 01:15:15 PM PDT 24
Peak memory 198056 kb
Host smart-033420eb-041f-4678-a030-0e76a98cf1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101215885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3101215885
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2057710149
Short name T143
Test name
Test status
Simulation time 56122380 ps
CPU time 0.9 seconds
Started May 14 01:15:09 PM PDT 24
Finished May 14 01:15:14 PM PDT 24
Peak memory 196616 kb
Host smart-987f16e4-9afd-41d2-89e5-bde5f10ffb67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057710149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2057710149
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3410561755
Short name T229
Test name
Test status
Simulation time 477632104 ps
CPU time 5.49 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:16 PM PDT 24
Peak memory 198160 kb
Host smart-105ce376-badd-4eba-80fb-fc1fcc8e44b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410561755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3410561755
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.397160891
Short name T55
Test name
Test status
Simulation time 68604998 ps
CPU time 1.27 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 196540 kb
Host smart-9252fa5f-411c-4787-80d9-40027fbb7d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397160891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.397160891
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2520559843
Short name T23
Test name
Test status
Simulation time 52531240 ps
CPU time 1.2 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 195616 kb
Host smart-1989a300-6b06-43a0-865e-2833d114800e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520559843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2520559843
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1845987545
Short name T352
Test name
Test status
Simulation time 24260651719 ps
CPU time 157.91 seconds
Started May 14 01:15:01 PM PDT 24
Finished May 14 01:17:41 PM PDT 24
Peak memory 198092 kb
Host smart-9e4a24bc-b14c-4ecb-8991-73b95c80a416
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845987545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1845987545
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1501721083
Short name T547
Test name
Test status
Simulation time 65673406814 ps
CPU time 223.53 seconds
Started May 14 01:15:22 PM PDT 24
Finished May 14 01:19:06 PM PDT 24
Peak memory 198220 kb
Host smart-a4d07bce-6fb1-49cd-8850-ac352503f06e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1501721083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1501721083
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1139694285
Short name T493
Test name
Test status
Simulation time 14937526 ps
CPU time 0.57 seconds
Started May 14 01:15:10 PM PDT 24
Finished May 14 01:15:14 PM PDT 24
Peak memory 194568 kb
Host smart-420290a9-3394-444c-9380-64d001c361cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139694285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1139694285
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.937238660
Short name T180
Test name
Test status
Simulation time 113443400 ps
CPU time 0.91 seconds
Started May 14 01:14:57 PM PDT 24
Finished May 14 01:15:01 PM PDT 24
Peak memory 196484 kb
Host smart-bf221524-c96c-4573-9245-7641675798bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937238660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.937238660
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3903756081
Short name T279
Test name
Test status
Simulation time 476828383 ps
CPU time 4.88 seconds
Started May 14 01:15:00 PM PDT 24
Finished May 14 01:15:07 PM PDT 24
Peak memory 195644 kb
Host smart-bc84848e-dc46-4e4f-a68d-66dc9776996c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903756081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3903756081
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.1111180568
Short name T181
Test name
Test status
Simulation time 127253644 ps
CPU time 0.8 seconds
Started May 14 01:15:11 PM PDT 24
Finished May 14 01:15:15 PM PDT 24
Peak memory 196112 kb
Host smart-77952f30-ca79-440c-b130-0d156be22eaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111180568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.1111180568
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.831945800
Short name T592
Test name
Test status
Simulation time 109570135 ps
CPU time 0.95 seconds
Started May 14 01:15:14 PM PDT 24
Finished May 14 01:15:18 PM PDT 24
Peak memory 196076 kb
Host smart-10c4ac09-7f57-454e-9e00-dbc156251eb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831945800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.831945800
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3793689508
Short name T588
Test name
Test status
Simulation time 354538424 ps
CPU time 3.42 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 197996 kb
Host smart-3d0c3d17-5b47-483d-a6b7-c9a3bff79590
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793689508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3793689508
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3326217623
Short name T495
Test name
Test status
Simulation time 485338704 ps
CPU time 1.87 seconds
Started May 14 01:15:04 PM PDT 24
Finished May 14 01:15:09 PM PDT 24
Peak memory 195780 kb
Host smart-6caaf8c3-cd58-4a7d-8f24-5f5b4e10caaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326217623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3326217623
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3754463154
Short name T638
Test name
Test status
Simulation time 130136925 ps
CPU time 0.92 seconds
Started May 14 01:15:00 PM PDT 24
Finished May 14 01:15:03 PM PDT 24
Peak memory 195960 kb
Host smart-2a3df129-4ceb-4643-b612-5790d13ba121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754463154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3754463154
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2216366389
Short name T604
Test name
Test status
Simulation time 125621984 ps
CPU time 1.29 seconds
Started May 14 01:15:01 PM PDT 24
Finished May 14 01:15:04 PM PDT 24
Peak memory 195784 kb
Host smart-7d9b09e0-f509-416f-b159-8758687cf941
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216366389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2216366389
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.721513863
Short name T273
Test name
Test status
Simulation time 931030955 ps
CPU time 5.7 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:15:13 PM PDT 24
Peak memory 197996 kb
Host smart-e8c02c38-2865-4268-86da-eb176fe9433a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721513863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.721513863
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3792967263
Short name T171
Test name
Test status
Simulation time 268988254 ps
CPU time 1.2 seconds
Started May 14 01:15:02 PM PDT 24
Finished May 14 01:15:06 PM PDT 24
Peak memory 196220 kb
Host smart-757ab2c9-e552-45ea-8e58-513fb8e630f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792967263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3792967263
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.4207124284
Short name T147
Test name
Test status
Simulation time 170484266 ps
CPU time 1.02 seconds
Started May 14 01:15:19 PM PDT 24
Finished May 14 01:15:21 PM PDT 24
Peak memory 195764 kb
Host smart-635cfd2e-dab5-43d1-8b44-d50b75c40caf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207124284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.4207124284
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2745759945
Short name T222
Test name
Test status
Simulation time 22489851228 ps
CPU time 63.81 seconds
Started May 14 01:15:09 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 198196 kb
Host smart-bbf1878a-208b-45b7-b4c2-789b87954ade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745759945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2745759945
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1591735620
Short name T490
Test name
Test status
Simulation time 49760267 ps
CPU time 0.6 seconds
Started May 14 01:15:03 PM PDT 24
Finished May 14 01:15:06 PM PDT 24
Peak memory 193936 kb
Host smart-166731c4-13b2-4a3a-a316-9b8b771ab0fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591735620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1591735620
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1088169613
Short name T127
Test name
Test status
Simulation time 37065877 ps
CPU time 0.73 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:15:08 PM PDT 24
Peak memory 195976 kb
Host smart-eced3db8-b008-4c5a-9a13-439f5da42623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088169613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1088169613
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2604066536
Short name T521
Test name
Test status
Simulation time 497137508 ps
CPU time 26.23 seconds
Started May 14 01:15:11 PM PDT 24
Finished May 14 01:15:40 PM PDT 24
Peak memory 196272 kb
Host smart-8eadf0f0-3f55-4a9e-b7fd-bf3c9e3137fd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604066536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2604066536
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.299318230
Short name T427
Test name
Test status
Simulation time 381331295 ps
CPU time 1 seconds
Started May 14 01:15:13 PM PDT 24
Finished May 14 01:15:17 PM PDT 24
Peak memory 197736 kb
Host smart-30e8dff0-5a1a-4c67-b919-4f920f6b207c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299318230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.299318230
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.585791888
Short name T259
Test name
Test status
Simulation time 285896436 ps
CPU time 1.18 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:15:12 PM PDT 24
Peak memory 196012 kb
Host smart-0e9703c9-74c3-4215-832f-0b37d893c8f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585791888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.585791888
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.128684848
Short name T695
Test name
Test status
Simulation time 80594523 ps
CPU time 3.07 seconds
Started May 14 01:15:02 PM PDT 24
Finished May 14 01:15:08 PM PDT 24
Peak memory 198024 kb
Host smart-f6e04bfc-3aed-423e-9656-2694b2f006a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128684848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.128684848
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1200935105
Short name T102
Test name
Test status
Simulation time 110218166 ps
CPU time 1 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 195640 kb
Host smart-102136b3-b375-4f1d-8b89-90870a5cd261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200935105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1200935105
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1060377180
Short name T555
Test name
Test status
Simulation time 92263805 ps
CPU time 1.04 seconds
Started May 14 01:15:02 PM PDT 24
Finished May 14 01:15:06 PM PDT 24
Peak memory 195840 kb
Host smart-3f94223e-8fbc-432e-8dac-c8854fe6da11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060377180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1060377180
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3014136911
Short name T197
Test name
Test status
Simulation time 42290544 ps
CPU time 1.03 seconds
Started May 14 01:15:04 PM PDT 24
Finished May 14 01:15:08 PM PDT 24
Peak memory 196660 kb
Host smart-2a012745-a8ae-427d-9e4f-f24695d54292
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014136911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3014136911
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2836465874
Short name T177
Test name
Test status
Simulation time 275314087 ps
CPU time 4.33 seconds
Started May 14 01:15:03 PM PDT 24
Finished May 14 01:15:10 PM PDT 24
Peak memory 197876 kb
Host smart-ee882327-f284-4c4c-a1bc-ad71cc65e0e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836465874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2836465874
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3597215285
Short name T154
Test name
Test status
Simulation time 500101664 ps
CPU time 1.35 seconds
Started May 14 01:15:06 PM PDT 24
Finished May 14 01:15:10 PM PDT 24
Peak memory 196816 kb
Host smart-f5aaccb3-b8a3-4679-8c15-7b17ff5de379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597215285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3597215285
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1018994117
Short name T469
Test name
Test status
Simulation time 45807464 ps
CPU time 0.93 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 196504 kb
Host smart-b8e23f36-8248-4407-b79e-e14c23d370e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018994117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1018994117
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3861188503
Short name T628
Test name
Test status
Simulation time 3710419441 ps
CPU time 91.76 seconds
Started May 14 01:15:00 PM PDT 24
Finished May 14 01:16:34 PM PDT 24
Peak memory 198184 kb
Host smart-9156f4fe-725b-40c2-9196-e766963e57ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861188503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3861188503
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1786101368
Short name T261
Test name
Test status
Simulation time 74716624 ps
CPU time 0.6 seconds
Started May 14 01:15:28 PM PDT 24
Finished May 14 01:15:30 PM PDT 24
Peak memory 194572 kb
Host smart-0a5a68e5-7288-4d84-90e2-6d2d8adcb68e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786101368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1786101368
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.2372725683
Short name T629
Test name
Test status
Simulation time 54881377 ps
CPU time 0.62 seconds
Started May 14 01:15:09 PM PDT 24
Finished May 14 01:15:13 PM PDT 24
Peak memory 194756 kb
Host smart-f289b5c3-ad7c-4049-bb96-fdf86dea4898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372725683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.2372725683
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4049810712
Short name T163
Test name
Test status
Simulation time 262561769 ps
CPU time 13.5 seconds
Started May 14 01:15:31 PM PDT 24
Finished May 14 01:15:46 PM PDT 24
Peak memory 197912 kb
Host smart-da493ec4-d1d8-47c6-8be7-0e425776a311
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049810712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4049810712
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2682054300
Short name T610
Test name
Test status
Simulation time 572646818 ps
CPU time 0.74 seconds
Started May 14 01:15:23 PM PDT 24
Finished May 14 01:15:25 PM PDT 24
Peak memory 195804 kb
Host smart-2e3834ca-0397-464d-803a-f3bcb6f931f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682054300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2682054300
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1263134327
Short name T419
Test name
Test status
Simulation time 192734385 ps
CPU time 1.22 seconds
Started May 14 01:15:02 PM PDT 24
Finished May 14 01:15:05 PM PDT 24
Peak memory 197208 kb
Host smart-a0d3fe20-b2da-4d82-9f4f-44991123c9d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263134327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1263134327
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2180053272
Short name T278
Test name
Test status
Simulation time 75788809 ps
CPU time 2.93 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:15:10 PM PDT 24
Peak memory 198084 kb
Host smart-2138c7a4-6828-40de-b3a3-75736c643842
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180053272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2180053272
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1862825431
Short name T372
Test name
Test status
Simulation time 114304351 ps
CPU time 1.42 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 196116 kb
Host smart-618eabf1-e284-4bb7-a232-0ed5e6d41767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862825431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1862825431
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1117286002
Short name T603
Test name
Test status
Simulation time 34991750 ps
CPU time 1.38 seconds
Started May 14 01:15:19 PM PDT 24
Finished May 14 01:15:22 PM PDT 24
Peak memory 197084 kb
Host smart-5e420ef0-e08d-41e6-ac07-0fcf4f1466da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117286002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1117286002
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1179334857
Short name T397
Test name
Test status
Simulation time 58919355 ps
CPU time 0.83 seconds
Started May 14 01:15:06 PM PDT 24
Finished May 14 01:15:10 PM PDT 24
Peak memory 196444 kb
Host smart-5708feef-89a5-427f-b2cf-9758006efb2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179334857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1179334857
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3627701243
Short name T567
Test name
Test status
Simulation time 458516862 ps
CPU time 2.21 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:20 PM PDT 24
Peak memory 197624 kb
Host smart-d750bc38-fb93-4a2c-a502-c94b1ed814e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627701243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3627701243
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3455070762
Short name T292
Test name
Test status
Simulation time 29070134 ps
CPU time 0.79 seconds
Started May 14 01:15:12 PM PDT 24
Finished May 14 01:15:16 PM PDT 24
Peak memory 195244 kb
Host smart-00833e5a-c151-4fec-8d63-c0e894fcfa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455070762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3455070762
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.593784273
Short name T644
Test name
Test status
Simulation time 60934422 ps
CPU time 1.06 seconds
Started May 14 01:15:11 PM PDT 24
Finished May 14 01:15:15 PM PDT 24
Peak memory 195488 kb
Host smart-016784bc-6b5d-4f7d-ab05-828ded80ff87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593784273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.593784273
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3046789969
Short name T627
Test name
Test status
Simulation time 13080702966 ps
CPU time 142.43 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:17:34 PM PDT 24
Peak memory 198212 kb
Host smart-41819e45-b447-41e8-a15f-dbf466ce90ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046789969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3046789969
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3533572873
Short name T345
Test name
Test status
Simulation time 16031214 ps
CPU time 0.62 seconds
Started May 14 01:15:06 PM PDT 24
Finished May 14 01:15:10 PM PDT 24
Peak memory 195048 kb
Host smart-e8988979-c2d4-4faf-b4e2-8e8ba5d98189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533572873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3533572873
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3711354715
Short name T641
Test name
Test status
Simulation time 31649945 ps
CPU time 0.94 seconds
Started May 14 01:15:09 PM PDT 24
Finished May 14 01:15:14 PM PDT 24
Peak memory 195664 kb
Host smart-1d2ab2a1-9dd0-43d6-ba29-4a6a4128c87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711354715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3711354715
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3936084691
Short name T332
Test name
Test status
Simulation time 539703493 ps
CPU time 27.29 seconds
Started May 14 01:15:13 PM PDT 24
Finished May 14 01:15:43 PM PDT 24
Peak memory 195500 kb
Host smart-ad4c5db3-a481-4566-9106-00cd5a933690
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936084691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3936084691
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3551522060
Short name T579
Test name
Test status
Simulation time 86188709 ps
CPU time 1.1 seconds
Started May 14 01:15:06 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 196656 kb
Host smart-29b9494e-88dc-4f0b-aa61-ea0bebe706e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551522060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3551522060
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1617386006
Short name T216
Test name
Test status
Simulation time 53787683 ps
CPU time 0.93 seconds
Started May 14 01:15:06 PM PDT 24
Finished May 14 01:15:10 PM PDT 24
Peak memory 196544 kb
Host smart-5d668351-26d3-433b-8863-4a238ce12d1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617386006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1617386006
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2060421131
Short name T673
Test name
Test status
Simulation time 40376323 ps
CPU time 1.67 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:12 PM PDT 24
Peak memory 196756 kb
Host smart-32141fb7-baff-4169-9f55-a4520aa3e585
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060421131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2060421131
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.4191053939
Short name T686
Test name
Test status
Simulation time 116110667 ps
CPU time 2.43 seconds
Started May 14 01:15:14 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 196472 kb
Host smart-755edf32-9d56-44fb-81c2-f337acc4b322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191053939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.4191053939
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3684344299
Short name T317
Test name
Test status
Simulation time 184255778 ps
CPU time 0.72 seconds
Started May 14 01:15:18 PM PDT 24
Finished May 14 01:15:21 PM PDT 24
Peak memory 195448 kb
Host smart-6111f9d0-596d-488d-8bc4-3f9ee9a1c326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684344299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3684344299
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3003195500
Short name T24
Test name
Test status
Simulation time 107089494 ps
CPU time 1.21 seconds
Started May 14 01:15:09 PM PDT 24
Finished May 14 01:15:14 PM PDT 24
Peak memory 196904 kb
Host smart-d1316a47-fec8-4ae4-8f08-09a29e0a7167
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003195500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3003195500
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_smoke.1619043435
Short name T324
Test name
Test status
Simulation time 660309647 ps
CPU time 1.15 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:15:13 PM PDT 24
Peak memory 195684 kb
Host smart-9c02e8fe-a92f-457d-a217-2dc6f794f37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619043435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1619043435
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.954995642
Short name T206
Test name
Test status
Simulation time 138832488 ps
CPU time 1.1 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:15:12 PM PDT 24
Peak memory 195724 kb
Host smart-90d98aac-651e-4dec-8ff6-65bdd5a2dfaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954995642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.954995642
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2943438735
Short name T142
Test name
Test status
Simulation time 12077030845 ps
CPU time 78.6 seconds
Started May 14 01:15:11 PM PDT 24
Finished May 14 01:16:33 PM PDT 24
Peak memory 198180 kb
Host smart-c216b1e3-3b2c-4193-ba7f-f5ed4d6204f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943438735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2943438735
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3855941748
Short name T556
Test name
Test status
Simulation time 30053892 ps
CPU time 0.53 seconds
Started May 14 01:15:06 PM PDT 24
Finished May 14 01:15:09 PM PDT 24
Peak memory 193908 kb
Host smart-e953d5a7-883c-443e-9ea2-56ab75d5ca12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855941748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3855941748
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1249271339
Short name T691
Test name
Test status
Simulation time 102801449 ps
CPU time 0.7 seconds
Started May 14 01:15:14 PM PDT 24
Finished May 14 01:15:18 PM PDT 24
Peak memory 194132 kb
Host smart-b035317e-092b-4ac4-a16d-e1a5de806bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249271339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1249271339
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2585331820
Short name T525
Test name
Test status
Simulation time 288191917 ps
CPU time 8.88 seconds
Started May 14 01:15:10 PM PDT 24
Finished May 14 01:15:22 PM PDT 24
Peak memory 196760 kb
Host smart-79cc05ee-cbbc-44af-9a89-5bf9b2c542e3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585331820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2585331820
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1078839423
Short name T121
Test name
Test status
Simulation time 47176637 ps
CPU time 0.67 seconds
Started May 14 01:15:22 PM PDT 24
Finished May 14 01:15:23 PM PDT 24
Peak memory 194708 kb
Host smart-9772297d-bb0d-4eee-8d5e-efffcb904678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078839423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1078839423
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1807327411
Short name T451
Test name
Test status
Simulation time 92376061 ps
CPU time 0.89 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:11 PM PDT 24
Peak memory 196544 kb
Host smart-adba87b6-32f7-4d41-8125-79974c93850e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807327411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1807327411
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1402025420
Short name T482
Test name
Test status
Simulation time 128397341 ps
CPU time 2.32 seconds
Started May 14 01:15:10 PM PDT 24
Finished May 14 01:15:15 PM PDT 24
Peak memory 197012 kb
Host smart-5013e999-c150-43a8-be72-a00d69c75c98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402025420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1402025420
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3320129480
Short name T580
Test name
Test status
Simulation time 50417862 ps
CPU time 1.03 seconds
Started May 14 01:15:35 PM PDT 24
Finished May 14 01:15:38 PM PDT 24
Peak memory 196664 kb
Host smart-93783252-dc41-488d-bfb9-c6175970e378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320129480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3320129480
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1036390279
Short name T281
Test name
Test status
Simulation time 50041402 ps
CPU time 0.64 seconds
Started May 14 01:15:35 PM PDT 24
Finished May 14 01:15:38 PM PDT 24
Peak memory 194296 kb
Host smart-c14a34a3-e529-47d2-87af-6daf708ec3f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036390279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1036390279
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1618040109
Short name T501
Test name
Test status
Simulation time 576791040 ps
CPU time 2.07 seconds
Started May 14 01:15:40 PM PDT 24
Finished May 14 01:15:45 PM PDT 24
Peak memory 197940 kb
Host smart-239df079-1106-459c-8a30-ff64ebd3355a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618040109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1618040109
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3170300712
Short name T594
Test name
Test status
Simulation time 118400618 ps
CPU time 1.5 seconds
Started May 14 01:15:30 PM PDT 24
Finished May 14 01:15:34 PM PDT 24
Peak memory 196760 kb
Host smart-2de209a4-c2b4-404b-b019-b944b74f912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170300712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3170300712
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1804854134
Short name T172
Test name
Test status
Simulation time 212383624 ps
CPU time 1.11 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 195760 kb
Host smart-cc3a1f26-7204-4a24-99a6-3aafd885ddd9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804854134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1804854134
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.840753043
Short name T571
Test name
Test status
Simulation time 57294071848 ps
CPU time 199.14 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:18:37 PM PDT 24
Peak memory 198156 kb
Host smart-73fbb61f-a119-4326-ac8a-55dd4f7945b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840753043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.840753043
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.194405347
Short name T285
Test name
Test status
Simulation time 55268999 ps
CPU time 0.58 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 194744 kb
Host smart-5ea48335-388b-43be-b0e2-980ca0f39a7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194405347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.194405347
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.73527095
Short name T295
Test name
Test status
Simulation time 172462134 ps
CPU time 0.76 seconds
Started May 14 01:14:37 PM PDT 24
Finished May 14 01:14:40 PM PDT 24
Peak memory 195260 kb
Host smart-ad427a63-554f-4c19-b4bf-eaa72822ed57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73527095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.73527095
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1450136366
Short name T157
Test name
Test status
Simulation time 1260957972 ps
CPU time 15.76 seconds
Started May 14 01:14:39 PM PDT 24
Finished May 14 01:14:57 PM PDT 24
Peak memory 196712 kb
Host smart-392552b8-760e-4399-9dee-2e1791490579
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450136366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1450136366
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2435835904
Short name T49
Test name
Test status
Simulation time 141340371 ps
CPU time 0.81 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 196744 kb
Host smart-8262133d-71b8-4102-a21f-9b0c5a4f0c64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435835904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2435835904
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3213159078
Short name T300
Test name
Test status
Simulation time 102107685 ps
CPU time 0.74 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:37 PM PDT 24
Peak memory 194404 kb
Host smart-4310047f-9cd3-4219-b8a8-eaba5075130e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213159078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3213159078
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4234023334
Short name T442
Test name
Test status
Simulation time 250498105 ps
CPU time 2.73 seconds
Started May 14 01:14:42 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 198084 kb
Host smart-6c8dda1d-2368-4fc1-aacf-9d805e1754e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234023334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.4234023334
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.919228823
Short name T412
Test name
Test status
Simulation time 127104142 ps
CPU time 1.07 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 195488 kb
Host smart-d7ff32b3-fc9a-49b5-83ef-e7d2718711f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919228823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.919228823
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.4058211873
Short name T57
Test name
Test status
Simulation time 67309224 ps
CPU time 0.92 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 197364 kb
Host smart-c5857bd9-f68e-49c2-8ed1-41be53fbd1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058211873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.4058211873
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1823458755
Short name T420
Test name
Test status
Simulation time 66004080 ps
CPU time 0.91 seconds
Started May 14 01:14:36 PM PDT 24
Finished May 14 01:14:39 PM PDT 24
Peak memory 196568 kb
Host smart-c2003ccb-2b96-465d-93e5-55dae671fc3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823458755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1823458755
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.624581720
Short name T148
Test name
Test status
Simulation time 315285031 ps
CPU time 5.01 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:58 PM PDT 24
Peak memory 197948 kb
Host smart-dce5b32d-d849-4cf8-bf3b-3f8f91345e83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624581720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.624581720
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.867051849
Short name T38
Test name
Test status
Simulation time 228072548 ps
CPU time 0.85 seconds
Started May 14 01:14:44 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 213860 kb
Host smart-8de4b29a-b3fb-4c2e-be56-0cfa6de09381
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867051849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.867051849
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1932805219
Short name T363
Test name
Test status
Simulation time 97166421 ps
CPU time 0.89 seconds
Started May 14 01:14:37 PM PDT 24
Finished May 14 01:14:40 PM PDT 24
Peak memory 196164 kb
Host smart-e5f81448-d431-4fa9-aa25-6ce5600e4529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932805219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1932805219
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.946857232
Short name T65
Test name
Test status
Simulation time 103728126 ps
CPU time 0.92 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:50 PM PDT 24
Peak memory 196460 kb
Host smart-4d7fc12d-eae0-40ca-a2b9-5e7d9899d5ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946857232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.946857232
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3095558265
Short name T168
Test name
Test status
Simulation time 19917584320 ps
CPU time 127.23 seconds
Started May 14 01:14:44 PM PDT 24
Finished May 14 01:16:53 PM PDT 24
Peak memory 198188 kb
Host smart-2491fe71-9e4c-4a7b-9445-52432fd9b160
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095558265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3095558265
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1671746978
Short name T445
Test name
Test status
Simulation time 29164137 ps
CPU time 0.57 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:15:12 PM PDT 24
Peak memory 194572 kb
Host smart-1fa8a91a-5c46-44f0-8e83-47d3952a65a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671746978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1671746978
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.323401874
Short name T550
Test name
Test status
Simulation time 27617281 ps
CPU time 0.8 seconds
Started May 14 01:15:27 PM PDT 24
Finished May 14 01:15:29 PM PDT 24
Peak memory 195496 kb
Host smart-99adae6a-4c56-4fad-a7d2-ff889188f651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323401874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.323401874
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2858072979
Short name T511
Test name
Test status
Simulation time 1065133158 ps
CPU time 16.41 seconds
Started May 14 01:15:13 PM PDT 24
Finished May 14 01:15:32 PM PDT 24
Peak memory 197976 kb
Host smart-16d5321d-f4ff-4b7a-b806-07c05f441572
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858072979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2858072979
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1186139313
Short name T523
Test name
Test status
Simulation time 27433476 ps
CPU time 0.65 seconds
Started May 14 01:15:17 PM PDT 24
Finished May 14 01:15:20 PM PDT 24
Peak memory 194600 kb
Host smart-e00d0318-af18-4c2d-8776-dc7d9fb2dfa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186139313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1186139313
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1596384930
Short name T452
Test name
Test status
Simulation time 280577181 ps
CPU time 1.22 seconds
Started May 14 01:15:26 PM PDT 24
Finished May 14 01:15:28 PM PDT 24
Peak memory 196772 kb
Host smart-12af2a37-c69b-45ef-b905-ad17414bce94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596384930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1596384930
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.851972309
Short name T109
Test name
Test status
Simulation time 47873607 ps
CPU time 2.08 seconds
Started May 14 01:15:25 PM PDT 24
Finished May 14 01:15:27 PM PDT 24
Peak memory 197964 kb
Host smart-4e228083-bc1b-43dd-b131-8ef02de462ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851972309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.851972309
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1359178552
Short name T698
Test name
Test status
Simulation time 542321519 ps
CPU time 2.99 seconds
Started May 14 01:15:07 PM PDT 24
Finished May 14 01:15:13 PM PDT 24
Peak memory 196744 kb
Host smart-dbe7f0f0-b763-4291-afc5-c04cf6ff2512
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359178552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1359178552
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3595686489
Short name T473
Test name
Test status
Simulation time 14544651 ps
CPU time 0.69 seconds
Started May 14 01:15:23 PM PDT 24
Finished May 14 01:15:25 PM PDT 24
Peak memory 194308 kb
Host smart-8eb09edf-cdd9-48ce-a5e0-069bfa789803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595686489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3595686489
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.703258671
Short name T173
Test name
Test status
Simulation time 56244537 ps
CPU time 1.1 seconds
Started May 14 01:15:26 PM PDT 24
Finished May 14 01:15:29 PM PDT 24
Peak memory 196056 kb
Host smart-88aa137b-b196-41c0-b86e-e6c980132da0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703258671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.703258671
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.497142418
Short name T212
Test name
Test status
Simulation time 210252250 ps
CPU time 3.27 seconds
Started May 14 01:15:06 PM PDT 24
Finished May 14 01:15:13 PM PDT 24
Peak memory 197956 kb
Host smart-22d749a4-4a23-4feb-9ed2-15a6f1863608
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497142418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.497142418
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2615744674
Short name T434
Test name
Test status
Simulation time 86513731 ps
CPU time 0.95 seconds
Started May 14 01:15:37 PM PDT 24
Finished May 14 01:15:41 PM PDT 24
Peak memory 195568 kb
Host smart-f6dfe007-c577-4d03-b0b4-ea6a909efbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615744674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2615744674
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1043222072
Short name T479
Test name
Test status
Simulation time 43787456 ps
CPU time 0.91 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:15:12 PM PDT 24
Peak memory 196344 kb
Host smart-ed09bbad-ac9a-45bf-bee4-f2e9a999486c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043222072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1043222072
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2053783878
Short name T314
Test name
Test status
Simulation time 29763843469 ps
CPU time 97.1 seconds
Started May 14 01:15:09 PM PDT 24
Finished May 14 01:16:49 PM PDT 24
Peak memory 198084 kb
Host smart-b84a27e7-3a3d-48cd-9a5a-890ecd2d80a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053783878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2053783878
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.696778833
Short name T58
Test name
Test status
Simulation time 39278687671 ps
CPU time 993.57 seconds
Started May 14 01:15:13 PM PDT 24
Finished May 14 01:31:50 PM PDT 24
Peak memory 198212 kb
Host smart-6f501ce1-908c-43b2-ab06-936cb1f2614b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=696778833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.696778833
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1137191367
Short name T367
Test name
Test status
Simulation time 113556766 ps
CPU time 0.58 seconds
Started May 14 01:15:12 PM PDT 24
Finished May 14 01:15:15 PM PDT 24
Peak memory 194544 kb
Host smart-db4e7549-2e61-49e4-80b7-665dd4500b40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137191367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1137191367
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3284637292
Short name T537
Test name
Test status
Simulation time 103195645 ps
CPU time 0.94 seconds
Started May 14 01:15:12 PM PDT 24
Finished May 14 01:15:16 PM PDT 24
Peak memory 195956 kb
Host smart-b14d19b6-8404-4630-8b67-f086b0ed5101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284637292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3284637292
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2719711617
Short name T676
Test name
Test status
Simulation time 591099445 ps
CPU time 19.42 seconds
Started May 14 01:15:13 PM PDT 24
Finished May 14 01:15:36 PM PDT 24
Peak memory 196756 kb
Host smart-1f3c55d8-d50b-40c5-8223-860a3b034433
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719711617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2719711617
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.976419992
Short name T518
Test name
Test status
Simulation time 95848685 ps
CPU time 1.11 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:15:12 PM PDT 24
Peak memory 196480 kb
Host smart-1c7bea35-4a8b-4401-bb54-3f4ecef6fed0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976419992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.976419992
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1536701943
Short name T500
Test name
Test status
Simulation time 33877068 ps
CPU time 1.09 seconds
Started May 14 01:15:21 PM PDT 24
Finished May 14 01:15:23 PM PDT 24
Peak memory 196760 kb
Host smart-1dd83800-71c2-444e-8512-e8ea97608b12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536701943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1536701943
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2271021444
Short name T456
Test name
Test status
Simulation time 499517732 ps
CPU time 3.18 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:21 PM PDT 24
Peak memory 198048 kb
Host smart-8e7ae506-b82f-4498-860b-d68ab7a21add
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271021444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2271021444
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1056662918
Short name T311
Test name
Test status
Simulation time 46606473 ps
CPU time 1.49 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:15:14 PM PDT 24
Peak memory 196744 kb
Host smart-17f0b181-864c-4f8d-b89f-8663720d2116
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056662918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1056662918
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1116087440
Short name T403
Test name
Test status
Simulation time 57897269 ps
CPU time 0.87 seconds
Started May 14 01:15:08 PM PDT 24
Finished May 14 01:15:12 PM PDT 24
Peak memory 195884 kb
Host smart-4b7828b4-5661-438a-8a2f-0e7a2807488c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116087440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1116087440
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3151859222
Short name T31
Test name
Test status
Simulation time 40449560 ps
CPU time 0.81 seconds
Started May 14 01:15:30 PM PDT 24
Finished May 14 01:15:33 PM PDT 24
Peak memory 195368 kb
Host smart-85775e36-0d23-404e-9721-29e878e4f791
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151859222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3151859222
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2431959589
Short name T9
Test name
Test status
Simulation time 399389502 ps
CPU time 1.52 seconds
Started May 14 01:15:35 PM PDT 24
Finished May 14 01:15:38 PM PDT 24
Peak memory 197964 kb
Host smart-eb664c01-ad99-4888-bdbb-861380a367cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431959589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2431959589
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.4189836688
Short name T643
Test name
Test status
Simulation time 76025401 ps
CPU time 1.39 seconds
Started May 14 01:15:14 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 197928 kb
Host smart-6f4ad10d-d7b9-46a2-9726-df776a5c4290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189836688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.4189836688
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.87718580
Short name T600
Test name
Test status
Simulation time 48754867 ps
CPU time 0.91 seconds
Started May 14 01:15:26 PM PDT 24
Finished May 14 01:15:28 PM PDT 24
Peak memory 197008 kb
Host smart-63db1b74-9ec4-49d1-874f-0de7d4251892
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87718580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.87718580
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2627542965
Short name T97
Test name
Test status
Simulation time 12865527010 ps
CPU time 180.88 seconds
Started May 14 01:15:37 PM PDT 24
Finished May 14 01:18:40 PM PDT 24
Peak memory 198136 kb
Host smart-7cadc23d-c4f0-47ea-8e45-4234cec6b9cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627542965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2627542965
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1381048124
Short name T60
Test name
Test status
Simulation time 104097499255 ps
CPU time 562.18 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:24:40 PM PDT 24
Peak memory 198188 kb
Host smart-e681cf5e-24fb-4768-b73d-34b034976149
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1381048124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1381048124
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.936563393
Short name T29
Test name
Test status
Simulation time 28328572 ps
CPU time 0.59 seconds
Started May 14 01:15:30 PM PDT 24
Finished May 14 01:15:32 PM PDT 24
Peak memory 193856 kb
Host smart-4e7c971f-f65a-44d6-a810-b2f2cb04f23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936563393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.936563393
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2316172584
Short name T218
Test name
Test status
Simulation time 25117573 ps
CPU time 0.69 seconds
Started May 14 01:15:27 PM PDT 24
Finished May 14 01:15:29 PM PDT 24
Peak memory 194180 kb
Host smart-1704e725-d8d1-4518-bcd2-8d508dbb074f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316172584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2316172584
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1913078131
Short name T658
Test name
Test status
Simulation time 632484786 ps
CPU time 17.05 seconds
Started May 14 01:15:37 PM PDT 24
Finished May 14 01:15:56 PM PDT 24
Peak memory 197080 kb
Host smart-293d2139-d3f1-4ea9-ba03-d10be9d81d7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913078131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1913078131
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1028027405
Short name T595
Test name
Test status
Simulation time 302105157 ps
CPU time 1.1 seconds
Started May 14 01:15:20 PM PDT 24
Finished May 14 01:15:22 PM PDT 24
Peak memory 196664 kb
Host smart-90d11202-b9a5-494e-81b7-ddb174ae7592
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028027405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1028027405
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3384380595
Short name T444
Test name
Test status
Simulation time 276650366 ps
CPU time 1.38 seconds
Started May 14 01:15:26 PM PDT 24
Finished May 14 01:15:28 PM PDT 24
Peak memory 196796 kb
Host smart-1925d52b-27b1-440f-986a-613f0cee812b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384380595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3384380595
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.613091722
Short name T108
Test name
Test status
Simulation time 329027121 ps
CPU time 3.15 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:15:41 PM PDT 24
Peak memory 198028 kb
Host smart-b018c23f-cbb6-41cc-a66f-e8ac8138f375
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613091722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.613091722
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3535146236
Short name T431
Test name
Test status
Simulation time 59535352 ps
CPU time 1.12 seconds
Started May 14 01:15:37 PM PDT 24
Finished May 14 01:15:41 PM PDT 24
Peak memory 196396 kb
Host smart-9cba4ef1-1382-45a4-9d11-1040d7fd4322
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535146236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3535146236
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1675318138
Short name T66
Test name
Test status
Simulation time 23300418 ps
CPU time 0.93 seconds
Started May 14 01:15:14 PM PDT 24
Finished May 14 01:15:18 PM PDT 24
Peak memory 196492 kb
Host smart-33d219a9-f650-4dcb-8e8c-40c7e97d9f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675318138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1675318138
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2659159888
Short name T139
Test name
Test status
Simulation time 18214552 ps
CPU time 0.75 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 195300 kb
Host smart-83775781-c51d-4dc3-b3d1-b09da6b85a6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659159888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2659159888
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3264104982
Short name T169
Test name
Test status
Simulation time 221631537 ps
CPU time 5.14 seconds
Started May 14 01:15:14 PM PDT 24
Finished May 14 01:15:22 PM PDT 24
Peak memory 198016 kb
Host smart-6fa9011d-4963-4b0f-9b45-26bb0e60c1dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264104982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3264104982
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1369031862
Short name T418
Test name
Test status
Simulation time 88300656 ps
CPU time 0.93 seconds
Started May 14 01:15:13 PM PDT 24
Finished May 14 01:15:17 PM PDT 24
Peak memory 196404 kb
Host smart-2acc7436-3c9d-4ed4-8360-5b3a7687f030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369031862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1369031862
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1991371525
Short name T574
Test name
Test status
Simulation time 35125790 ps
CPU time 0.76 seconds
Started May 14 01:15:20 PM PDT 24
Finished May 14 01:15:22 PM PDT 24
Peak memory 195228 kb
Host smart-c219dec1-08cf-40bd-8b95-518ba52015ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991371525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1991371525
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1745892212
Short name T583
Test name
Test status
Simulation time 64490482865 ps
CPU time 133.81 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:17:52 PM PDT 24
Peak memory 198196 kb
Host smart-bd566243-d2ff-491a-ba0a-35cdaad3e08e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745892212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1745892212
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2382067808
Short name T632
Test name
Test status
Simulation time 49831175172 ps
CPU time 725.99 seconds
Started May 14 01:15:16 PM PDT 24
Finished May 14 01:27:24 PM PDT 24
Peak memory 198220 kb
Host smart-7e41b65d-e3c3-402e-b095-f21ebbede245
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2382067808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2382067808
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.578946407
Short name T283
Test name
Test status
Simulation time 24601851 ps
CPU time 0.54 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:15:46 PM PDT 24
Peak memory 194600 kb
Host smart-ff4b7b51-7478-45b5-a907-fbfca758c6d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578946407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.578946407
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.752535741
Short name T396
Test name
Test status
Simulation time 117678478 ps
CPU time 0.9 seconds
Started May 14 01:15:17 PM PDT 24
Finished May 14 01:15:20 PM PDT 24
Peak memory 196752 kb
Host smart-c7eed38c-054c-4391-98c3-374c5593efdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752535741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.752535741
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3647403164
Short name T350
Test name
Test status
Simulation time 524440205 ps
CPU time 26.51 seconds
Started May 14 01:15:37 PM PDT 24
Finished May 14 01:16:07 PM PDT 24
Peak memory 196796 kb
Host smart-25d5284e-1779-4536-b712-fc659f079386
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647403164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3647403164
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1550114264
Short name T614
Test name
Test status
Simulation time 132057734 ps
CPU time 0.77 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 195620 kb
Host smart-f658dcd5-d586-4367-a729-3b3515cb4648
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550114264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1550114264
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3092243147
Short name T204
Test name
Test status
Simulation time 23779920 ps
CPU time 0.73 seconds
Started May 14 01:15:32 PM PDT 24
Finished May 14 01:15:35 PM PDT 24
Peak memory 195048 kb
Host smart-0b9e7128-fe30-4a97-9752-bd4323e56af7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092243147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3092243147
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3942928881
Short name T440
Test name
Test status
Simulation time 311067433 ps
CPU time 3.15 seconds
Started May 14 01:15:35 PM PDT 24
Finished May 14 01:15:41 PM PDT 24
Peak memory 198000 kb
Host smart-4bae8a6c-154d-4f40-b280-f619527b3f21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942928881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3942928881
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2927965104
Short name T201
Test name
Test status
Simulation time 301233486 ps
CPU time 2.3 seconds
Started May 14 01:15:16 PM PDT 24
Finished May 14 01:15:21 PM PDT 24
Peak memory 196984 kb
Host smart-fd86571a-8030-4ef8-ac7c-44070ce352c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927965104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2927965104
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2139267632
Short name T237
Test name
Test status
Simulation time 168860340 ps
CPU time 1.03 seconds
Started May 14 01:15:38 PM PDT 24
Finished May 14 01:15:43 PM PDT 24
Peak memory 196020 kb
Host smart-5019135a-36a4-421f-8696-3ce3cb014541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139267632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2139267632
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.594835811
Short name T392
Test name
Test status
Simulation time 33538198 ps
CPU time 0.75 seconds
Started May 14 01:15:14 PM PDT 24
Finished May 14 01:15:18 PM PDT 24
Peak memory 195388 kb
Host smart-60e0f212-ec3e-49df-bb16-8b07be8940aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594835811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.594835811
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3180336655
Short name T239
Test name
Test status
Simulation time 1269211885 ps
CPU time 5.04 seconds
Started May 14 01:15:31 PM PDT 24
Finished May 14 01:15:39 PM PDT 24
Peak memory 197904 kb
Host smart-b51612e6-ca68-41ce-afaf-4720f1f4ef01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180336655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3180336655
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.1247732427
Short name T436
Test name
Test status
Simulation time 347064196 ps
CPU time 1.5 seconds
Started May 14 01:15:16 PM PDT 24
Finished May 14 01:15:20 PM PDT 24
Peak memory 197960 kb
Host smart-6403e043-18f1-4639-8f37-fbd6fda8d872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247732427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.1247732427
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.912706331
Short name T140
Test name
Test status
Simulation time 63459437 ps
CPU time 1.06 seconds
Started May 14 01:15:18 PM PDT 24
Finished May 14 01:15:21 PM PDT 24
Peak memory 195804 kb
Host smart-e4373953-3b50-43bb-8ca8-49f72b951338
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912706331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.912706331
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1634811860
Short name T15
Test name
Test status
Simulation time 12946052604 ps
CPU time 167.14 seconds
Started May 14 01:15:19 PM PDT 24
Finished May 14 01:18:08 PM PDT 24
Peak memory 198152 kb
Host smart-6e070dbf-846e-4fe5-91e9-7f482d069485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634811860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1634811860
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3653129331
Short name T453
Test name
Test status
Simulation time 14133227 ps
CPU time 0.58 seconds
Started May 14 01:15:20 PM PDT 24
Finished May 14 01:15:22 PM PDT 24
Peak memory 193880 kb
Host smart-45f96e52-b746-446d-97e1-cfdc5c55c8c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653129331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3653129331
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2441405998
Short name T164
Test name
Test status
Simulation time 46432223 ps
CPU time 0.62 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:15:39 PM PDT 24
Peak memory 194752 kb
Host smart-e7f7d429-5276-412a-9162-c20bd90a263f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441405998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2441405998
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3759263915
Short name T124
Test name
Test status
Simulation time 1864907287 ps
CPU time 13 seconds
Started May 14 01:15:33 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 196916 kb
Host smart-a6de785e-fd3f-4876-a0d5-096e8e21bb87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759263915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3759263915
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1208428555
Short name T608
Test name
Test status
Simulation time 315885715 ps
CPU time 1.16 seconds
Started May 14 01:15:25 PM PDT 24
Finished May 14 01:15:27 PM PDT 24
Peak memory 197772 kb
Host smart-47295456-a43e-4f2c-b192-451122d3235e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208428555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1208428555
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.411122600
Short name T339
Test name
Test status
Simulation time 109656377 ps
CPU time 1.46 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 197028 kb
Host smart-78d78339-5657-4890-b8c6-9aaf45cd31fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411122600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.411122600
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2442963629
Short name T565
Test name
Test status
Simulation time 51781194 ps
CPU time 1.37 seconds
Started May 14 01:15:17 PM PDT 24
Finished May 14 01:15:20 PM PDT 24
Peak memory 196784 kb
Host smart-93e0d6e2-59e5-4922-a406-4ac4dfc15c90
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442963629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2442963629
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3382481845
Short name T219
Test name
Test status
Simulation time 361141001 ps
CPU time 2.86 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:15:41 PM PDT 24
Peak memory 198080 kb
Host smart-00dcdd1f-3353-4738-8ced-a02cff29f2e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382481845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3382481845
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1875205342
Short name T677
Test name
Test status
Simulation time 195271574 ps
CPU time 1.18 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 196960 kb
Host smart-26c6361e-d896-4d4e-98f1-ad404ccf0110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875205342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1875205342
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.469379085
Short name T467
Test name
Test status
Simulation time 45597698 ps
CPU time 0.67 seconds
Started May 14 01:15:32 PM PDT 24
Finished May 14 01:15:35 PM PDT 24
Peak memory 195380 kb
Host smart-5ace090e-fb75-4a3d-8888-444641020b21
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469379085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.469379085
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1985609880
Short name T126
Test name
Test status
Simulation time 522328808 ps
CPU time 3.27 seconds
Started May 14 01:15:19 PM PDT 24
Finished May 14 01:15:23 PM PDT 24
Peak memory 198028 kb
Host smart-caf89ef1-80bc-41ba-a99a-b578d96206cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985609880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1985609880
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2397670013
Short name T305
Test name
Test status
Simulation time 311738237 ps
CPU time 1.44 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:15:41 PM PDT 24
Peak memory 196336 kb
Host smart-659bc1c5-f545-4205-9cb6-a0a6319e59ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397670013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2397670013
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2592498259
Short name T338
Test name
Test status
Simulation time 121449974 ps
CPU time 0.94 seconds
Started May 14 01:15:23 PM PDT 24
Finished May 14 01:15:24 PM PDT 24
Peak memory 195284 kb
Host smart-b564de4e-a922-40c9-a0c1-bfdac5f6c97f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592498259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2592498259
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.642369515
Short name T612
Test name
Test status
Simulation time 13310038568 ps
CPU time 161.61 seconds
Started May 14 01:15:33 PM PDT 24
Finished May 14 01:18:17 PM PDT 24
Peak memory 198156 kb
Host smart-ab3d9b5e-835a-4a3e-a2ff-06f1e620736e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642369515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.642369515
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4193138419
Short name T668
Test name
Test status
Simulation time 58107885 ps
CPU time 0.61 seconds
Started May 14 01:15:16 PM PDT 24
Finished May 14 01:15:20 PM PDT 24
Peak memory 194104 kb
Host smart-715cb2bd-5d95-4516-8878-dd854b45a4f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193138419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4193138419
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3704022834
Short name T512
Test name
Test status
Simulation time 374153216 ps
CPU time 0.74 seconds
Started May 14 01:15:35 PM PDT 24
Finished May 14 01:15:38 PM PDT 24
Peak memory 195348 kb
Host smart-edc9ebb9-03b7-4e5d-be99-f8696dd329f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704022834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3704022834
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3988071022
Short name T116
Test name
Test status
Simulation time 746491648 ps
CPU time 21.25 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:39 PM PDT 24
Peak memory 195520 kb
Host smart-6ce89fae-030a-456d-865a-567d2d1aa334
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988071022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3988071022
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2303638769
Short name T390
Test name
Test status
Simulation time 348788189 ps
CPU time 1.12 seconds
Started May 14 01:15:32 PM PDT 24
Finished May 14 01:15:36 PM PDT 24
Peak memory 197784 kb
Host smart-965cb180-db45-473a-a690-20762a6c5596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303638769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2303638769
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2273605970
Short name T288
Test name
Test status
Simulation time 56845862 ps
CPU time 0.91 seconds
Started May 14 01:15:16 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 196900 kb
Host smart-1ffdc7e4-97fc-4933-8815-8428cc3bac34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273605970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2273605970
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1248042473
Short name T264
Test name
Test status
Simulation time 258514645 ps
CPU time 3.06 seconds
Started May 14 01:15:15 PM PDT 24
Finished May 14 01:15:21 PM PDT 24
Peak memory 198108 kb
Host smart-0dab0929-6003-46d3-bba6-2c26489017e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248042473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1248042473
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.835857296
Short name T450
Test name
Test status
Simulation time 62252154 ps
CPU time 1.94 seconds
Started May 14 01:15:30 PM PDT 24
Finished May 14 01:15:34 PM PDT 24
Peak memory 196748 kb
Host smart-f2024107-ee6c-480b-844b-34144b892606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835857296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
835857296
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3195709191
Short name T570
Test name
Test status
Simulation time 83651701 ps
CPU time 0.99 seconds
Started May 14 01:15:16 PM PDT 24
Finished May 14 01:15:19 PM PDT 24
Peak memory 196716 kb
Host smart-aebeee90-5750-4290-b414-c541d5fb4b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195709191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3195709191
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.3226838681
Short name T447
Test name
Test status
Simulation time 29930228 ps
CPU time 0.76 seconds
Started May 14 01:15:19 PM PDT 24
Finished May 14 01:15:21 PM PDT 24
Peak memory 195356 kb
Host smart-71899832-625b-4792-b107-4e79a8e31396
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226838681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.3226838681
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1284421749
Short name T21
Test name
Test status
Simulation time 382603457 ps
CPU time 4.36 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:15:43 PM PDT 24
Peak memory 197908 kb
Host smart-84435249-febf-4daf-9746-00722049b6dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284421749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1284421749
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3384745787
Short name T11
Test name
Test status
Simulation time 317501831 ps
CPU time 1.45 seconds
Started May 14 01:15:31 PM PDT 24
Finished May 14 01:15:34 PM PDT 24
Peak memory 196772 kb
Host smart-ae3d6d02-7f0e-4089-a292-8b48be7033b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384745787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3384745787
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.182080483
Short name T549
Test name
Test status
Simulation time 77675184 ps
CPU time 0.87 seconds
Started May 14 01:15:26 PM PDT 24
Finished May 14 01:15:28 PM PDT 24
Peak memory 195396 kb
Host smart-e80e1591-481f-43ba-a8e8-aa5cb8e2e427
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182080483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.182080483
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2970817386
Short name T671
Test name
Test status
Simulation time 7710039862 ps
CPU time 177.98 seconds
Started May 14 01:15:35 PM PDT 24
Finished May 14 01:18:35 PM PDT 24
Peak memory 198108 kb
Host smart-0cd2638a-915f-4b2d-af08-510efe1614bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970817386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2970817386
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1618528584
Short name T481
Test name
Test status
Simulation time 68032806070 ps
CPU time 399.91 seconds
Started May 14 01:15:16 PM PDT 24
Finished May 14 01:21:58 PM PDT 24
Peak memory 198144 kb
Host smart-0c2ba9af-658e-4ec9-948e-85ba8f7f2280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1618528584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1618528584
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1287517296
Short name T611
Test name
Test status
Simulation time 26087446 ps
CPU time 0.6 seconds
Started May 14 01:15:29 PM PDT 24
Finished May 14 01:15:31 PM PDT 24
Peak memory 193856 kb
Host smart-9a81e67f-5d58-4f77-bb63-0c0d911c2343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287517296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1287517296
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.4225085088
Short name T28
Test name
Test status
Simulation time 33958980 ps
CPU time 0.77 seconds
Started May 14 01:15:32 PM PDT 24
Finished May 14 01:15:35 PM PDT 24
Peak memory 195292 kb
Host smart-94a7db1a-5e81-4efe-b826-857b24d95504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225085088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.4225085088
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2296329624
Short name T621
Test name
Test status
Simulation time 3837450233 ps
CPU time 27.95 seconds
Started May 14 01:15:30 PM PDT 24
Finished May 14 01:16:00 PM PDT 24
Peak memory 197056 kb
Host smart-3b4ff0cd-8303-49a1-a9d9-8c1e13c111bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296329624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2296329624
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2248989565
Short name T655
Test name
Test status
Simulation time 49511388 ps
CPU time 0.82 seconds
Started May 14 01:15:33 PM PDT 24
Finished May 14 01:15:36 PM PDT 24
Peak memory 195876 kb
Host smart-c4f5d438-9a45-43f9-8032-6195b0d6615f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248989565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2248989565
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.179052228
Short name T446
Test name
Test status
Simulation time 130422868 ps
CPU time 1.08 seconds
Started May 14 01:15:28 PM PDT 24
Finished May 14 01:15:30 PM PDT 24
Peak memory 196748 kb
Host smart-28293ec2-f7af-470f-888d-31c3e892a680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179052228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.179052228
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1943495448
Short name T230
Test name
Test status
Simulation time 80654262 ps
CPU time 2.7 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:15:42 PM PDT 24
Peak memory 196348 kb
Host smart-50ebf6fc-6026-448c-86e4-392b829bc5dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943495448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1943495448
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3543426596
Short name T648
Test name
Test status
Simulation time 76946344 ps
CPU time 1.72 seconds
Started May 14 01:15:29 PM PDT 24
Finished May 14 01:15:33 PM PDT 24
Peak memory 196728 kb
Host smart-56393e22-b1d5-4926-b3d7-6648dd6e9fa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543426596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3543426596
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3386099828
Short name T607
Test name
Test status
Simulation time 42789907 ps
CPU time 0.99 seconds
Started May 14 01:15:34 PM PDT 24
Finished May 14 01:15:38 PM PDT 24
Peak memory 196660 kb
Host smart-efb72789-7048-4120-aefe-1357cebec5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386099828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3386099828
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2259960628
Short name T348
Test name
Test status
Simulation time 46037598 ps
CPU time 1.19 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:15:39 PM PDT 24
Peak memory 196656 kb
Host smart-a72ddca7-0cfd-46f7-ad09-b72e62a7e7ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259960628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2259960628
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2727691738
Short name T256
Test name
Test status
Simulation time 80485364 ps
CPU time 1.58 seconds
Started May 14 01:15:28 PM PDT 24
Finished May 14 01:15:30 PM PDT 24
Peak memory 197948 kb
Host smart-d5beecd4-6b48-4682-a64c-242b7bc7dd39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727691738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2727691738
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3372930884
Short name T373
Test name
Test status
Simulation time 71315070 ps
CPU time 1.37 seconds
Started May 14 01:15:34 PM PDT 24
Finished May 14 01:15:37 PM PDT 24
Peak memory 196764 kb
Host smart-ee73b8dc-f203-46d7-b7ae-6f5e8dca03ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372930884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3372930884
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2346177081
Short name T152
Test name
Test status
Simulation time 18303119 ps
CPU time 0.7 seconds
Started May 14 01:15:38 PM PDT 24
Finished May 14 01:15:42 PM PDT 24
Peak memory 194104 kb
Host smart-db891e39-89bf-43c5-8ffa-ac835a08bde4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346177081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2346177081
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.279251591
Short name T5
Test name
Test status
Simulation time 29498794942 ps
CPU time 164.41 seconds
Started May 14 01:15:30 PM PDT 24
Finished May 14 01:18:16 PM PDT 24
Peak memory 198064 kb
Host smart-a58723cb-e587-4ec7-be0f-190d676f06e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279251591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.279251591
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.876622581
Short name T646
Test name
Test status
Simulation time 26948061040 ps
CPU time 487.24 seconds
Started May 14 01:15:38 PM PDT 24
Finished May 14 01:23:49 PM PDT 24
Peak memory 198244 kb
Host smart-9b2d1648-957e-4ec0-88c0-229c7e9415a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=876622581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.876622581
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3612891644
Short name T153
Test name
Test status
Simulation time 13897576 ps
CPU time 0.64 seconds
Started May 14 01:15:30 PM PDT 24
Finished May 14 01:15:32 PM PDT 24
Peak memory 193840 kb
Host smart-0c229398-9803-4dda-a350-62b2e7130cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612891644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3612891644
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2759242750
Short name T190
Test name
Test status
Simulation time 145637862 ps
CPU time 0.85 seconds
Started May 14 01:15:32 PM PDT 24
Finished May 14 01:15:35 PM PDT 24
Peak memory 196156 kb
Host smart-6ef04bc1-e619-400f-9a56-4d2be603f2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759242750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2759242750
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2258389311
Short name T356
Test name
Test status
Simulation time 3294271702 ps
CPU time 25.09 seconds
Started May 14 01:15:32 PM PDT 24
Finished May 14 01:15:59 PM PDT 24
Peak memory 197432 kb
Host smart-4ceded68-2c19-4d87-8dad-bd77e982b000
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258389311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2258389311
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1996641935
Short name T575
Test name
Test status
Simulation time 271181320 ps
CPU time 0.9 seconds
Started May 14 01:15:33 PM PDT 24
Finished May 14 01:15:36 PM PDT 24
Peak memory 196668 kb
Host smart-60890b06-acc0-4544-b912-21eb544fdd86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996641935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1996641935
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.4200347433
Short name T662
Test name
Test status
Simulation time 72049669 ps
CPU time 1.12 seconds
Started May 14 01:15:28 PM PDT 24
Finished May 14 01:15:30 PM PDT 24
Peak memory 196836 kb
Host smart-02b0bb5d-7ddc-45f2-ab78-8182549d4904
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200347433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.4200347433
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3527244027
Short name T504
Test name
Test status
Simulation time 63807273 ps
CPU time 2.52 seconds
Started May 14 01:15:27 PM PDT 24
Finished May 14 01:15:31 PM PDT 24
Peak memory 198048 kb
Host smart-72bed292-a053-4db5-a61f-68ed6623936b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527244027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3527244027
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3997163174
Short name T267
Test name
Test status
Simulation time 106156172 ps
CPU time 1.58 seconds
Started May 14 01:15:25 PM PDT 24
Finished May 14 01:15:28 PM PDT 24
Peak memory 195944 kb
Host smart-36edbf4e-f9de-4b08-9112-7c99ea400802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997163174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3997163174
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3447715837
Short name T563
Test name
Test status
Simulation time 21946883 ps
CPU time 0.97 seconds
Started May 14 01:15:29 PM PDT 24
Finished May 14 01:15:32 PM PDT 24
Peak memory 196036 kb
Host smart-a0befc94-9eeb-4fb0-83b2-d09561ee2f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447715837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3447715837
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2321466686
Short name T487
Test name
Test status
Simulation time 21513184 ps
CPU time 0.74 seconds
Started May 14 01:15:35 PM PDT 24
Finished May 14 01:15:38 PM PDT 24
Peak memory 194972 kb
Host smart-0e89ba83-6435-4e87-8e5f-44f824933186
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321466686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2321466686
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.3905873299
Short name T221
Test name
Test status
Simulation time 422278105 ps
CPU time 5.15 seconds
Started May 14 01:15:26 PM PDT 24
Finished May 14 01:15:33 PM PDT 24
Peak memory 197992 kb
Host smart-dc1be1aa-acd7-4193-aa3a-6e2b93b12129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905873299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.3905873299
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.534576084
Short name T354
Test name
Test status
Simulation time 303895144 ps
CPU time 1.28 seconds
Started May 14 01:15:30 PM PDT 24
Finished May 14 01:15:33 PM PDT 24
Peak memory 196664 kb
Host smart-51c763a7-a7ee-4d9f-a426-c98ae1150440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534576084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.534576084
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2449869209
Short name T101
Test name
Test status
Simulation time 122292704 ps
CPU time 1.42 seconds
Started May 14 01:15:37 PM PDT 24
Finished May 14 01:15:41 PM PDT 24
Peak memory 196688 kb
Host smart-2932632a-1fdd-4f81-9406-70f345e3723c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449869209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2449869209
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2863948191
Short name T161
Test name
Test status
Simulation time 9342722417 ps
CPU time 189.42 seconds
Started May 14 01:15:26 PM PDT 24
Finished May 14 01:18:37 PM PDT 24
Peak memory 198240 kb
Host smart-cd4c5a1c-ced8-4590-a285-dcee7de1de69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863948191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2863948191
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1260432176
Short name T40
Test name
Test status
Simulation time 75672619 ps
CPU time 0.62 seconds
Started May 14 01:15:46 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 193880 kb
Host smart-636612fa-7891-4beb-acf0-9ab0fb9c9003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260432176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1260432176
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3236801289
Short name T697
Test name
Test status
Simulation time 43871470 ps
CPU time 0.6 seconds
Started May 14 01:15:37 PM PDT 24
Finished May 14 01:15:41 PM PDT 24
Peak memory 194032 kb
Host smart-46f15644-7ea5-441d-af42-222edebef400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236801289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3236801289
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.4233797467
Short name T358
Test name
Test status
Simulation time 1462502761 ps
CPU time 26.66 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:16:15 PM PDT 24
Peak memory 197996 kb
Host smart-6228276d-4296-4fc4-aa1d-0dfccad7bd1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233797467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.4233797467
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1441486027
Short name T576
Test name
Test status
Simulation time 45593777 ps
CPU time 0.91 seconds
Started May 14 01:15:39 PM PDT 24
Finished May 14 01:15:44 PM PDT 24
Peak memory 196016 kb
Host smart-28261bcf-105f-4327-a27a-9ba7e8362ec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441486027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1441486027
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2627742639
Short name T472
Test name
Test status
Simulation time 74917782 ps
CPU time 1.21 seconds
Started May 14 01:15:27 PM PDT 24
Finished May 14 01:15:29 PM PDT 24
Peak memory 196720 kb
Host smart-2632a0a6-b155-4df2-9600-2f77f5a60ea8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627742639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2627742639
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.549643597
Short name T284
Test name
Test status
Simulation time 34871577 ps
CPU time 1.32 seconds
Started May 14 01:15:35 PM PDT 24
Finished May 14 01:15:39 PM PDT 24
Peak memory 196548 kb
Host smart-8d886c5b-8cae-43ac-bffd-f2d66a591a92
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549643597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.549643597
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3761546860
Short name T438
Test name
Test status
Simulation time 128958200 ps
CPU time 2 seconds
Started May 14 01:15:33 PM PDT 24
Finished May 14 01:15:37 PM PDT 24
Peak memory 196728 kb
Host smart-ffa6b37a-9c6e-4efc-9dd5-de66654d7148
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761546860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3761546860
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1533944660
Short name T480
Test name
Test status
Simulation time 19170068 ps
CPU time 0.8 seconds
Started May 14 01:15:28 PM PDT 24
Finished May 14 01:15:30 PM PDT 24
Peak memory 196108 kb
Host smart-e62fadfa-87a3-4f6c-809e-3d5737c7e786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533944660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1533944660
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3102266546
Short name T125
Test name
Test status
Simulation time 29195155 ps
CPU time 0.74 seconds
Started May 14 01:15:30 PM PDT 24
Finished May 14 01:15:33 PM PDT 24
Peak memory 195012 kb
Host smart-3816c772-4336-4850-9925-2889138ed1da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102266546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3102266546
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2078497455
Short name T405
Test name
Test status
Simulation time 87977838 ps
CPU time 2.1 seconds
Started May 14 01:15:40 PM PDT 24
Finished May 14 01:15:46 PM PDT 24
Peak memory 197940 kb
Host smart-85b64549-0010-4a92-a0cb-d4ebd5290004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078497455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2078497455
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.25555352
Short name T236
Test name
Test status
Simulation time 282623694 ps
CPU time 1.15 seconds
Started May 14 01:15:36 PM PDT 24
Finished May 14 01:15:40 PM PDT 24
Peak memory 195776 kb
Host smart-5b1d3be5-9cee-497e-ba4c-baf51775e29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25555352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.25555352
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1715725845
Short name T679
Test name
Test status
Simulation time 295667051 ps
CPU time 1.37 seconds
Started May 14 01:15:35 PM PDT 24
Finished May 14 01:15:39 PM PDT 24
Peak memory 196712 kb
Host smart-b9381eca-86e1-4dda-ab8e-551b92ef5aa8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715725845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1715725845
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3362037545
Short name T633
Test name
Test status
Simulation time 525865470 ps
CPU time 15.36 seconds
Started May 14 01:15:40 PM PDT 24
Finished May 14 01:15:58 PM PDT 24
Peak memory 198004 kb
Host smart-5e47dfff-b9f9-4a52-ad65-56820bb502e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362037545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3362037545
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2365246228
Short name T361
Test name
Test status
Simulation time 13908759 ps
CPU time 0.57 seconds
Started May 14 01:15:41 PM PDT 24
Finished May 14 01:15:45 PM PDT 24
Peak memory 193944 kb
Host smart-c304d032-2538-41ed-8f82-b0530d9e689d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365246228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2365246228
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2316787603
Short name T138
Test name
Test status
Simulation time 46394750 ps
CPU time 0.8 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 196220 kb
Host smart-379a9b36-41d4-42d5-b65c-5912801e0c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316787603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2316787603
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.156759532
Short name T665
Test name
Test status
Simulation time 255884660 ps
CPU time 7.15 seconds
Started May 14 01:15:50 PM PDT 24
Finished May 14 01:16:02 PM PDT 24
Peak memory 195520 kb
Host smart-f02d192c-ab57-482e-b1f8-cd5bea8a3af1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156759532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.156759532
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3443940850
Short name T544
Test name
Test status
Simulation time 82653537 ps
CPU time 0.99 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:50 PM PDT 24
Peak memory 196988 kb
Host smart-39bb8d8b-b32c-4db0-8cf6-f315a088488c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443940850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3443940850
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.4170219494
Short name T313
Test name
Test status
Simulation time 22135598 ps
CPU time 0.72 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 194368 kb
Host smart-9d427800-92c9-441e-9e4a-b2f607430269
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170219494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.4170219494
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.27108088
Short name T301
Test name
Test status
Simulation time 28580804 ps
CPU time 1.24 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:50 PM PDT 24
Peak memory 197984 kb
Host smart-16427f2f-9901-4622-b4c3-53c6b419edc4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27108088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.gpio_intr_with_filter_rand_intr_event.27108088
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2682953203
Short name T189
Test name
Test status
Simulation time 677909280 ps
CPU time 3.18 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:50 PM PDT 24
Peak memory 197068 kb
Host smart-f86444ef-e71e-48a5-8cbe-e39ec9235177
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682953203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2682953203
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1589243033
Short name T249
Test name
Test status
Simulation time 65136234 ps
CPU time 1.2 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 196960 kb
Host smart-e1ae12b8-baec-4e41-9c36-2b97b656d9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589243033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1589243033
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3027101243
Short name T557
Test name
Test status
Simulation time 72974383 ps
CPU time 1.29 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:50 PM PDT 24
Peak memory 197032 kb
Host smart-43d31546-030e-4235-b84f-d90d30ac51dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027101243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3027101243
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1597770326
Short name T568
Test name
Test status
Simulation time 589334466 ps
CPU time 2.07 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:50 PM PDT 24
Peak memory 197980 kb
Host smart-c040dacc-2148-47d1-bac5-109b01fb36d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597770326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1597770326
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2714071940
Short name T411
Test name
Test status
Simulation time 76349468 ps
CPU time 1.22 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 195540 kb
Host smart-4e7bbf21-c0ae-43b2-adb9-dbb58e822082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714071940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2714071940
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1393986119
Short name T179
Test name
Test status
Simulation time 179095309 ps
CPU time 0.93 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 195772 kb
Host smart-a681b13c-9d20-4070-b585-9b7e483ec235
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393986119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1393986119
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.710343791
Short name T6
Test name
Test status
Simulation time 4525714630 ps
CPU time 57.76 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:16:45 PM PDT 24
Peak memory 198136 kb
Host smart-4a934a0b-664a-4234-8bb7-a3cec0045cae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710343791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.710343791
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1608877522
Short name T223
Test name
Test status
Simulation time 12205367 ps
CPU time 0.56 seconds
Started May 14 01:14:49 PM PDT 24
Finished May 14 01:14:53 PM PDT 24
Peak memory 192788 kb
Host smart-c8e61325-b6f1-498c-8854-490c4e2582d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608877522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1608877522
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3440445633
Short name T386
Test name
Test status
Simulation time 243021566 ps
CPU time 0.66 seconds
Started May 14 01:14:44 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 194064 kb
Host smart-f4b6658d-79fd-4af7-b660-fb25b4243617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440445633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3440445633
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1094911396
Short name T228
Test name
Test status
Simulation time 2316159021 ps
CPU time 15.28 seconds
Started May 14 01:14:37 PM PDT 24
Finished May 14 01:14:54 PM PDT 24
Peak memory 196976 kb
Host smart-75cd80ca-a687-469d-af8d-97baee038cd4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094911396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1094911396
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.2543284993
Short name T120
Test name
Test status
Simulation time 35884790 ps
CPU time 0.72 seconds
Started May 14 01:14:41 PM PDT 24
Finished May 14 01:14:44 PM PDT 24
Peak memory 194512 kb
Host smart-b2041bef-9403-4423-a256-030aad715663
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543284993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.2543284993
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1277126380
Short name T514
Test name
Test status
Simulation time 81518343 ps
CPU time 1.41 seconds
Started May 14 01:14:38 PM PDT 24
Finished May 14 01:14:42 PM PDT 24
Peak memory 197000 kb
Host smart-fef0be01-d5f9-498a-b30e-a3a359331a3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277126380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1277126380
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4136137268
Short name T710
Test name
Test status
Simulation time 631259063 ps
CPU time 1.71 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:51 PM PDT 24
Peak memory 196900 kb
Host smart-2f788404-7582-4206-92e5-c3cae42edcc2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136137268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4136137268
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3443593130
Short name T250
Test name
Test status
Simulation time 1561293376 ps
CPU time 2.51 seconds
Started May 14 01:14:34 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 197220 kb
Host smart-a0f731aa-c90e-45b8-bb4a-b8d1ce8d5345
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443593130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3443593130
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1528585025
Short name T394
Test name
Test status
Simulation time 52223830 ps
CPU time 1.13 seconds
Started May 14 01:14:34 PM PDT 24
Finished May 14 01:14:37 PM PDT 24
Peak memory 196560 kb
Host smart-a1347d16-1806-4614-a9f8-ebbc3ae58ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528585025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1528585025
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3615684197
Short name T642
Test name
Test status
Simulation time 42370321 ps
CPU time 0.98 seconds
Started May 14 01:14:37 PM PDT 24
Finished May 14 01:14:41 PM PDT 24
Peak memory 195992 kb
Host smart-00062dbe-be9e-4e8c-81b2-dfaab1a1baab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615684197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3615684197
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2488243553
Short name T688
Test name
Test status
Simulation time 84129462 ps
CPU time 4.01 seconds
Started May 14 01:14:38 PM PDT 24
Finished May 14 01:14:44 PM PDT 24
Peak memory 197992 kb
Host smart-f91535eb-1b01-4606-b37e-630c8a247cfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488243553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2488243553
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1426867942
Short name T37
Test name
Test status
Simulation time 515813470 ps
CPU time 0.96 seconds
Started May 14 01:14:51 PM PDT 24
Finished May 14 01:14:56 PM PDT 24
Peak memory 214912 kb
Host smart-3cf09be3-f3b1-4cde-871a-d4c434ad8c26
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426867942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1426867942
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1369274745
Short name T616
Test name
Test status
Simulation time 541033705 ps
CPU time 1.41 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 197908 kb
Host smart-a9aa097e-0b5d-4c21-a9c6-cddf98ea6b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369274745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1369274745
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.864830552
Short name T645
Test name
Test status
Simulation time 235277908 ps
CPU time 1.01 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:53 PM PDT 24
Peak memory 195684 kb
Host smart-89025097-a245-44d3-a47f-fbc617f243c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864830552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.864830552
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2046021004
Short name T483
Test name
Test status
Simulation time 10954716508 ps
CPU time 152.52 seconds
Started May 14 01:14:41 PM PDT 24
Finished May 14 01:17:15 PM PDT 24
Peak memory 198056 kb
Host smart-968d9700-c4c9-4468-8b22-af4617b0819b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046021004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2046021004
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1552232424
Short name T694
Test name
Test status
Simulation time 14652451 ps
CPU time 0.56 seconds
Started May 14 01:15:40 PM PDT 24
Finished May 14 01:15:45 PM PDT 24
Peak memory 193884 kb
Host smart-53efc5d2-9dc8-4012-8980-3fd5657093cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552232424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1552232424
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3118488632
Short name T639
Test name
Test status
Simulation time 40956930 ps
CPU time 0.9 seconds
Started May 14 01:15:49 PM PDT 24
Finished May 14 01:15:55 PM PDT 24
Peak memory 197260 kb
Host smart-f99a2a54-8ced-47e3-b0ce-44e9540fc37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118488632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3118488632
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3463189904
Short name T516
Test name
Test status
Simulation time 991093534 ps
CPU time 19.69 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 195500 kb
Host smart-1089fdcb-988e-4e98-9961-77fb5e795dac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463189904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3463189904
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3514873800
Short name T100
Test name
Test status
Simulation time 42659397 ps
CPU time 0.79 seconds
Started May 14 01:15:38 PM PDT 24
Finished May 14 01:15:43 PM PDT 24
Peak memory 196088 kb
Host smart-126e6213-0358-415b-a455-ab377bd12b69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514873800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3514873800
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3530693979
Short name T706
Test name
Test status
Simulation time 487051403 ps
CPU time 1.06 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 195720 kb
Host smart-04870611-dfcc-4162-83d4-f394c1207950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530693979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3530693979
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3633738877
Short name T573
Test name
Test status
Simulation time 55149774 ps
CPU time 2.26 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 197996 kb
Host smart-63be842f-ad55-4d47-b8fd-f0a5cb7c551c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633738877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3633738877
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1063223738
Short name T318
Test name
Test status
Simulation time 342694280 ps
CPU time 2.12 seconds
Started May 14 01:15:38 PM PDT 24
Finished May 14 01:15:43 PM PDT 24
Peak memory 196900 kb
Host smart-3b69cbed-4482-45f7-9ff0-89a232bd61dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063223738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1063223738
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1890222197
Short name T509
Test name
Test status
Simulation time 185853164 ps
CPU time 1.19 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 196600 kb
Host smart-a43f80e8-f1b7-44ad-8b21-103501b82a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890222197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1890222197
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2969541872
Short name T333
Test name
Test status
Simulation time 75815803 ps
CPU time 0.76 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:47 PM PDT 24
Peak memory 195392 kb
Host smart-b680bb9e-bd86-408c-ad19-7681a207bbde
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969541872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2969541872
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.207652058
Short name T471
Test name
Test status
Simulation time 2272739479 ps
CPU time 6.38 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 198048 kb
Host smart-5c7b5ada-bfc5-4134-9140-b4b1cdc04d90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207652058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.207652058
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.4100924328
Short name T426
Test name
Test status
Simulation time 118302996 ps
CPU time 0.81 seconds
Started May 14 01:15:39 PM PDT 24
Finished May 14 01:15:43 PM PDT 24
Peak memory 195244 kb
Host smart-76c92e58-1281-455f-be09-7da4973fc0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100924328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.4100924328
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3603901863
Short name T297
Test name
Test status
Simulation time 49664510 ps
CPU time 1.06 seconds
Started May 14 01:15:41 PM PDT 24
Finished May 14 01:15:46 PM PDT 24
Peak memory 196372 kb
Host smart-d1bd12c2-d686-4ad5-a154-df410f2eab82
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603901863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3603901863
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1109557978
Short name T661
Test name
Test status
Simulation time 15531889383 ps
CPU time 178.6 seconds
Started May 14 01:15:50 PM PDT 24
Finished May 14 01:18:54 PM PDT 24
Peak memory 198204 kb
Host smart-1c73e9bc-ba43-457b-a5bb-658f40f2c4ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109557978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1109557978
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2481134671
Short name T199
Test name
Test status
Simulation time 28628879 ps
CPU time 0.62 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 193900 kb
Host smart-10bdb59f-b166-48bb-862a-43bb7fd9d7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481134671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2481134671
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1126138336
Short name T344
Test name
Test status
Simulation time 122296310 ps
CPU time 0.69 seconds
Started May 14 01:15:39 PM PDT 24
Finished May 14 01:15:43 PM PDT 24
Peak memory 194772 kb
Host smart-f58ff1f8-9c77-4a47-9cbe-7e66b14f9768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126138336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1126138336
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.183599785
Short name T383
Test name
Test status
Simulation time 821210853 ps
CPU time 23.7 seconds
Started May 14 01:15:39 PM PDT 24
Finished May 14 01:16:06 PM PDT 24
Peak memory 196716 kb
Host smart-3aca2e80-7236-49b8-a65b-409eff534f3c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183599785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.183599785
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3795430395
Short name T346
Test name
Test status
Simulation time 76262751 ps
CPU time 0.98 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 197912 kb
Host smart-45ae0551-65a2-460a-9402-9755c26d193b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795430395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3795430395
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.502673081
Short name T198
Test name
Test status
Simulation time 37429324 ps
CPU time 0.81 seconds
Started May 14 01:15:39 PM PDT 24
Finished May 14 01:15:43 PM PDT 24
Peak memory 195504 kb
Host smart-76235e60-7bbd-46f1-be8c-a7a0826e6f23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502673081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.502673081
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2987838263
Short name T193
Test name
Test status
Simulation time 276857555 ps
CPU time 2.98 seconds
Started May 14 01:15:45 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 198072 kb
Host smart-bc3fc02a-e9b8-47f2-a9ce-627d5a89bab3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987838263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2987838263
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1290747234
Short name T382
Test name
Test status
Simulation time 25599670 ps
CPU time 0.96 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 195648 kb
Host smart-05e1ea75-2ddc-4430-85c0-e285bd5c73c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290747234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1290747234
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2834533142
Short name T327
Test name
Test status
Simulation time 106351387 ps
CPU time 1.12 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 196516 kb
Host smart-5bd4df2c-f9ac-4f4c-a65f-c4fde5766f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834533142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2834533142
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1022838396
Short name T185
Test name
Test status
Simulation time 87064162 ps
CPU time 0.93 seconds
Started May 14 01:15:48 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 196608 kb
Host smart-87a65b0c-24aa-46d1-92e0-766b37329a8c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022838396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1022838396
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2260837143
Short name T585
Test name
Test status
Simulation time 2023169961 ps
CPU time 5.52 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 198176 kb
Host smart-30abff85-322b-425a-a841-f5daaa80abf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260837143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2260837143
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3128451929
Short name T680
Test name
Test status
Simulation time 767191981 ps
CPU time 1.45 seconds
Started May 14 01:15:38 PM PDT 24
Finished May 14 01:15:43 PM PDT 24
Peak memory 196248 kb
Host smart-76d75980-42c8-4f1a-8cd3-af89deb15ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128451929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3128451929
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1047171582
Short name T252
Test name
Test status
Simulation time 115347754 ps
CPU time 1.08 seconds
Started May 14 01:15:51 PM PDT 24
Finished May 14 01:15:57 PM PDT 24
Peak memory 195536 kb
Host smart-929346d7-e681-4ad5-a794-c8d66224eab7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047171582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1047171582
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.680266332
Short name T8
Test name
Test status
Simulation time 10085771517 ps
CPU time 110.21 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:17:39 PM PDT 24
Peak memory 198192 kb
Host smart-78ac362c-985c-44ce-bf45-d33f5ae0a8bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680266332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.680266332
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1512971448
Short name T330
Test name
Test status
Simulation time 15433711 ps
CPU time 0.7 seconds
Started May 14 01:15:47 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 194080 kb
Host smart-e661ffb2-f702-48e5-94e1-bf95c20c0429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512971448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1512971448
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.542583789
Short name T622
Test name
Test status
Simulation time 83366333 ps
CPU time 0.69 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 194860 kb
Host smart-13a73d04-0aa8-43a8-9136-c32d61a50d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542583789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.542583789
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3038072457
Short name T674
Test name
Test status
Simulation time 131156704 ps
CPU time 7.07 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 196876 kb
Host smart-a6e06967-0c22-4817-87d9-7543d784e922
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038072457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3038072457
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1710534973
Short name T2
Test name
Test status
Simulation time 1565492526 ps
CPU time 0.99 seconds
Started May 14 01:15:41 PM PDT 24
Finished May 14 01:15:46 PM PDT 24
Peak memory 196460 kb
Host smart-5e93c37f-092f-4070-9414-80b40836d012
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710534973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1710534973
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2456819341
Short name T231
Test name
Test status
Simulation time 103797805 ps
CPU time 1 seconds
Started May 14 01:16:05 PM PDT 24
Finished May 14 01:16:10 PM PDT 24
Peak memory 195988 kb
Host smart-b0c7315e-eeb6-4943-902d-30d8f622f8fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456819341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2456819341
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2540714134
Short name T572
Test name
Test status
Simulation time 190953852 ps
CPU time 3.71 seconds
Started May 14 01:15:55 PM PDT 24
Finished May 14 01:16:03 PM PDT 24
Peak memory 198104 kb
Host smart-666977ac-1ce4-4193-9afc-6ad0275559cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540714134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2540714134
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3922537639
Short name T340
Test name
Test status
Simulation time 80844976 ps
CPU time 1.05 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:47 PM PDT 24
Peak memory 196376 kb
Host smart-cf8744e7-00d3-4171-9f2b-5c104972affd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922537639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3922537639
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3403305618
Short name T282
Test name
Test status
Simulation time 25233149 ps
CPU time 1.1 seconds
Started May 14 01:15:45 PM PDT 24
Finished May 14 01:15:51 PM PDT 24
Peak memory 196452 kb
Host smart-f7fd7063-e149-46e3-b25c-7f2744c57a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403305618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3403305618
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3482243355
Short name T693
Test name
Test status
Simulation time 62364437 ps
CPU time 1.17 seconds
Started May 14 01:15:55 PM PDT 24
Finished May 14 01:16:01 PM PDT 24
Peak memory 197044 kb
Host smart-06b9e198-977c-43f2-99c6-ac6dc9793698
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482243355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3482243355
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4119564556
Short name T704
Test name
Test status
Simulation time 469430177 ps
CPU time 5.11 seconds
Started May 14 01:15:40 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 197948 kb
Host smart-6f17a50d-4e3a-4b42-ae42-ce522e18dd23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119564556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.4119564556
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.4111797284
Short name T652
Test name
Test status
Simulation time 112337478 ps
CPU time 1.01 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:50 PM PDT 24
Peak memory 195760 kb
Host smart-313465a7-fb85-40b1-a8af-a1a99e8de91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111797284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.4111797284
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1029747933
Short name T255
Test name
Test status
Simulation time 321132092 ps
CPU time 0.92 seconds
Started May 14 01:15:47 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 195284 kb
Host smart-49b5b07c-e0ce-49ab-a513-9f9f1fc35780
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029747933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1029747933
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.1973278322
Short name T213
Test name
Test status
Simulation time 24956276162 ps
CPU time 94.54 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:17:24 PM PDT 24
Peak memory 198116 kb
Host smart-a96b8f9d-1861-47df-b397-7f096969ce29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973278322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.1973278322
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.932280927
Short name T631
Test name
Test status
Simulation time 13643820 ps
CPU time 0.59 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 194568 kb
Host smart-3563e287-600b-463c-86b6-f01035085fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932280927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.932280927
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2857561405
Short name T159
Test name
Test status
Simulation time 27723328 ps
CPU time 0.63 seconds
Started May 14 01:15:37 PM PDT 24
Finished May 14 01:15:41 PM PDT 24
Peak memory 194696 kb
Host smart-c503c78c-6562-4071-8bb0-bd4831cbaa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857561405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2857561405
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_full_random.3747982974
Short name T270
Test name
Test status
Simulation time 137554127 ps
CPU time 0.7 seconds
Started May 14 01:15:46 PM PDT 24
Finished May 14 01:15:52 PM PDT 24
Peak memory 194788 kb
Host smart-2894a5e9-9aab-423b-b91b-55345858c46e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747982974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3747982974
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3387009788
Short name T700
Test name
Test status
Simulation time 123438008 ps
CPU time 0.9 seconds
Started May 14 01:15:40 PM PDT 24
Finished May 14 01:15:44 PM PDT 24
Peak memory 196504 kb
Host smart-32deb125-7a40-49f8-b406-2bfae082ad86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387009788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3387009788
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2661594400
Short name T478
Test name
Test status
Simulation time 57171094 ps
CPU time 2.41 seconds
Started May 14 01:15:46 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 198036 kb
Host smart-069b1d8c-7e35-475d-9539-c797629528ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661594400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2661594400
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.4038312033
Short name T166
Test name
Test status
Simulation time 86773866 ps
CPU time 2.89 seconds
Started May 14 01:15:47 PM PDT 24
Finished May 14 01:15:55 PM PDT 24
Peak memory 198048 kb
Host smart-42df43e5-1c0a-4e06-959e-e481628acc95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038312033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.4038312033
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.504552779
Short name T424
Test name
Test status
Simulation time 35837430 ps
CPU time 1.14 seconds
Started May 14 01:15:47 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 197040 kb
Host smart-96231507-1fd9-4ede-a48b-b23b2de4404d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504552779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.504552779
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1385166927
Short name T335
Test name
Test status
Simulation time 84826737 ps
CPU time 1.12 seconds
Started May 14 01:15:42 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 196720 kb
Host smart-5f360332-fb36-49b2-bfbc-e84a26ba3cc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385166927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1385166927
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1116403767
Short name T675
Test name
Test status
Simulation time 229343115 ps
CPU time 3.67 seconds
Started May 14 01:15:52 PM PDT 24
Finished May 14 01:16:00 PM PDT 24
Peak memory 198016 kb
Host smart-efc94965-c6dc-43c2-85ea-3c09c7034365
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116403767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1116403767
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2339589835
Short name T175
Test name
Test status
Simulation time 41686248 ps
CPU time 1.07 seconds
Started May 14 01:15:50 PM PDT 24
Finished May 14 01:15:56 PM PDT 24
Peak memory 195612 kb
Host smart-78a4a210-deb8-4168-abc5-8807a3fe40cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339589835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2339589835
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3814036415
Short name T280
Test name
Test status
Simulation time 62577874 ps
CPU time 1.13 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:48 PM PDT 24
Peak memory 195548 kb
Host smart-f9bd39b5-adc4-415f-8ffa-b94fd02ddcec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814036415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3814036415
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3672786583
Short name T552
Test name
Test status
Simulation time 51295126617 ps
CPU time 170.18 seconds
Started May 14 01:15:41 PM PDT 24
Finished May 14 01:18:36 PM PDT 24
Peak memory 198204 kb
Host smart-10569071-f3dc-4ce1-83e8-bf926afd930f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672786583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3672786583
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.72951475
Short name T416
Test name
Test status
Simulation time 161718396 ps
CPU time 0.56 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 194068 kb
Host smart-fa08e341-0e17-4812-b400-6477d5730222
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72951475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.72951475
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.580954514
Short name T12
Test name
Test status
Simulation time 23503393 ps
CPU time 0.72 seconds
Started May 14 01:15:48 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 195324 kb
Host smart-5e3b56d9-35c6-44c8-9778-6056a2915681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580954514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.580954514
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2915584581
Short name T287
Test name
Test status
Simulation time 1340054722 ps
CPU time 17.38 seconds
Started May 14 01:15:48 PM PDT 24
Finished May 14 01:16:10 PM PDT 24
Peak memory 196852 kb
Host smart-9c8cd843-a4d8-4561-9cbd-cb853e648694
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915584581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2915584581
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.843570882
Short name T337
Test name
Test status
Simulation time 92121057 ps
CPU time 0.97 seconds
Started May 14 01:15:46 PM PDT 24
Finished May 14 01:15:52 PM PDT 24
Peak memory 197084 kb
Host smart-3dac72b4-ef0b-46d8-ba40-7bbee5874b8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843570882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.843570882
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2268665290
Short name T545
Test name
Test status
Simulation time 279943646 ps
CPU time 1.3 seconds
Started May 14 01:15:50 PM PDT 24
Finished May 14 01:15:56 PM PDT 24
Peak memory 196920 kb
Host smart-2c730c8e-5872-44ad-a9a6-6ca500b74676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268665290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2268665290
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2174859608
Short name T659
Test name
Test status
Simulation time 74155681 ps
CPU time 3.12 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:51 PM PDT 24
Peak memory 197992 kb
Host smart-867d1121-6cbc-45e2-83af-e5bfe2e63d80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174859608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2174859608
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3469802379
Short name T117
Test name
Test status
Simulation time 93832257 ps
CPU time 2.32 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:51 PM PDT 24
Peak memory 196524 kb
Host smart-0f4e9c45-9c6e-452b-a325-1a5f68875a45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469802379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3469802379
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2789349528
Short name T135
Test name
Test status
Simulation time 55252344 ps
CPU time 1.07 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:06 PM PDT 24
Peak memory 196596 kb
Host smart-99031b8d-2ec7-4059-b4b3-14e56f82832c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789349528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2789349528
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2102004125
Short name T343
Test name
Test status
Simulation time 76339669 ps
CPU time 1.36 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:07 PM PDT 24
Peak memory 198036 kb
Host smart-323087c9-132d-4674-aa9a-c4d8775514dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102004125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2102004125
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2517345732
Short name T364
Test name
Test status
Simulation time 778040078 ps
CPU time 2.76 seconds
Started May 14 01:15:45 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 197908 kb
Host smart-55e3bca1-2d7c-48a0-a8cc-8c522934029f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517345732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2517345732
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.200285404
Short name T468
Test name
Test status
Simulation time 93894025 ps
CPU time 1.34 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:51 PM PDT 24
Peak memory 196696 kb
Host smart-5b477ef1-7774-4b58-a2a7-cf5a66802698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200285404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.200285404
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2764191507
Short name T269
Test name
Test status
Simulation time 21885730 ps
CPU time 0.77 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:50 PM PDT 24
Peak memory 195288 kb
Host smart-f3268259-f960-47f7-a73f-861c78928c91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764191507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2764191507
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3002049448
Short name T150
Test name
Test status
Simulation time 10253713466 ps
CPU time 65.21 seconds
Started May 14 01:15:50 PM PDT 24
Finished May 14 01:17:00 PM PDT 24
Peak memory 198160 kb
Host smart-02a0b019-ebd7-4df1-bfba-d6aae89fb4e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002049448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3002049448
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1601108495
Short name T428
Test name
Test status
Simulation time 12358711 ps
CPU time 0.57 seconds
Started May 14 01:16:06 PM PDT 24
Finished May 14 01:16:10 PM PDT 24
Peak memory 193912 kb
Host smart-a34d4874-98a1-49e6-a28d-e50cacdbf446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601108495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1601108495
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.4137245292
Short name T156
Test name
Test status
Simulation time 21473359 ps
CPU time 0.74 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 195276 kb
Host smart-911373f2-cfc2-4fae-bce8-48d86c3dd249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137245292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.4137245292
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2322751677
Short name T286
Test name
Test status
Simulation time 288913323 ps
CPU time 9.05 seconds
Started May 14 01:15:55 PM PDT 24
Finished May 14 01:16:08 PM PDT 24
Peak memory 196892 kb
Host smart-86b64203-e6ac-422f-86fb-0b916b337c42
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322751677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2322751677
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3395927394
Short name T649
Test name
Test status
Simulation time 41609501 ps
CPU time 0.7 seconds
Started May 14 01:16:05 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 194808 kb
Host smart-ef34ad71-42aa-4773-845b-0ce0c22ac46d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395927394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3395927394
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2437580800
Short name T257
Test name
Test status
Simulation time 42083150 ps
CPU time 1.1 seconds
Started May 14 01:15:49 PM PDT 24
Finished May 14 01:15:56 PM PDT 24
Peak memory 196540 kb
Host smart-6cdb5021-e5f6-481d-a6f4-9389088c19a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437580800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2437580800
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1073531847
Short name T254
Test name
Test status
Simulation time 136286915 ps
CPU time 2.94 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:52 PM PDT 24
Peak memory 198108 kb
Host smart-5aa6c0ef-504a-429e-95c2-4686b8df60be
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073531847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1073531847
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1356534138
Short name T294
Test name
Test status
Simulation time 117858497 ps
CPU time 1.48 seconds
Started May 14 01:15:47 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 196720 kb
Host smart-a97c02aa-854f-4e5e-974c-43b97d40ecea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356534138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1356534138
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.46749335
Short name T587
Test name
Test status
Simulation time 44638354 ps
CPU time 1.01 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:49 PM PDT 24
Peak memory 196672 kb
Host smart-67cf943e-bd97-4b6a-8200-f7d6ad62a7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46749335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.46749335
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3711251766
Short name T136
Test name
Test status
Simulation time 575747016 ps
CPU time 1.1 seconds
Started May 14 01:16:05 PM PDT 24
Finished May 14 01:16:10 PM PDT 24
Peak memory 196048 kb
Host smart-e3fc78b1-29e2-4d20-8b87-34a535b9a1f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711251766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3711251766
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.4207943392
Short name T96
Test name
Test status
Simulation time 172122836 ps
CPU time 4.02 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 198132 kb
Host smart-c34b02ed-9f63-48fd-b245-18d7c470aa0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207943392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.4207943392
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2471798256
Short name T687
Test name
Test status
Simulation time 49924488 ps
CPU time 1.01 seconds
Started May 14 01:15:48 PM PDT 24
Finished May 14 01:15:55 PM PDT 24
Peak memory 196300 kb
Host smart-d1a66065-d579-4a17-b9ca-a90391fdde62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471798256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2471798256
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.318536023
Short name T174
Test name
Test status
Simulation time 169854391 ps
CPU time 0.75 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:16:05 PM PDT 24
Peak memory 195316 kb
Host smart-8c3f1e4d-b6cd-432b-993c-6a313a6beb47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318536023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.318536023
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3659697944
Short name T502
Test name
Test status
Simulation time 13624989431 ps
CPU time 71.15 seconds
Started May 14 01:15:46 PM PDT 24
Finished May 14 01:17:02 PM PDT 24
Peak memory 198140 kb
Host smart-9c3bc3ba-20c9-46b4-9165-7fdf0564f3a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659697944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3659697944
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2420037398
Short name T370
Test name
Test status
Simulation time 120456026 ps
CPU time 0.58 seconds
Started May 14 01:16:12 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 193892 kb
Host smart-f0424a49-6493-41a6-a0b8-79849105acd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420037398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2420037398
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2289352643
Short name T626
Test name
Test status
Simulation time 35599743 ps
CPU time 0.92 seconds
Started May 14 01:15:48 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 195912 kb
Host smart-07a6793c-f2f6-455b-8ed5-e0fe2dff0eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289352643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2289352643
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.3901454421
Short name T244
Test name
Test status
Simulation time 181594730 ps
CPU time 4.12 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 196176 kb
Host smart-c8735611-8289-4c36-8a64-7fd33ee07cd1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901454421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.3901454421
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2458734482
Short name T51
Test name
Test status
Simulation time 25547970 ps
CPU time 0.71 seconds
Started May 14 01:15:48 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 195380 kb
Host smart-d185b9e8-829e-49e7-9175-f55a7c8b2a78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458734482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2458734482
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.318023110
Short name T162
Test name
Test status
Simulation time 206427951 ps
CPU time 1.24 seconds
Started May 14 01:15:55 PM PDT 24
Finished May 14 01:16:00 PM PDT 24
Peak memory 198052 kb
Host smart-4099d992-b2f2-41b0-aebb-4fdd5644f686
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318023110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.318023110
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1390318141
Short name T435
Test name
Test status
Simulation time 115718800 ps
CPU time 2.29 seconds
Started May 14 01:16:07 PM PDT 24
Finished May 14 01:16:12 PM PDT 24
Peak memory 198056 kb
Host smart-61a79202-1d65-4830-a048-61a18003ee82
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390318141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1390318141
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1432327726
Short name T539
Test name
Test status
Simulation time 98515686 ps
CPU time 2.68 seconds
Started May 14 01:15:49 PM PDT 24
Finished May 14 01:15:57 PM PDT 24
Peak memory 196944 kb
Host smart-7cb55b67-45a7-4593-a0fd-e8300b1973d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432327726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1432327726
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1760601151
Short name T664
Test name
Test status
Simulation time 55267922 ps
CPU time 1.16 seconds
Started May 14 01:15:52 PM PDT 24
Finished May 14 01:15:58 PM PDT 24
Peak memory 197056 kb
Host smart-3e173c59-14e5-473a-a80a-d53e425002c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760601151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1760601151
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2001928158
Short name T304
Test name
Test status
Simulation time 137837557 ps
CPU time 0.85 seconds
Started May 14 01:15:49 PM PDT 24
Finished May 14 01:15:55 PM PDT 24
Peak memory 195536 kb
Host smart-61390208-0488-429c-ba56-0d2fc38e7c96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001928158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2001928158
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2369325115
Short name T308
Test name
Test status
Simulation time 3836830218 ps
CPU time 5.21 seconds
Started May 14 01:16:08 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 198100 kb
Host smart-5897f84c-d455-4130-a9d5-b30f3bef95df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369325115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2369325115
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1727712577
Short name T243
Test name
Test status
Simulation time 244072813 ps
CPU time 1.29 seconds
Started May 14 01:15:49 PM PDT 24
Finished May 14 01:15:56 PM PDT 24
Peak memory 196756 kb
Host smart-666f3552-540a-4296-a93c-da074a899be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727712577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1727712577
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.363924349
Short name T400
Test name
Test status
Simulation time 174626322 ps
CPU time 1.11 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:50 PM PDT 24
Peak memory 196504 kb
Host smart-700b422c-bd1c-4476-a84e-912856f3deee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363924349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.363924349
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.609518096
Short name T369
Test name
Test status
Simulation time 8082130569 ps
CPU time 53.15 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:16:41 PM PDT 24
Peak memory 198124 kb
Host smart-50f08fe3-7c68-47b6-a2e8-913e94928690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609518096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.609518096
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2808774674
Short name T62
Test name
Test status
Simulation time 18790421290 ps
CPU time 183.26 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:19:07 PM PDT 24
Peak memory 198300 kb
Host smart-300d44a9-18a8-42b4-a16b-aa9b788f32e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2808774674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2808774674
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2393021074
Short name T415
Test name
Test status
Simulation time 15750217 ps
CPU time 0.59 seconds
Started May 14 01:15:47 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 194720 kb
Host smart-4ff9d0ec-2108-4ee1-b9b1-ece61d657e09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393021074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2393021074
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2059601402
Short name T291
Test name
Test status
Simulation time 28785379 ps
CPU time 0.85 seconds
Started May 14 01:15:44 PM PDT 24
Finished May 14 01:15:51 PM PDT 24
Peak memory 196352 kb
Host smart-e308e349-a7a6-49e4-ab72-8702bc01eb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059601402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2059601402
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.342628672
Short name T484
Test name
Test status
Simulation time 461781609 ps
CPU time 6.97 seconds
Started May 14 01:15:48 PM PDT 24
Finished May 14 01:16:00 PM PDT 24
Peak memory 196688 kb
Host smart-66c2b376-586a-4aac-b564-e9953e03c9dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342628672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.342628672
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1029720970
Short name T14
Test name
Test status
Simulation time 42110341 ps
CPU time 0.75 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:16:05 PM PDT 24
Peak memory 195824 kb
Host smart-d4d858cd-0161-4a84-8064-28b4e3fb0e74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029720970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1029720970
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.590138395
Short name T27
Test name
Test status
Simulation time 169172920 ps
CPU time 0.95 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:07 PM PDT 24
Peak memory 196164 kb
Host smart-b7d92a60-0b68-4bf4-9d05-e57065364576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590138395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.590138395
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4051164526
Short name T232
Test name
Test status
Simulation time 384884269 ps
CPU time 2.4 seconds
Started May 14 01:15:47 PM PDT 24
Finished May 14 01:15:55 PM PDT 24
Peak memory 198024 kb
Host smart-e78351d8-5462-44c9-a227-b8cc49a3c420
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051164526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4051164526
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3325114699
Short name T375
Test name
Test status
Simulation time 1677176353 ps
CPU time 3.27 seconds
Started May 14 01:15:45 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 197104 kb
Host smart-ec74fbb5-10ef-4462-9e81-452527b3d1ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325114699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3325114699
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3072859807
Short name T690
Test name
Test status
Simulation time 25774156 ps
CPU time 0.69 seconds
Started May 14 01:15:58 PM PDT 24
Finished May 14 01:16:02 PM PDT 24
Peak memory 194380 kb
Host smart-d02c295f-0016-4c33-8736-e9b4cdeaa64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072859807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3072859807
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1359078217
Short name T529
Test name
Test status
Simulation time 354528072 ps
CPU time 1.36 seconds
Started May 14 01:15:43 PM PDT 24
Finished May 14 01:15:50 PM PDT 24
Peak memory 197948 kb
Host smart-7b0ed443-a352-4090-be23-0e53aba2dc7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359078217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1359078217
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3091766332
Short name T293
Test name
Test status
Simulation time 75258077 ps
CPU time 1.96 seconds
Started May 14 01:15:47 PM PDT 24
Finished May 14 01:15:54 PM PDT 24
Peak memory 198024 kb
Host smart-0457d53f-d94e-4eaa-8474-e21040e7628b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091766332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3091766332
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.867103248
Short name T353
Test name
Test status
Simulation time 377163517 ps
CPU time 1.15 seconds
Started May 14 01:15:50 PM PDT 24
Finished May 14 01:15:57 PM PDT 24
Peak memory 196392 kb
Host smart-65f9966b-6f35-4457-9ad8-15b90e06a06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867103248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.867103248
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2248741702
Short name T167
Test name
Test status
Simulation time 175989165 ps
CPU time 1.32 seconds
Started May 14 01:15:48 PM PDT 24
Finished May 14 01:15:55 PM PDT 24
Peak memory 195540 kb
Host smart-54d9b0ab-daff-4772-9295-9c1f725f6b9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248741702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2248741702
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2573572157
Short name T522
Test name
Test status
Simulation time 6517726540 ps
CPU time 90.42 seconds
Started May 14 01:15:45 PM PDT 24
Finished May 14 01:17:21 PM PDT 24
Peak memory 198156 kb
Host smart-727b0361-582d-4d65-aab4-cba55f5efbce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573572157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2573572157
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.636875784
Short name T210
Test name
Test status
Simulation time 12251680 ps
CPU time 0.6 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:16:06 PM PDT 24
Peak memory 193864 kb
Host smart-b26a68d3-f553-4093-a48f-331262230130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636875784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.636875784
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4106897705
Short name T582
Test name
Test status
Simulation time 109958420 ps
CPU time 0.84 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:03 PM PDT 24
Peak memory 195364 kb
Host smart-143755ae-d823-4992-bde8-b89a6d59cee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106897705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4106897705
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2700404505
Short name T276
Test name
Test status
Simulation time 477136075 ps
CPU time 14.45 seconds
Started May 14 01:15:53 PM PDT 24
Finished May 14 01:16:12 PM PDT 24
Peak memory 196872 kb
Host smart-62a61326-0daf-4407-b782-eda57df9851c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700404505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2700404505
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.1778856717
Short name T266
Test name
Test status
Simulation time 266572914 ps
CPU time 0.94 seconds
Started May 14 01:16:04 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 196416 kb
Host smart-8bd55d80-5dac-4b13-b180-1caac5f2389b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778856717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.1778856717
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1909946863
Short name T543
Test name
Test status
Simulation time 105521912 ps
CPU time 0.73 seconds
Started May 14 01:15:52 PM PDT 24
Finished May 14 01:15:58 PM PDT 24
Peak memory 194380 kb
Host smart-59caa1d2-2439-4d2f-bcd8-68db955efdc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909946863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1909946863
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1696273439
Short name T492
Test name
Test status
Simulation time 62827714 ps
CPU time 2.65 seconds
Started May 14 01:16:05 PM PDT 24
Finished May 14 01:16:11 PM PDT 24
Peak memory 198084 kb
Host smart-a0f00d9d-bc17-4959-811d-f08241d89960
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696273439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1696273439
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.144738461
Short name T111
Test name
Test status
Simulation time 949747206 ps
CPU time 3.76 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:14 PM PDT 24
Peak memory 196928 kb
Host smart-9d053450-61ab-4a83-913c-f5a6d0993848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144738461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
144738461
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2288792775
Short name T215
Test name
Test status
Simulation time 43533070 ps
CPU time 1.17 seconds
Started May 14 01:15:49 PM PDT 24
Finished May 14 01:15:55 PM PDT 24
Peak memory 195884 kb
Host smart-17b7db52-8b1c-41dd-b751-68b4c9c238d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288792775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2288792775
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1273669894
Short name T385
Test name
Test status
Simulation time 43794328 ps
CPU time 1.12 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:07 PM PDT 24
Peak memory 196824 kb
Host smart-db0c2386-8cd1-452d-89dc-ffb4b481af2c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273669894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1273669894
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1032863608
Short name T306
Test name
Test status
Simulation time 385090409 ps
CPU time 1.35 seconds
Started May 14 01:15:58 PM PDT 24
Finished May 14 01:16:03 PM PDT 24
Peak memory 197960 kb
Host smart-57bdb9ad-6d86-4052-b7f6-87647c56b690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032863608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1032863608
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3354518894
Short name T653
Test name
Test status
Simulation time 92501008 ps
CPU time 0.84 seconds
Started May 14 01:15:46 PM PDT 24
Finished May 14 01:15:53 PM PDT 24
Peak memory 197052 kb
Host smart-649dc585-db6b-4e9e-a7d2-715c1d131d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354518894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3354518894
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.3779812233
Short name T262
Test name
Test status
Simulation time 99001361 ps
CPU time 0.85 seconds
Started May 14 01:16:14 PM PDT 24
Finished May 14 01:16:18 PM PDT 24
Peak memory 195436 kb
Host smart-2c864c6e-cc8e-4420-a01d-65a134b72de1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779812233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.3779812233
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1701886318
Short name T457
Test name
Test status
Simulation time 19477507581 ps
CPU time 49.58 seconds
Started May 14 01:15:50 PM PDT 24
Finished May 14 01:16:45 PM PDT 24
Peak memory 198180 kb
Host smart-519d34b9-23f9-4f22-9408-e9c30721c5f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701886318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1701886318
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.4262933083
Short name T61
Test name
Test status
Simulation time 38037969479 ps
CPU time 894.13 seconds
Started May 14 01:15:57 PM PDT 24
Finished May 14 01:30:55 PM PDT 24
Peak memory 198200 kb
Host smart-f41913cb-80ce-49a9-9836-ccae1fba8531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4262933083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.4262933083
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3684844007
Short name T703
Test name
Test status
Simulation time 51234782 ps
CPU time 0.63 seconds
Started May 14 01:15:57 PM PDT 24
Finished May 14 01:16:02 PM PDT 24
Peak memory 194764 kb
Host smart-b0657f9c-4a98-4677-9a10-81732460224b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684844007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3684844007
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.591227950
Short name T578
Test name
Test status
Simulation time 53318514 ps
CPU time 0.62 seconds
Started May 14 01:16:08 PM PDT 24
Finished May 14 01:16:11 PM PDT 24
Peak memory 194056 kb
Host smart-d46467e7-206f-466a-9604-28cf037d232b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591227950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.591227950
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3998099160
Short name T454
Test name
Test status
Simulation time 356557540 ps
CPU time 6.87 seconds
Started May 14 01:15:52 PM PDT 24
Finished May 14 01:16:04 PM PDT 24
Peak memory 196676 kb
Host smart-ea9b5f41-2fb1-4cb1-a741-c39ace09d956
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998099160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3998099160
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.487601289
Short name T377
Test name
Test status
Simulation time 77260700 ps
CPU time 0.64 seconds
Started May 14 01:16:05 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 195332 kb
Host smart-cc3a3428-904b-49c4-8b48-51c35bba67c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487601289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.487601289
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.3585882434
Short name T18
Test name
Test status
Simulation time 274533512 ps
CPU time 1.15 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:04 PM PDT 24
Peak memory 195772 kb
Host smart-3e1ad9d5-a166-4ed6-a9e6-2407004624cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585882434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.3585882434
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.4032265376
Short name T275
Test name
Test status
Simulation time 43570401 ps
CPU time 1.29 seconds
Started May 14 01:15:53 PM PDT 24
Finished May 14 01:15:59 PM PDT 24
Peak memory 198076 kb
Host smart-95dabde4-da4e-48ef-80a8-78a1e9f90560
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032265376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.4032265376
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1589556463
Short name T321
Test name
Test status
Simulation time 110826011 ps
CPU time 2.29 seconds
Started May 14 01:16:08 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 196676 kb
Host smart-72f865de-b8d6-4da1-8041-3c8d6b94883a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589556463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1589556463
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3657136305
Short name T131
Test name
Test status
Simulation time 160918514 ps
CPU time 1.23 seconds
Started May 14 01:15:52 PM PDT 24
Finished May 14 01:15:58 PM PDT 24
Peak memory 196828 kb
Host smart-ebbaddf0-f712-41e9-b49f-5da162f6f513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657136305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3657136305
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3164156436
Short name T491
Test name
Test status
Simulation time 30009402 ps
CPU time 1 seconds
Started May 14 01:16:03 PM PDT 24
Finished May 14 01:16:08 PM PDT 24
Peak memory 196696 kb
Host smart-dba932f0-219a-49e3-b581-92c7113b9859
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164156436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3164156436
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2468889635
Short name T640
Test name
Test status
Simulation time 2088922816 ps
CPU time 5.54 seconds
Started May 14 01:15:52 PM PDT 24
Finished May 14 01:16:03 PM PDT 24
Peak memory 198020 kb
Host smart-c781d9dd-45fc-40a8-9eb8-1247ebda8fff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468889635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2468889635
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1248253157
Short name T203
Test name
Test status
Simulation time 482643584 ps
CPU time 1.15 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:04 PM PDT 24
Peak memory 196492 kb
Host smart-7bf9135c-5f86-4cce-9083-feae82481144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248253157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1248253157
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2269112987
Short name T274
Test name
Test status
Simulation time 32593577 ps
CPU time 0.93 seconds
Started May 14 01:15:54 PM PDT 24
Finished May 14 01:15:59 PM PDT 24
Peak memory 196464 kb
Host smart-20203165-372e-4760-aeae-1d5caaccd849
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269112987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2269112987
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1718876320
Short name T316
Test name
Test status
Simulation time 24559659882 ps
CPU time 188.75 seconds
Started May 14 01:16:05 PM PDT 24
Finished May 14 01:19:17 PM PDT 24
Peak memory 198176 kb
Host smart-23469a4c-e58d-4f1b-abfd-a53705156a24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718876320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1718876320
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2239711796
Short name T532
Test name
Test status
Simulation time 30282436 ps
CPU time 0.6 seconds
Started May 14 01:14:49 PM PDT 24
Finished May 14 01:14:53 PM PDT 24
Peak memory 193904 kb
Host smart-d75abc5c-d7d6-46e1-ab8b-b400c9a48849
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239711796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2239711796
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2185757797
Short name T182
Test name
Test status
Simulation time 527149724 ps
CPU time 0.82 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 196056 kb
Host smart-bb41cd0d-7804-4999-a9dd-034501ca6556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185757797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2185757797
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1492802953
Short name T118
Test name
Test status
Simulation time 3172264827 ps
CPU time 19.01 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:15:10 PM PDT 24
Peak memory 197088 kb
Host smart-35866550-25c3-4e9b-9fec-aa602e9caf17
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492802953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1492802953
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3644215861
Short name T692
Test name
Test status
Simulation time 52272168 ps
CPU time 0.7 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:51 PM PDT 24
Peak memory 195248 kb
Host smart-7d2f87dd-ca1a-419e-8191-b2477502ec9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644215861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3644215861
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2704052290
Short name T409
Test name
Test status
Simulation time 48986627 ps
CPU time 1.23 seconds
Started May 14 01:14:45 PM PDT 24
Finished May 14 01:14:49 PM PDT 24
Peak memory 196904 kb
Host smart-02ce8398-3a3d-4d22-90c5-a3a7cf45d71b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704052290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2704052290
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.3361063939
Short name T226
Test name
Test status
Simulation time 101637389 ps
CPU time 1.19 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:50 PM PDT 24
Peak memory 196792 kb
Host smart-c414e95a-e643-4bb6-8db6-5e2aa26715ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361063939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.3361063939
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.643287723
Short name T151
Test name
Test status
Simulation time 144345405 ps
CPU time 2.27 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 195804 kb
Host smart-953568c7-ccb3-4202-8e5c-a40555c4e602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643287723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.643287723
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3553863368
Short name T443
Test name
Test status
Simulation time 43557853 ps
CPU time 0.65 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:50 PM PDT 24
Peak memory 194424 kb
Host smart-16689ace-6e0d-4248-9c1f-f2a35476ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553863368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3553863368
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3560595452
Short name T298
Test name
Test status
Simulation time 69912107 ps
CPU time 1.44 seconds
Started May 14 01:14:49 PM PDT 24
Finished May 14 01:14:54 PM PDT 24
Peak memory 197000 kb
Host smart-98edb2f9-2350-43e5-807d-86f909c7435b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560595452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3560595452
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1281020509
Short name T234
Test name
Test status
Simulation time 1749086238 ps
CPU time 3.1 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:48 PM PDT 24
Peak memory 197992 kb
Host smart-e76bd569-8fa6-4b55-81bc-48c84622f84f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281020509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1281020509
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3850297634
Short name T39
Test name
Test status
Simulation time 114950280 ps
CPU time 0.87 seconds
Started May 14 01:14:44 PM PDT 24
Finished May 14 01:14:47 PM PDT 24
Peak memory 213688 kb
Host smart-43f79ce5-4b00-4c9d-8c41-44da2047f5bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850297634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3850297634
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1627806659
Short name T184
Test name
Test status
Simulation time 130483542 ps
CPU time 1.31 seconds
Started May 14 01:14:51 PM PDT 24
Finished May 14 01:14:57 PM PDT 24
Peak memory 198008 kb
Host smart-6d68f934-870b-43ef-921e-1823dce6124b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627806659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1627806659
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2041224820
Short name T114
Test name
Test status
Simulation time 64726684 ps
CPU time 1.11 seconds
Started May 14 01:14:41 PM PDT 24
Finished May 14 01:14:44 PM PDT 24
Peak memory 195724 kb
Host smart-e86c59cc-b5c0-413d-a5fe-87d1dd5cbca7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041224820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2041224820
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.128928528
Short name T538
Test name
Test status
Simulation time 5918765020 ps
CPU time 33.17 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:15:26 PM PDT 24
Peak memory 198020 kb
Host smart-dbc176a0-1893-487b-b879-bb86ea9e6a91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128928528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gp
io_stress_all.128928528
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.4133884401
Short name T32
Test name
Test status
Simulation time 37984943727 ps
CPU time 1072.81 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:32:41 PM PDT 24
Peak memory 198208 kb
Host smart-834fe5c6-aec2-40b6-9aae-1af26b9fb6d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4133884401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.4133884401
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2964636515
Short name T26
Test name
Test status
Simulation time 24538912 ps
CPU time 0.57 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:07 PM PDT 24
Peak memory 193864 kb
Host smart-0e9cdd7a-7c91-4b2b-99e3-9e4d46115f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964636515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2964636515
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1286977109
Short name T186
Test name
Test status
Simulation time 67859111 ps
CPU time 0.66 seconds
Started May 14 01:16:05 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 194088 kb
Host smart-b6a00294-7bcf-423c-a67c-3430ccab9963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286977109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1286977109
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3617916953
Short name T359
Test name
Test status
Simulation time 620141237 ps
CPU time 21.78 seconds
Started May 14 01:16:04 PM PDT 24
Finished May 14 01:16:29 PM PDT 24
Peak memory 196812 kb
Host smart-890fd21f-b6dd-4546-a0a5-1d457463afe5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617916953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3617916953
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3397041191
Short name T689
Test name
Test status
Simulation time 106294382 ps
CPU time 0.66 seconds
Started May 14 01:15:53 PM PDT 24
Finished May 14 01:15:58 PM PDT 24
Peak memory 195584 kb
Host smart-68598dda-2601-4c6c-9e63-6f0a5a025025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397041191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3397041191
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.135458644
Short name T615
Test name
Test status
Simulation time 289031132 ps
CPU time 0.86 seconds
Started May 14 01:15:51 PM PDT 24
Finished May 14 01:15:57 PM PDT 24
Peak memory 195672 kb
Host smart-7956fa69-5f39-48e8-97bb-2b6f11e8fb7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135458644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.135458644
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2733067692
Short name T194
Test name
Test status
Simulation time 118938489 ps
CPU time 2.4 seconds
Started May 14 01:15:57 PM PDT 24
Finished May 14 01:16:03 PM PDT 24
Peak memory 198044 kb
Host smart-cec46c10-4671-42a4-9dcc-554df1379655
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733067692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2733067692
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2457224020
Short name T227
Test name
Test status
Simulation time 167235547 ps
CPU time 3.45 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 198044 kb
Host smart-2d98a928-952c-4166-a865-c0a944242b97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457224020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2457224020
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.844801144
Short name T191
Test name
Test status
Simulation time 30373286 ps
CPU time 0.88 seconds
Started May 14 01:15:54 PM PDT 24
Finished May 14 01:15:59 PM PDT 24
Peak memory 196172 kb
Host smart-4a91956c-925b-48e5-bc99-6f9a6a8946fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844801144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.844801144
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2756017569
Short name T200
Test name
Test status
Simulation time 382256002 ps
CPU time 1.09 seconds
Started May 14 01:15:57 PM PDT 24
Finished May 14 01:16:06 PM PDT 24
Peak memory 196796 kb
Host smart-98ab6560-79b5-41d3-b182-da839b71da09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756017569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2756017569
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3175227319
Short name T606
Test name
Test status
Simulation time 86141778 ps
CPU time 2.23 seconds
Started May 14 01:15:55 PM PDT 24
Finished May 14 01:16:01 PM PDT 24
Peak memory 197968 kb
Host smart-7e9f1ea3-5261-4d70-8654-6c4052aa8f99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175227319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3175227319
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1877296395
Short name T160
Test name
Test status
Simulation time 25543140 ps
CPU time 0.83 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 195160 kb
Host smart-77b4c523-ded5-465b-9c1d-3e0326978546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877296395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1877296395
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.959045767
Short name T165
Test name
Test status
Simulation time 97060941 ps
CPU time 1.27 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:03 PM PDT 24
Peak memory 196504 kb
Host smart-01a01f4a-838d-4211-8676-7f90a0674f1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959045767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.959045767
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1470043018
Short name T7
Test name
Test status
Simulation time 4124430939 ps
CPU time 40.37 seconds
Started May 14 01:15:54 PM PDT 24
Finished May 14 01:16:39 PM PDT 24
Peak memory 198096 kb
Host smart-46a2137d-ef98-4b0a-b167-f6f298cedaf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470043018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1470043018
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3082629961
Short name T463
Test name
Test status
Simulation time 56271218 ps
CPU time 0.58 seconds
Started May 14 01:15:58 PM PDT 24
Finished May 14 01:16:02 PM PDT 24
Peak memory 193888 kb
Host smart-12c021af-3d08-48bb-984f-08588d055ed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082629961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3082629961
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.554340565
Short name T682
Test name
Test status
Simulation time 112057396 ps
CPU time 0.9 seconds
Started May 14 01:15:56 PM PDT 24
Finished May 14 01:16:01 PM PDT 24
Peak memory 195968 kb
Host smart-91bd8a03-8122-4b9e-9d0a-1ebe6443f3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554340565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.554340565
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.27859877
Short name T601
Test name
Test status
Simulation time 240662409 ps
CPU time 12.95 seconds
Started May 14 01:16:07 PM PDT 24
Finished May 14 01:16:23 PM PDT 24
Peak memory 196464 kb
Host smart-5c153a3f-208b-4da2-9e91-9cfed021f534
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27859877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stress
.27859877
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1920982302
Short name T533
Test name
Test status
Simulation time 50889153 ps
CPU time 0.82 seconds
Started May 14 01:16:04 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 196008 kb
Host smart-c13b1fcf-9de4-4644-92fd-807f1c3128ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920982302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1920982302
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3418633768
Short name T499
Test name
Test status
Simulation time 116664923 ps
CPU time 1.29 seconds
Started May 14 01:16:07 PM PDT 24
Finished May 14 01:16:11 PM PDT 24
Peak memory 196096 kb
Host smart-df9e9b59-9f55-4fea-be83-442f951aa6a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418633768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3418633768
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3330897239
Short name T251
Test name
Test status
Simulation time 172822117 ps
CPU time 2.6 seconds
Started May 14 01:15:53 PM PDT 24
Finished May 14 01:16:00 PM PDT 24
Peak memory 197984 kb
Host smart-5abe8ac2-2be1-4c6c-9ff0-1c247a1220c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330897239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3330897239
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3233621046
Short name T380
Test name
Test status
Simulation time 312848002 ps
CPU time 3.1 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:08 PM PDT 24
Peak memory 198072 kb
Host smart-ca3e6515-9e98-4326-a9db-f912eff8954f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233621046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3233621046
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1014366759
Short name T546
Test name
Test status
Simulation time 122500824 ps
CPU time 1.21 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:07 PM PDT 24
Peak memory 195712 kb
Host smart-83780c25-8ade-4dd1-a748-2f8c4be61fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014366759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1014366759
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3986118618
Short name T513
Test name
Test status
Simulation time 37703757 ps
CPU time 0.9 seconds
Started May 14 01:16:12 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 197336 kb
Host smart-de575761-e1fc-46b1-b064-de514472a972
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986118618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3986118618
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.49287702
Short name T246
Test name
Test status
Simulation time 8263051961 ps
CPU time 6.1 seconds
Started May 14 01:15:54 PM PDT 24
Finished May 14 01:16:04 PM PDT 24
Peak memory 198084 kb
Host smart-f9df4f98-5a22-4b47-ad95-fd1fa3f32948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49287702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand
om_long_reg_writes_reg_reads.49287702
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3415381505
Short name T312
Test name
Test status
Simulation time 269219561 ps
CPU time 1.28 seconds
Started May 14 01:16:07 PM PDT 24
Finished May 14 01:16:11 PM PDT 24
Peak memory 196564 kb
Host smart-24a03298-2e5c-4dd1-a5f2-4ff003d7f525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415381505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3415381505
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.826940380
Short name T328
Test name
Test status
Simulation time 142316463 ps
CPU time 1.13 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:08 PM PDT 24
Peak memory 195532 kb
Host smart-8586fe4b-4312-4935-ba39-6561dad9229e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826940380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.826940380
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.647060485
Short name T433
Test name
Test status
Simulation time 3019401686 ps
CPU time 30.11 seconds
Started May 14 01:15:53 PM PDT 24
Finished May 14 01:16:28 PM PDT 24
Peak memory 198152 kb
Host smart-28215b57-8282-4a77-a4b1-bfff3f20ce68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647060485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.647060485
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.4251424718
Short name T63
Test name
Test status
Simulation time 53200644753 ps
CPU time 1439.35 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:40:06 PM PDT 24
Peak memory 198240 kb
Host smart-aa40d35f-1799-46bf-a0fa-fbe27de3eca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4251424718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.4251424718
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.175420431
Short name T128
Test name
Test status
Simulation time 36136715 ps
CPU time 0.6 seconds
Started May 14 01:16:12 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 194568 kb
Host smart-7ece3ecd-907c-4243-9f33-b49432382776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175420431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.175420431
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1603136094
Short name T455
Test name
Test status
Simulation time 285815948 ps
CPU time 0.81 seconds
Started May 14 01:16:05 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 195348 kb
Host smart-676b8f62-22cd-4871-a7d3-12a2c4c5bbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603136094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1603136094
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4111816612
Short name T134
Test name
Test status
Simulation time 344841524 ps
CPU time 3.05 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:16:07 PM PDT 24
Peak memory 195464 kb
Host smart-1d2ba6b7-4424-41db-b5c3-da40baebe98d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111816612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4111816612
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3178746409
Short name T461
Test name
Test status
Simulation time 142367645 ps
CPU time 0.73 seconds
Started May 14 01:16:13 PM PDT 24
Finished May 14 01:16:17 PM PDT 24
Peak memory 195824 kb
Host smart-d47aaad1-7523-4abc-9711-5362dd67f3d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178746409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3178746409
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1014983065
Short name T391
Test name
Test status
Simulation time 53026062 ps
CPU time 1.07 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:16:06 PM PDT 24
Peak memory 195944 kb
Host smart-608037b9-76aa-4067-8bd4-95b6c2d2d5eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014983065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1014983065
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3168200802
Short name T553
Test name
Test status
Simulation time 76982125 ps
CPU time 3.24 seconds
Started May 14 01:15:58 PM PDT 24
Finished May 14 01:16:05 PM PDT 24
Peak memory 198108 kb
Host smart-8fa7675c-414e-45f7-8e55-98e348be04b8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168200802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3168200802
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2471953720
Short name T524
Test name
Test status
Simulation time 261410179 ps
CPU time 1.7 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:04 PM PDT 24
Peak memory 196136 kb
Host smart-d7a59c4a-57dc-45f7-b191-272eb34aa522
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471953720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2471953720
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3212223168
Short name T618
Test name
Test status
Simulation time 179740352 ps
CPU time 1.02 seconds
Started May 14 01:16:06 PM PDT 24
Finished May 14 01:16:10 PM PDT 24
Peak memory 195960 kb
Host smart-0669ee5e-b3f8-49c3-89b7-371a92493637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212223168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3212223168
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1562668405
Short name T357
Test name
Test status
Simulation time 184234505 ps
CPU time 0.87 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:03 PM PDT 24
Peak memory 196008 kb
Host smart-5977d32a-3895-44b7-a31e-03a36af8742c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562668405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1562668405
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.4134383424
Short name T202
Test name
Test status
Simulation time 1787867537 ps
CPU time 7.41 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 198088 kb
Host smart-428c6961-b182-4978-bb21-b664e317c7e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134383424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.4134383424
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1719822656
Short name T696
Test name
Test status
Simulation time 157905628 ps
CPU time 0.96 seconds
Started May 14 01:15:53 PM PDT 24
Finished May 14 01:15:58 PM PDT 24
Peak memory 195648 kb
Host smart-097916dc-fca5-4223-bdd5-e682bd686113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719822656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1719822656
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.2107207079
Short name T260
Test name
Test status
Simulation time 157162968 ps
CPU time 1 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:03 PM PDT 24
Peak memory 197244 kb
Host smart-87388847-1488-4afd-8dc4-6758ae5fb9f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107207079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.2107207079
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2006975600
Short name T224
Test name
Test status
Simulation time 4672131311 ps
CPU time 121.26 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:18:13 PM PDT 24
Peak memory 198240 kb
Host smart-8a8fe6d1-1df9-4b9f-ba77-c647d5049dc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006975600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2006975600
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2019711295
Short name T30
Test name
Test status
Simulation time 16553439112 ps
CPU time 510.39 seconds
Started May 14 01:16:00 PM PDT 24
Finished May 14 01:24:34 PM PDT 24
Peak memory 198200 kb
Host smart-43e70fd9-ee6f-4bbb-a547-efa447aa8dd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2019711295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2019711295
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2760172504
Short name T624
Test name
Test status
Simulation time 36243269 ps
CPU time 0.58 seconds
Started May 14 01:16:27 PM PDT 24
Finished May 14 01:16:29 PM PDT 24
Peak memory 194560 kb
Host smart-0498dd84-449c-4e92-852e-b865ce03af84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760172504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2760172504
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.1930172254
Short name T559
Test name
Test status
Simulation time 116641574 ps
CPU time 0.86 seconds
Started May 14 01:16:20 PM PDT 24
Finished May 14 01:16:22 PM PDT 24
Peak memory 195272 kb
Host smart-bcdb9070-6af6-4146-bcec-ceefa05ba032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930172254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.1930172254
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2505103256
Short name T310
Test name
Test status
Simulation time 1415175681 ps
CPU time 18.82 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:24 PM PDT 24
Peak memory 195460 kb
Host smart-4d2bbc86-d9ad-4e67-a65a-51d1cb5e09ba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505103256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2505103256
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1726008015
Short name T448
Test name
Test status
Simulation time 88136251 ps
CPU time 0.91 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:16:12 PM PDT 24
Peak memory 197208 kb
Host smart-267fab4b-f3ae-48e2-9843-09b8f043df3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726008015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1726008015
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3317018816
Short name T584
Test name
Test status
Simulation time 71888298 ps
CPU time 0.66 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 195348 kb
Host smart-647c6f4c-4b65-44c3-9a57-8dd7f9277f38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317018816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3317018816
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.616785255
Short name T362
Test name
Test status
Simulation time 54760592 ps
CPU time 2.18 seconds
Started May 14 01:16:21 PM PDT 24
Finished May 14 01:16:25 PM PDT 24
Peak memory 198084 kb
Host smart-aab9e2cf-ac68-4f1f-8fda-653251c746d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616785255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.616785255
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.1375859725
Short name T558
Test name
Test status
Simulation time 179225442 ps
CPU time 1.88 seconds
Started May 14 01:16:08 PM PDT 24
Finished May 14 01:16:12 PM PDT 24
Peak memory 195772 kb
Host smart-d275ce3c-1b5b-45ed-821b-89ea1f09f907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375859725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.1375859725
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3943352406
Short name T205
Test name
Test status
Simulation time 35381610 ps
CPU time 1.24 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:16:06 PM PDT 24
Peak memory 196940 kb
Host smart-a5ad5728-665a-47d6-9d65-d916d5e7055f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943352406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3943352406
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2914809633
Short name T561
Test name
Test status
Simulation time 31857059 ps
CPU time 0.85 seconds
Started May 14 01:16:10 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 195984 kb
Host smart-c1c43b8e-699d-4948-87d4-231f72150c11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914809633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2914809633
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.2855756450
Short name T620
Test name
Test status
Simulation time 62479591 ps
CPU time 1.54 seconds
Started May 14 01:16:03 PM PDT 24
Finished May 14 01:16:08 PM PDT 24
Peak memory 197664 kb
Host smart-32610e79-4677-474d-9b43-d52df52b32de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855756450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.2855756450
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.185910161
Short name T517
Test name
Test status
Simulation time 63889062 ps
CPU time 0.96 seconds
Started May 14 01:16:04 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 195772 kb
Host smart-334b94ff-c9bb-4e56-b420-02275d05bb4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185910161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.185910161
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3589517592
Short name T531
Test name
Test status
Simulation time 28801564 ps
CPU time 0.95 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:07 PM PDT 24
Peak memory 197264 kb
Host smart-2cfda59b-fd61-4cd2-a887-1f5d431b6cf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589517592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3589517592
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.154731883
Short name T657
Test name
Test status
Simulation time 38503204556 ps
CPU time 89.71 seconds
Started May 14 01:16:16 PM PDT 24
Finished May 14 01:17:48 PM PDT 24
Peak memory 198164 kb
Host smart-f4f0fe42-7e23-436a-a341-2d80a65c57da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154731883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.154731883
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1379450878
Short name T593
Test name
Test status
Simulation time 13951767 ps
CPU time 0.61 seconds
Started May 14 01:16:02 PM PDT 24
Finished May 14 01:16:06 PM PDT 24
Peak memory 193880 kb
Host smart-37e5199e-0d23-48d1-b895-43fbf6ddc2c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379450878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1379450878
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2347539050
Short name T430
Test name
Test status
Simulation time 51631157 ps
CPU time 0.91 seconds
Started May 14 01:16:14 PM PDT 24
Finished May 14 01:16:17 PM PDT 24
Peak memory 196644 kb
Host smart-d14fd04d-a5d3-4bf9-8ac3-871f9dca898d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347539050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2347539050
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3497051446
Short name T591
Test name
Test status
Simulation time 3674362383 ps
CPU time 27.62 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:30 PM PDT 24
Peak memory 196820 kb
Host smart-e60f47a1-3bdb-4385-b397-db9564763b6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497051446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3497051446
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.732644095
Short name T211
Test name
Test status
Simulation time 255311540 ps
CPU time 1.01 seconds
Started May 14 01:16:19 PM PDT 24
Finished May 14 01:16:21 PM PDT 24
Peak memory 197880 kb
Host smart-250179c9-252c-40e5-8461-a7ec0caf5740
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732644095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.732644095
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1806965332
Short name T336
Test name
Test status
Simulation time 37731876 ps
CPU time 1.11 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:16:06 PM PDT 24
Peak memory 196072 kb
Host smart-4af4e799-0c22-43f1-8a11-49c2311e6d73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806965332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1806965332
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.4185734067
Short name T670
Test name
Test status
Simulation time 375762142 ps
CPU time 3.43 seconds
Started May 14 01:16:03 PM PDT 24
Finished May 14 01:16:11 PM PDT 24
Peak memory 198024 kb
Host smart-fccc8a5f-7096-4426-9c31-cb4cb9e0273f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185734067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.4185734067
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.758379237
Short name T417
Test name
Test status
Simulation time 330551332 ps
CPU time 2.41 seconds
Started May 14 01:16:16 PM PDT 24
Finished May 14 01:16:20 PM PDT 24
Peak memory 196956 kb
Host smart-2fe5994d-2b01-4064-ba0d-95a6adacf598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758379237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
758379237
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1605789098
Short name T378
Test name
Test status
Simulation time 23845526 ps
CPU time 0.78 seconds
Started May 14 01:16:23 PM PDT 24
Finished May 14 01:16:26 PM PDT 24
Peak memory 196008 kb
Host smart-0291ec8c-8d34-4128-ac70-155bea5f70d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605789098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1605789098
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3106411142
Short name T235
Test name
Test status
Simulation time 202867596 ps
CPU time 1.07 seconds
Started May 14 01:16:03 PM PDT 24
Finished May 14 01:16:08 PM PDT 24
Peak memory 196052 kb
Host smart-b8f56ea3-0c62-446f-91d0-c8ce27369df2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106411142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3106411142
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.4281288551
Short name T462
Test name
Test status
Simulation time 170237515 ps
CPU time 2.34 seconds
Started May 14 01:16:10 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 197940 kb
Host smart-1aace251-ca69-43ee-b8de-b48f6d2b55ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281288551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.4281288551
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3400956374
Short name T598
Test name
Test status
Simulation time 53957082 ps
CPU time 1.02 seconds
Started May 14 01:16:12 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 195580 kb
Host smart-921afd7e-aff5-42f8-a56f-54bafd02ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400956374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3400956374
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.4116207166
Short name T268
Test name
Test status
Simulation time 201115473 ps
CPU time 1.25 seconds
Started May 14 01:16:07 PM PDT 24
Finished May 14 01:16:11 PM PDT 24
Peak memory 195688 kb
Host smart-e42ad113-5e58-4254-a251-da77f23598f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116207166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.4116207166
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.4157624503
Short name T494
Test name
Test status
Simulation time 13371423484 ps
CPU time 168.33 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:19:00 PM PDT 24
Peak memory 198184 kb
Host smart-d66ee9e9-d370-42bf-8a85-ed081d36c197
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157624503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.4157624503
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1342800525
Short name T474
Test name
Test status
Simulation time 50282324 ps
CPU time 0.61 seconds
Started May 14 01:16:11 PM PDT 24
Finished May 14 01:16:15 PM PDT 24
Peak memory 193876 kb
Host smart-9128b79f-6854-4646-9e20-1757bab9297e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342800525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1342800525
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3300537469
Short name T408
Test name
Test status
Simulation time 41718858 ps
CPU time 0.93 seconds
Started May 14 01:16:20 PM PDT 24
Finished May 14 01:16:22 PM PDT 24
Peak memory 195424 kb
Host smart-0aaeaae9-cfa2-467c-a9cd-40038a3dd3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300537469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3300537469
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.692036632
Short name T625
Test name
Test status
Simulation time 326953228 ps
CPU time 10.88 seconds
Started May 14 01:16:14 PM PDT 24
Finished May 14 01:16:28 PM PDT 24
Peak memory 196980 kb
Host smart-83578546-706b-4be0-970d-c28236d25d23
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692036632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.692036632
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.893524241
Short name T599
Test name
Test status
Simulation time 454091016 ps
CPU time 0.82 seconds
Started May 14 01:16:15 PM PDT 24
Finished May 14 01:16:18 PM PDT 24
Peak memory 195972 kb
Host smart-f99cbedf-7ba3-4e84-9c1b-896221c3561d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893524241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.893524241
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1438586858
Short name T247
Test name
Test status
Simulation time 164410882 ps
CPU time 1.24 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:16:05 PM PDT 24
Peak memory 198020 kb
Host smart-0ac08fc1-0168-4e98-a8a8-081c5a3c96f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438586858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1438586858
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1021367426
Short name T395
Test name
Test status
Simulation time 75612139 ps
CPU time 1.07 seconds
Started May 14 01:16:21 PM PDT 24
Finished May 14 01:16:24 PM PDT 24
Peak memory 197516 kb
Host smart-c2bf6454-7ba0-47de-88a8-ff2998c88a5d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021367426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1021367426
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2953625880
Short name T253
Test name
Test status
Simulation time 81521587 ps
CPU time 1.6 seconds
Started May 14 01:16:01 PM PDT 24
Finished May 14 01:16:06 PM PDT 24
Peak memory 195748 kb
Host smart-c364b3b6-0d64-4b81-8578-dd46a9fecbe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953625880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2953625880
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3682343090
Short name T379
Test name
Test status
Simulation time 187748152 ps
CPU time 0.84 seconds
Started May 14 01:16:03 PM PDT 24
Finished May 14 01:16:07 PM PDT 24
Peak memory 196556 kb
Host smart-eb96d3ab-54de-4019-a369-c0a0127b2e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682343090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3682343090
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3054688266
Short name T542
Test name
Test status
Simulation time 201730519 ps
CPU time 1.33 seconds
Started May 14 01:16:21 PM PDT 24
Finished May 14 01:16:24 PM PDT 24
Peak memory 196952 kb
Host smart-a7df2400-c477-4a99-aebc-07767c185c97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054688266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3054688266
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2714574999
Short name T708
Test name
Test status
Simulation time 138379227 ps
CPU time 1.94 seconds
Started May 14 01:16:12 PM PDT 24
Finished May 14 01:16:17 PM PDT 24
Peak memory 197896 kb
Host smart-5c8bb2be-3635-49c0-badb-71d0b4a24e01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714574999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2714574999
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1213351543
Short name T699
Test name
Test status
Simulation time 39943838 ps
CPU time 1.24 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 195824 kb
Host smart-b8b5efa5-6796-45e4-a8f7-8300c7c0881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213351543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1213351543
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3818867600
Short name T178
Test name
Test status
Simulation time 187049269 ps
CPU time 1.36 seconds
Started May 14 01:16:22 PM PDT 24
Finished May 14 01:16:26 PM PDT 24
Peak memory 196656 kb
Host smart-e76c260b-70dc-4bd3-97bb-b8ef53dd4750
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818867600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3818867600
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.717057234
Short name T701
Test name
Test status
Simulation time 32292488866 ps
CPU time 178.58 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:19:11 PM PDT 24
Peak memory 198152 kb
Host smart-e54d7d18-7dfd-401f-a657-60300482d292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717057234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.717057234
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3630108846
Short name T241
Test name
Test status
Simulation time 22939833 ps
CPU time 0.59 seconds
Started May 14 01:16:17 PM PDT 24
Finished May 14 01:16:19 PM PDT 24
Peak memory 193856 kb
Host smart-3468a835-64a0-4130-84c0-5200fa37d88b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630108846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3630108846
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.490091479
Short name T398
Test name
Test status
Simulation time 37624191 ps
CPU time 0.78 seconds
Started May 14 01:16:12 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 195248 kb
Host smart-d5b60435-dde6-498e-8c60-6a390de4f4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490091479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.490091479
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1792102634
Short name T56
Test name
Test status
Simulation time 143529522 ps
CPU time 3.45 seconds
Started May 14 01:16:10 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 195708 kb
Host smart-c65d2547-ace8-4049-afb9-2f3fdc3188a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792102634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1792102634
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.997568967
Short name T170
Test name
Test status
Simulation time 359067521 ps
CPU time 1.09 seconds
Started May 14 01:16:13 PM PDT 24
Finished May 14 01:16:17 PM PDT 24
Peak memory 196584 kb
Host smart-26f5668f-a6a7-4885-b9a1-8c7364996a17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997568967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.997568967
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.4059732820
Short name T519
Test name
Test status
Simulation time 228100559 ps
CPU time 1.04 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 195788 kb
Host smart-53a376a3-a0be-46c5-9984-4bbdd22aea1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059732820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.4059732820
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.789304096
Short name T488
Test name
Test status
Simulation time 592555992 ps
CPU time 2.51 seconds
Started May 14 01:16:03 PM PDT 24
Finished May 14 01:16:09 PM PDT 24
Peak memory 198108 kb
Host smart-d25bd8c1-df49-4dd1-b511-02cc8b34d6fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789304096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.789304096
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1877777342
Short name T113
Test name
Test status
Simulation time 196783155 ps
CPU time 3.35 seconds
Started May 14 01:16:11 PM PDT 24
Finished May 14 01:16:18 PM PDT 24
Peak memory 198048 kb
Host smart-d49e4a02-1192-4ab7-8aff-b4cee0248a49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877777342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1877777342
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.4155248018
Short name T605
Test name
Test status
Simulation time 49138176 ps
CPU time 1.01 seconds
Started May 14 01:16:10 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 195864 kb
Host smart-e2a6fcec-1626-4da2-9240-eb2f733e232f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155248018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.4155248018
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.1401145090
Short name T650
Test name
Test status
Simulation time 28164125 ps
CPU time 0.92 seconds
Started May 14 01:16:10 PM PDT 24
Finished May 14 01:16:14 PM PDT 24
Peak memory 195952 kb
Host smart-01f6f330-ff77-47d9-8833-a1127e93cdba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401145090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.1401145090
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4101921335
Short name T155
Test name
Test status
Simulation time 516184120 ps
CPU time 4.58 seconds
Started May 14 01:16:11 PM PDT 24
Finished May 14 01:16:18 PM PDT 24
Peak memory 197916 kb
Host smart-d4e4540c-e8e6-48db-a7db-6dbe28bf033a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101921335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4101921335
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3662889369
Short name T464
Test name
Test status
Simulation time 135401956 ps
CPU time 1.02 seconds
Started May 14 01:15:59 PM PDT 24
Finished May 14 01:16:04 PM PDT 24
Peak memory 195868 kb
Host smart-3c7ca731-c369-44d3-9e98-8694c9a2a46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662889369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3662889369
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1758631976
Short name T119
Test name
Test status
Simulation time 56257940 ps
CPU time 0.84 seconds
Started May 14 01:16:11 PM PDT 24
Finished May 14 01:16:15 PM PDT 24
Peak memory 197116 kb
Host smart-aa542d52-b99c-4347-8f8b-d3cab0e2e3da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758631976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1758631976
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.578353872
Short name T617
Test name
Test status
Simulation time 16017878799 ps
CPU time 85.98 seconds
Started May 14 01:16:10 PM PDT 24
Finished May 14 01:17:39 PM PDT 24
Peak memory 198056 kb
Host smart-7d76ddd6-05c7-4434-a1e9-cc1cd7cf5040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578353872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.578353872
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2940043194
Short name T242
Test name
Test status
Simulation time 23382967 ps
CPU time 0.61 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:16:12 PM PDT 24
Peak memory 194108 kb
Host smart-ab5c6a0d-ec98-480e-bfd1-65a25df3487f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940043194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2940043194
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2187325731
Short name T289
Test name
Test status
Simulation time 26357120 ps
CPU time 0.62 seconds
Started May 14 01:16:24 PM PDT 24
Finished May 14 01:16:26 PM PDT 24
Peak memory 193976 kb
Host smart-ba14da54-fa66-43a4-a179-63834612c261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187325731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2187325731
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2874016784
Short name T429
Test name
Test status
Simulation time 3273853430 ps
CPU time 21.95 seconds
Started May 14 01:16:22 PM PDT 24
Finished May 14 01:16:46 PM PDT 24
Peak memory 196868 kb
Host smart-79c2ed61-3d3f-46b2-9a44-9fae4cc7ae39
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874016784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2874016784
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3343957146
Short name T341
Test name
Test status
Simulation time 61547870 ps
CPU time 0.79 seconds
Started May 14 01:16:20 PM PDT 24
Finished May 14 01:16:22 PM PDT 24
Peak memory 195816 kb
Host smart-5f2a8084-d0af-4c22-a4c4-e9a02eccbb13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343957146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3343957146
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.794775097
Short name T137
Test name
Test status
Simulation time 44110598 ps
CPU time 0.74 seconds
Started May 14 01:16:11 PM PDT 24
Finished May 14 01:16:15 PM PDT 24
Peak memory 195032 kb
Host smart-4383be08-7481-44e8-8fe1-365092841be1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794775097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.794775097
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1323859633
Short name T323
Test name
Test status
Simulation time 35529495 ps
CPU time 1.42 seconds
Started May 14 01:16:22 PM PDT 24
Finished May 14 01:16:25 PM PDT 24
Peak memory 196928 kb
Host smart-35b47b15-fb83-4a1a-8466-0d1cecab7ea5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323859633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1323859633
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1597918904
Short name T566
Test name
Test status
Simulation time 36502207 ps
CPU time 1.15 seconds
Started May 14 01:16:30 PM PDT 24
Finished May 14 01:16:33 PM PDT 24
Peak memory 196552 kb
Host smart-6c19fa0d-a221-44d7-ac99-dee694105dc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597918904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1597918904
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3998280194
Short name T110
Test name
Test status
Simulation time 16691660 ps
CPU time 0.71 seconds
Started May 14 01:16:26 PM PDT 24
Finished May 14 01:16:28 PM PDT 24
Peak memory 196148 kb
Host smart-2f6d051c-b4bb-497b-a35c-f3639b7ce239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998280194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3998280194
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1261681133
Short name T214
Test name
Test status
Simulation time 64238922 ps
CPU time 1.26 seconds
Started May 14 01:16:29 PM PDT 24
Finished May 14 01:16:33 PM PDT 24
Peak memory 198044 kb
Host smart-bb5a6a6e-6c6f-4d1f-9cd7-5b445ef73d9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261681133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1261681133
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3366061747
Short name T541
Test name
Test status
Simulation time 652934120 ps
CPU time 2.67 seconds
Started May 14 01:16:10 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 197984 kb
Host smart-3a1f4d43-bf61-462e-a50d-520f6c37b4ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366061747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3366061747
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3137894382
Short name T602
Test name
Test status
Simulation time 447569550 ps
CPU time 1.36 seconds
Started May 14 01:16:15 PM PDT 24
Finished May 14 01:16:19 PM PDT 24
Peak memory 196876 kb
Host smart-2daa652d-50ff-4e7f-af8a-b1404e8cc183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137894382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3137894382
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1688487813
Short name T609
Test name
Test status
Simulation time 224028747 ps
CPU time 1.28 seconds
Started May 14 01:16:08 PM PDT 24
Finished May 14 01:16:12 PM PDT 24
Peak memory 196288 kb
Host smart-6609b511-c291-41f4-838f-e1f5437595f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688487813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1688487813
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1076697488
Short name T508
Test name
Test status
Simulation time 128221359570 ps
CPU time 164.91 seconds
Started May 14 01:16:10 PM PDT 24
Finished May 14 01:18:58 PM PDT 24
Peak memory 198136 kb
Host smart-21146984-66b8-4930-b8a1-e39a04026a2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076697488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1076697488
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3554278963
Short name T141
Test name
Test status
Simulation time 41989257 ps
CPU time 0.58 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:16:13 PM PDT 24
Peak memory 194596 kb
Host smart-e18543b5-7c23-4e16-883f-753d65de5257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554278963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3554278963
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2001540254
Short name T17
Test name
Test status
Simulation time 19866718 ps
CPU time 0.68 seconds
Started May 14 01:16:13 PM PDT 24
Finished May 14 01:16:17 PM PDT 24
Peak memory 194856 kb
Host smart-ebbf0964-ee8b-45fd-be6c-3d79fbb577c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001540254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2001540254
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3784389366
Short name T355
Test name
Test status
Simulation time 1898725361 ps
CPU time 13.77 seconds
Started May 14 01:16:11 PM PDT 24
Finished May 14 01:16:28 PM PDT 24
Peak memory 196684 kb
Host smart-4b22a5f7-6ab2-4b68-bd39-1f69beb07042
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784389366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3784389366
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.629945206
Short name T526
Test name
Test status
Simulation time 224141100 ps
CPU time 0.91 seconds
Started May 14 01:16:24 PM PDT 24
Finished May 14 01:16:27 PM PDT 24
Peak memory 196956 kb
Host smart-96806e0a-f941-4073-9aad-e63c0962457c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629945206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.629945206
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.773748178
Short name T302
Test name
Test status
Simulation time 42412484 ps
CPU time 0.84 seconds
Started May 14 01:16:25 PM PDT 24
Finished May 14 01:16:28 PM PDT 24
Peak memory 195468 kb
Host smart-ba2c622a-ffd8-401c-adb1-0aa8896b3fbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773748178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.773748178
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.23090274
Short name T423
Test name
Test status
Simulation time 1280400044 ps
CPU time 3.15 seconds
Started May 14 01:16:27 PM PDT 24
Finished May 14 01:16:33 PM PDT 24
Peak memory 198016 kb
Host smart-e7dd19e1-ba77-442f-a84f-c150a3238fb8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23090274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.gpio_intr_with_filter_rand_intr_event.23090274
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.4066500171
Short name T188
Test name
Test status
Simulation time 1406129755 ps
CPU time 3.24 seconds
Started May 14 01:16:15 PM PDT 24
Finished May 14 01:16:21 PM PDT 24
Peak memory 196764 kb
Host smart-b1938732-91bc-4134-ad81-85a579ff5d69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066500171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.4066500171
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3772289339
Short name T590
Test name
Test status
Simulation time 29339363 ps
CPU time 0.78 seconds
Started May 14 01:16:14 PM PDT 24
Finished May 14 01:16:18 PM PDT 24
Peak memory 195540 kb
Host smart-32d61f59-a7cd-49b9-b8ba-42abbdda1a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772289339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3772289339
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.4230133964
Short name T534
Test name
Test status
Simulation time 24167919 ps
CPU time 0.7 seconds
Started May 14 01:16:12 PM PDT 24
Finished May 14 01:16:16 PM PDT 24
Peak memory 194224 kb
Host smart-daccb736-2b7e-4106-bf6f-03a5b1433bd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230133964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.4230133964
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2000496431
Short name T528
Test name
Test status
Simulation time 93733986 ps
CPU time 2.01 seconds
Started May 14 01:16:18 PM PDT 24
Finished May 14 01:16:21 PM PDT 24
Peak memory 197952 kb
Host smart-5576d3a8-030b-477f-b102-cde34de4c63b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000496431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2000496431
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3576163387
Short name T387
Test name
Test status
Simulation time 31885924 ps
CPU time 0.75 seconds
Started May 14 01:16:26 PM PDT 24
Finished May 14 01:16:28 PM PDT 24
Peak memory 195840 kb
Host smart-144b4bd0-c807-42c8-ac4e-66a12e5d4173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576163387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3576163387
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2079847375
Short name T465
Test name
Test status
Simulation time 41721198 ps
CPU time 0.89 seconds
Started May 14 01:16:10 PM PDT 24
Finished May 14 01:16:14 PM PDT 24
Peak memory 196216 kb
Host smart-23dff49c-726c-4d36-ab2e-c71cbe3e1b61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079847375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2079847375
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.284967729
Short name T672
Test name
Test status
Simulation time 5716010778 ps
CPU time 146.7 seconds
Started May 14 01:16:12 PM PDT 24
Finished May 14 01:18:42 PM PDT 24
Peak memory 198196 kb
Host smart-ed031120-4e11-466a-93bd-a7457e0651e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284967729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.284967729
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1874445474
Short name T581
Test name
Test status
Simulation time 23794816 ps
CPU time 0.59 seconds
Started May 14 01:16:28 PM PDT 24
Finished May 14 01:16:31 PM PDT 24
Peak memory 193864 kb
Host smart-3abd1c82-f81a-4339-b2b6-ffaabd0a2d2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874445474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1874445474
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1087834400
Short name T667
Test name
Test status
Simulation time 28919037 ps
CPU time 0.75 seconds
Started May 14 01:16:09 PM PDT 24
Finished May 14 01:16:12 PM PDT 24
Peak memory 195344 kb
Host smart-493d41f8-2a64-4ba9-b1b6-1eb827fb6cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087834400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1087834400
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.4270413886
Short name T651
Test name
Test status
Simulation time 2306747215 ps
CPU time 17.45 seconds
Started May 14 01:16:31 PM PDT 24
Finished May 14 01:16:51 PM PDT 24
Peak memory 196676 kb
Host smart-2bc480ba-8703-4419-b3c0-351f0e4f565f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270413886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.4270413886
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.377353952
Short name T402
Test name
Test status
Simulation time 60186495 ps
CPU time 0.76 seconds
Started May 14 01:16:18 PM PDT 24
Finished May 14 01:16:20 PM PDT 24
Peak memory 194736 kb
Host smart-6ed122b7-14e4-4a9a-8185-066996d11355
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377353952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.377353952
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1946936133
Short name T470
Test name
Test status
Simulation time 155692399 ps
CPU time 1.13 seconds
Started May 14 01:16:22 PM PDT 24
Finished May 14 01:16:25 PM PDT 24
Peak memory 195928 kb
Host smart-06e0fa5b-8ef9-4917-a76c-6b59131c047d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946936133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1946936133
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.124060564
Short name T384
Test name
Test status
Simulation time 38522076 ps
CPU time 0.98 seconds
Started May 14 01:16:27 PM PDT 24
Finished May 14 01:16:29 PM PDT 24
Peak memory 196280 kb
Host smart-7475e89a-acd6-4e5f-8b30-917615dad40d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124060564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.124060564
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3373058644
Short name T410
Test name
Test status
Simulation time 332392455 ps
CPU time 3.49 seconds
Started May 14 01:16:22 PM PDT 24
Finished May 14 01:16:28 PM PDT 24
Peak memory 197940 kb
Host smart-ceed23bc-ddda-4e94-9e4c-7bdbbda612d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373058644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3373058644
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.525108387
Short name T498
Test name
Test status
Simulation time 80866031 ps
CPU time 0.94 seconds
Started May 14 01:16:31 PM PDT 24
Finished May 14 01:16:34 PM PDT 24
Peak memory 195832 kb
Host smart-2cc1a338-1376-4f7f-b6b5-1c5c5e2d26c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525108387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.525108387
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.9586942
Short name T551
Test name
Test status
Simulation time 28302358 ps
CPU time 0.73 seconds
Started May 14 01:16:21 PM PDT 24
Finished May 14 01:16:23 PM PDT 24
Peak memory 194292 kb
Host smart-5d9cdd58-0977-45c7-9a0b-f256293c6d6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9586942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup_p
ulldown.9586942
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3204170431
Short name T683
Test name
Test status
Simulation time 435229814 ps
CPU time 2.74 seconds
Started May 14 01:16:27 PM PDT 24
Finished May 14 01:16:31 PM PDT 24
Peak memory 197980 kb
Host smart-e974db04-162f-4d8c-af82-b6a3cad674b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204170431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3204170431
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2815792005
Short name T678
Test name
Test status
Simulation time 237479060 ps
CPU time 1.16 seconds
Started May 14 01:16:25 PM PDT 24
Finished May 14 01:16:28 PM PDT 24
Peak memory 195504 kb
Host smart-454b3b19-af79-4c46-a06d-bab279e8d483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815792005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2815792005
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.740140352
Short name T315
Test name
Test status
Simulation time 60375875 ps
CPU time 1.19 seconds
Started May 14 01:16:18 PM PDT 24
Finished May 14 01:16:20 PM PDT 24
Peak memory 196380 kb
Host smart-94634bda-d114-49bd-90cf-27208c4b6a60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740140352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.740140352
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1656984053
Short name T144
Test name
Test status
Simulation time 78616774056 ps
CPU time 244.97 seconds
Started May 14 01:16:30 PM PDT 24
Finished May 14 01:20:37 PM PDT 24
Peak memory 198156 kb
Host smart-531fb421-69be-4a6e-a5f7-e44a68483aee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656984053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1656984053
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3691883219
Short name T660
Test name
Test status
Simulation time 36920358 ps
CPU time 0.56 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 194044 kb
Host smart-27ddefa4-497c-4c10-b5fd-df35939a9b29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691883219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3691883219
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2353049658
Short name T515
Test name
Test status
Simulation time 36311924 ps
CPU time 0.66 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:49 PM PDT 24
Peak memory 194804 kb
Host smart-432345e4-ad6c-4e90-922e-1ba2839fcb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353049658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2353049658
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3769920791
Short name T366
Test name
Test status
Simulation time 598716236 ps
CPU time 21.62 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:15:13 PM PDT 24
Peak memory 197980 kb
Host smart-753adda5-ee6f-42cd-a2cc-6122ef924145
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769920791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3769920791
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1866089142
Short name T331
Test name
Test status
Simulation time 141719426 ps
CPU time 0.99 seconds
Started May 14 01:14:44 PM PDT 24
Finished May 14 01:14:47 PM PDT 24
Peak memory 197732 kb
Host smart-5e816eda-230a-4352-bf0e-cc1e6a947071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866089142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1866089142
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3796774476
Short name T685
Test name
Test status
Simulation time 62264201 ps
CPU time 0.88 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 196604 kb
Host smart-069d6f61-b49b-429d-a64b-e1ad26bc2f81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796774476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3796774476
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2695002416
Short name T623
Test name
Test status
Simulation time 284116391 ps
CPU time 1.94 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:54 PM PDT 24
Peak memory 197988 kb
Host smart-37ff6fc0-47aa-4e57-966e-30695a6965c3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695002416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2695002416
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.841867425
Short name T503
Test name
Test status
Simulation time 123821061 ps
CPU time 1.87 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:53 PM PDT 24
Peak memory 195984 kb
Host smart-7cf8d4b8-8389-4cb8-9a50-c2b7b9fc45d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841867425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.841867425
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3910149602
Short name T527
Test name
Test status
Simulation time 91621356 ps
CPU time 0.98 seconds
Started May 14 01:14:53 PM PDT 24
Finished May 14 01:14:58 PM PDT 24
Peak memory 196684 kb
Host smart-a7bce9ea-946f-46a9-884f-b8ba4274ccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910149602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3910149602
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.378990922
Short name T388
Test name
Test status
Simulation time 55021060 ps
CPU time 1 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 196692 kb
Host smart-65e43cb0-6e25-46b9-89cd-4b4dfcd5e54a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378990922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.378990922
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.2125988764
Short name T684
Test name
Test status
Simulation time 729870043 ps
CPU time 4.37 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:56 PM PDT 24
Peak memory 197940 kb
Host smart-acf8071c-0a94-4462-99c4-0f6d4eb62fe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125988764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.2125988764
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2867561251
Short name T99
Test name
Test status
Simulation time 159330518 ps
CPU time 1.06 seconds
Started May 14 01:14:42 PM PDT 24
Finished May 14 01:14:44 PM PDT 24
Peak memory 195712 kb
Host smart-294d10e5-120e-4427-8126-318bc5b13426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867561251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2867561251
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1274138392
Short name T195
Test name
Test status
Simulation time 64483477 ps
CPU time 1.01 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:51 PM PDT 24
Peak memory 196240 kb
Host smart-f91ec0cf-57cd-469f-91fc-687bde2ad30f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274138392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1274138392
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3385621273
Short name T459
Test name
Test status
Simulation time 26726989503 ps
CPU time 166.2 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:17:31 PM PDT 24
Peak memory 198228 kb
Host smart-40ee2f3e-c3ef-423d-8ba0-fe187dc4d3d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385621273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3385621273
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.4142603162
Short name T146
Test name
Test status
Simulation time 93471239 ps
CPU time 0.58 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:51 PM PDT 24
Peak memory 193832 kb
Host smart-2904ac11-7622-4212-b930-4f79fd1fd34f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142603162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.4142603162
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2543838267
Short name T133
Test name
Test status
Simulation time 30066366 ps
CPU time 0.77 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:49 PM PDT 24
Peak memory 195324 kb
Host smart-5044e216-7682-4aad-a5c7-588c0d6ee999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543838267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2543838267
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.50409182
Short name T437
Test name
Test status
Simulation time 1008938695 ps
CPU time 15.32 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:15:06 PM PDT 24
Peak memory 196880 kb
Host smart-36d8a0ea-9ffe-4923-bae3-c2a63ea0a848
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50409182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress.50409182
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3920035061
Short name T681
Test name
Test status
Simulation time 55159848 ps
CPU time 0.84 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 196156 kb
Host smart-70601408-84f3-4c67-8e7a-3a67faeaaf5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920035061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3920035061
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3778639919
Short name T325
Test name
Test status
Simulation time 141266687 ps
CPU time 0.85 seconds
Started May 14 01:14:50 PM PDT 24
Finished May 14 01:14:55 PM PDT 24
Peak memory 196156 kb
Host smart-f79a57e2-c79c-4fa7-94f4-b35abadbcf5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778639919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3778639919
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2803047121
Short name T238
Test name
Test status
Simulation time 188149584 ps
CPU time 1.08 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:50 PM PDT 24
Peak memory 196060 kb
Host smart-9cc9c2cf-459d-4126-a2a5-290406df3996
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803047121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2803047121
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3052560825
Short name T365
Test name
Test status
Simulation time 164047213 ps
CPU time 3.23 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:54 PM PDT 24
Peak memory 197156 kb
Host smart-30040e92-98d5-4735-89fb-25faf9efa0cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052560825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3052560825
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2960645969
Short name T123
Test name
Test status
Simulation time 87226753 ps
CPU time 1.13 seconds
Started May 14 01:14:45 PM PDT 24
Finished May 14 01:14:48 PM PDT 24
Peak memory 196092 kb
Host smart-06a30eb2-2ca3-4d97-a721-ccb891623658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960645969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2960645969
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.254289867
Short name T530
Test name
Test status
Simulation time 44824683 ps
CPU time 1.15 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 195900 kb
Host smart-83e7fa06-e402-454a-b088-52fb90d9981c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254289867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.254289867
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.1655027687
Short name T413
Test name
Test status
Simulation time 425374221 ps
CPU time 5.16 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:56 PM PDT 24
Peak memory 197988 kb
Host smart-e400d5b2-271d-497f-8bdc-8e7315bd1cdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655027687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.1655027687
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2177399969
Short name T564
Test name
Test status
Simulation time 31030402 ps
CPU time 0.94 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:50 PM PDT 24
Peak memory 195860 kb
Host smart-ce3ff9e1-f6d8-4187-a3c3-f3efbe8e5ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177399969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2177399969
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3476483959
Short name T421
Test name
Test status
Simulation time 71779801 ps
CPU time 1.21 seconds
Started May 14 01:14:50 PM PDT 24
Finished May 14 01:14:55 PM PDT 24
Peak memory 195680 kb
Host smart-a8ad630e-baf2-4f53-a500-15a4a4e2ab34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476483959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3476483959
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.314783476
Short name T613
Test name
Test status
Simulation time 15628960296 ps
CPU time 169.57 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:17:38 PM PDT 24
Peak memory 198104 kb
Host smart-4a53d807-a7c1-4b70-8da2-d59a8b708d2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314783476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.314783476
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1521233773
Short name T50
Test name
Test status
Simulation time 21951623 ps
CPU time 0.57 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 193860 kb
Host smart-8cc8afcc-dc5d-4362-84a9-b5fd39981500
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521233773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1521233773
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3477071599
Short name T329
Test name
Test status
Simulation time 407470764 ps
CPU time 0.81 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:51 PM PDT 24
Peak memory 196076 kb
Host smart-adaf0bab-f9af-40fb-83ce-d451b05145a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477071599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3477071599
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.2118912615
Short name T458
Test name
Test status
Simulation time 766392346 ps
CPU time 9.26 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:54 PM PDT 24
Peak memory 195448 kb
Host smart-ab0a4c10-6125-4820-87d0-86a3f5973d56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118912615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.2118912615
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1475125117
Short name T309
Test name
Test status
Simulation time 293457880 ps
CPU time 0.89 seconds
Started May 14 01:14:43 PM PDT 24
Finished May 14 01:14:46 PM PDT 24
Peak memory 195984 kb
Host smart-4e695e00-f9cf-4eec-9c99-9b1bd0702d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475125117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1475125117
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2843575099
Short name T597
Test name
Test status
Simulation time 78373339 ps
CPU time 1.47 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 198020 kb
Host smart-4cd9cb88-d777-4344-8de0-c8ac08994635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843575099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2843575099
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2489359509
Short name T307
Test name
Test status
Simulation time 69840308 ps
CPU time 2.88 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:54 PM PDT 24
Peak memory 198072 kb
Host smart-b3ac36ec-64e9-4b3a-8276-6baeb6d4d6da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489359509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2489359509
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1554475419
Short name T122
Test name
Test status
Simulation time 242454156 ps
CPU time 3.59 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:52 PM PDT 24
Peak memory 198032 kb
Host smart-6b926381-159a-4ce2-8b8c-b3c23173263a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554475419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1554475419
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3687475729
Short name T596
Test name
Test status
Simulation time 165760596 ps
CPU time 1.08 seconds
Started May 14 01:14:50 PM PDT 24
Finished May 14 01:14:56 PM PDT 24
Peak memory 196036 kb
Host smart-12b1eb60-c5ea-4c6c-8970-fa331f331792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687475729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3687475729
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3886655066
Short name T290
Test name
Test status
Simulation time 192734783 ps
CPU time 1.18 seconds
Started May 14 01:14:45 PM PDT 24
Finished May 14 01:14:49 PM PDT 24
Peak memory 198068 kb
Host smart-618fb597-fe50-4693-b808-13bb767b99a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886655066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3886655066
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1880806254
Short name T265
Test name
Test status
Simulation time 427589400 ps
CPU time 2.07 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:14:53 PM PDT 24
Peak memory 197840 kb
Host smart-0a2b6121-ae7b-40cf-a8da-3e057b41ed71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880806254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1880806254
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.4047063613
Short name T630
Test name
Test status
Simulation time 67888802 ps
CPU time 1.06 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:50 PM PDT 24
Peak memory 195712 kb
Host smart-967889bf-bfd4-43ef-898d-f033ad465ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047063613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.4047063613
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1508685749
Short name T705
Test name
Test status
Simulation time 98049714 ps
CPU time 1.06 seconds
Started May 14 01:14:50 PM PDT 24
Finished May 14 01:14:56 PM PDT 24
Peak memory 195704 kb
Host smart-9c5250c9-e479-4fc7-a9af-cd944ddb6efe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508685749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1508685749
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3823005447
Short name T477
Test name
Test status
Simulation time 14952607961 ps
CPU time 108.22 seconds
Started May 14 01:14:47 PM PDT 24
Finished May 14 01:16:38 PM PDT 24
Peak memory 198108 kb
Host smart-17945090-0e80-469d-8b0b-dd496adde01e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823005447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3823005447
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.824496417
Short name T220
Test name
Test status
Simulation time 41105424 ps
CPU time 0.58 seconds
Started May 14 01:14:53 PM PDT 24
Finished May 14 01:14:58 PM PDT 24
Peak memory 194596 kb
Host smart-6ad3dbbf-9b55-403d-adb9-5623d6ca9493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824496417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.824496417
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1682549290
Short name T406
Test name
Test status
Simulation time 76332471 ps
CPU time 0.76 seconds
Started May 14 01:14:49 PM PDT 24
Finished May 14 01:14:53 PM PDT 24
Peak memory 195396 kb
Host smart-b660715f-cef5-49cb-aea0-40bd8126a561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682549290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1682549290
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2891912679
Short name T389
Test name
Test status
Simulation time 725160843 ps
CPU time 9.69 seconds
Started May 14 01:14:57 PM PDT 24
Finished May 14 01:15:09 PM PDT 24
Peak memory 196852 kb
Host smart-4735af7a-be53-461e-8da7-1d648dfc62e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891912679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2891912679
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1374502917
Short name T3
Test name
Test status
Simulation time 313908726 ps
CPU time 0.92 seconds
Started May 14 01:14:56 PM PDT 24
Finished May 14 01:15:00 PM PDT 24
Peak memory 196948 kb
Host smart-a4a6f924-a340-48a7-8b0a-83207784159f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374502917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1374502917
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.518091818
Short name T485
Test name
Test status
Simulation time 86809414 ps
CPU time 0.93 seconds
Started May 14 01:14:51 PM PDT 24
Finished May 14 01:14:56 PM PDT 24
Peak memory 196752 kb
Host smart-bb75b5e4-eae6-4c92-a984-ea41a6c76869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518091818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.518091818
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3321429170
Short name T349
Test name
Test status
Simulation time 35923318 ps
CPU time 1.45 seconds
Started May 14 01:15:09 PM PDT 24
Finished May 14 01:15:18 PM PDT 24
Peak memory 196556 kb
Host smart-2cddb24c-01ef-4b6f-a467-14de59a39528
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321429170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3321429170
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.191404755
Short name T334
Test name
Test status
Simulation time 355141028 ps
CPU time 2.05 seconds
Started May 14 01:14:53 PM PDT 24
Finished May 14 01:14:59 PM PDT 24
Peak memory 196396 kb
Host smart-f877929d-abf7-47d2-ac50-d8f17aeb6ef6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191404755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.191404755
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.538647264
Short name T707
Test name
Test status
Simulation time 120382381 ps
CPU time 1.39 seconds
Started May 14 01:14:50 PM PDT 24
Finished May 14 01:14:56 PM PDT 24
Peak memory 196772 kb
Host smart-8b990dfa-e4f2-443a-8ef5-e637a7f4d617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538647264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.538647264
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2460709902
Short name T449
Test name
Test status
Simulation time 182228111 ps
CPU time 0.96 seconds
Started May 14 01:14:46 PM PDT 24
Finished May 14 01:14:49 PM PDT 24
Peak memory 195852 kb
Host smart-09700538-9306-40f1-a631-a5e8d64f1dc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460709902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2460709902
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2771020661
Short name T548
Test name
Test status
Simulation time 119074162 ps
CPU time 5.53 seconds
Started May 14 01:14:52 PM PDT 24
Finished May 14 01:15:02 PM PDT 24
Peak memory 197948 kb
Host smart-2e984fd9-91c5-47a2-9c41-dd43554e7f10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771020661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2771020661
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.1775157956
Short name T569
Test name
Test status
Simulation time 279816102 ps
CPU time 1.01 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:53 PM PDT 24
Peak memory 195696 kb
Host smart-c79e2590-ab6b-4920-8663-ffd1376e713e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775157956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1775157956
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.4229726511
Short name T207
Test name
Test status
Simulation time 234781787 ps
CPU time 1.3 seconds
Started May 14 01:14:45 PM PDT 24
Finished May 14 01:14:49 PM PDT 24
Peak memory 196664 kb
Host smart-b90684e0-cc79-4e43-a905-26bc73b418cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229726511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.4229726511
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1148614143
Short name T647
Test name
Test status
Simulation time 12449406163 ps
CPU time 41.84 seconds
Started May 14 01:14:50 PM PDT 24
Finished May 14 01:15:36 PM PDT 24
Peak memory 198188 kb
Host smart-25b795da-b313-4351-b61e-7273034aaab8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148614143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1148614143
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2675393260
Short name T520
Test name
Test status
Simulation time 20241891 ps
CPU time 0.56 seconds
Started May 14 01:15:06 PM PDT 24
Finished May 14 01:15:10 PM PDT 24
Peak memory 193860 kb
Host smart-121372ef-59cc-42f6-8512-8e135535ce88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675393260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2675393260
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1696344208
Short name T589
Test name
Test status
Simulation time 51818076 ps
CPU time 0.72 seconds
Started May 14 01:14:56 PM PDT 24
Finished May 14 01:15:00 PM PDT 24
Peak memory 195240 kb
Host smart-6aa53ffd-cc68-4c37-94d4-50205a1f2526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696344208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1696344208
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2376376227
Short name T360
Test name
Test status
Simulation time 202737906 ps
CPU time 3.72 seconds
Started May 14 01:14:58 PM PDT 24
Finished May 14 01:15:04 PM PDT 24
Peak memory 195920 kb
Host smart-6a4d9469-796d-4bfd-8ebd-560a9983590d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376376227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2376376227
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2649126551
Short name T636
Test name
Test status
Simulation time 112438320 ps
CPU time 0.88 seconds
Started May 14 01:14:54 PM PDT 24
Finished May 14 01:14:59 PM PDT 24
Peak memory 196728 kb
Host smart-60f3bcb3-75fa-42a2-bff8-8a64c2ef36ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649126551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2649126551
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.167580576
Short name T322
Test name
Test status
Simulation time 58470648 ps
CPU time 0.75 seconds
Started May 14 01:14:50 PM PDT 24
Finished May 14 01:14:56 PM PDT 24
Peak memory 194424 kb
Host smart-a4be30eb-bbed-49de-8e4d-3b00f04372e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167580576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.167580576
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.299682942
Short name T248
Test name
Test status
Simulation time 327603087 ps
CPU time 3.17 seconds
Started May 14 01:14:54 PM PDT 24
Finished May 14 01:15:01 PM PDT 24
Peak memory 198104 kb
Host smart-2a47d2fa-b9d3-41e9-95d6-24d472d57e2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299682942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.299682942
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1728635113
Short name T271
Test name
Test status
Simulation time 164395574 ps
CPU time 2.57 seconds
Started May 14 01:14:59 PM PDT 24
Finished May 14 01:15:04 PM PDT 24
Peak memory 195160 kb
Host smart-658defcc-543a-49d9-b3c9-15b47b23de08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728635113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1728635113
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3866969769
Short name T404
Test name
Test status
Simulation time 32512755 ps
CPU time 0.9 seconds
Started May 14 01:14:48 PM PDT 24
Finished May 14 01:14:53 PM PDT 24
Peak memory 196624 kb
Host smart-f5aed50a-3de0-4839-a6c4-8e62e65fafcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866969769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3866969769
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2478510792
Short name T19
Test name
Test status
Simulation time 44397126 ps
CPU time 0.74 seconds
Started May 14 01:14:54 PM PDT 24
Finished May 14 01:14:59 PM PDT 24
Peak memory 195328 kb
Host smart-c7b70e77-b05e-402e-b3de-e2643e3dd187
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478510792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2478510792
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.833183738
Short name T233
Test name
Test status
Simulation time 394895533 ps
CPU time 6.5 seconds
Started May 14 01:15:05 PM PDT 24
Finished May 14 01:15:15 PM PDT 24
Peak memory 197992 kb
Host smart-07e7f6b1-e226-49cf-9960-b0757872db86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833183738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.833183738
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2429732938
Short name T299
Test name
Test status
Simulation time 47038290 ps
CPU time 1.33 seconds
Started May 14 01:14:52 PM PDT 24
Finished May 14 01:14:57 PM PDT 24
Peak memory 197952 kb
Host smart-e6d4d735-f1a5-4713-aeaf-2ac59941a8a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429732938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2429732938
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.4209137715
Short name T145
Test name
Test status
Simulation time 53644492 ps
CPU time 1.42 seconds
Started May 14 01:14:58 PM PDT 24
Finished May 14 01:15:02 PM PDT 24
Peak memory 196812 kb
Host smart-e533c246-043e-4fd6-b420-47b95a28d5f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209137715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.4209137715
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.172064736
Short name T10
Test name
Test status
Simulation time 2542180492 ps
CPU time 30.36 seconds
Started May 14 01:14:58 PM PDT 24
Finished May 14 01:15:31 PM PDT 24
Peak memory 198100 kb
Host smart-eaa9c6be-bfe2-43f2-bee7-0b3495f4cdf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172064736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.172064736
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3892082784
Short name T59
Test name
Test status
Simulation time 59777385582 ps
CPU time 1593.79 seconds
Started May 14 01:15:09 PM PDT 24
Finished May 14 01:41:47 PM PDT 24
Peak memory 198228 kb
Host smart-0ecffaa9-1d3d-4593-aebf-cb7c68cd00f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3892082784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3892082784
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3713609658
Short name T924
Test name
Test status
Simulation time 257208619 ps
CPU time 1.14 seconds
Started May 14 01:14:21 PM PDT 24
Finished May 14 01:14:24 PM PDT 24
Peak memory 198656 kb
Host smart-35a4b0ff-2713-4225-bf0c-3c6b465a3160
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3713609658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3713609658
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1405914420
Short name T852
Test name
Test status
Simulation time 148276254 ps
CPU time 1.33 seconds
Started May 14 01:14:20 PM PDT 24
Finished May 14 01:14:24 PM PDT 24
Peak memory 192292 kb
Host smart-0b5d223d-aa1d-436c-a439-0a8327ed7e74
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405914420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1405914420
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.492857958
Short name T917
Test name
Test status
Simulation time 99808755 ps
CPU time 1.58 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 198608 kb
Host smart-538f050d-d8fa-4aba-8dab-e53dfa8d7d3e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=492857958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.492857958
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1446251532
Short name T870
Test name
Test status
Simulation time 207725311 ps
CPU time 1.04 seconds
Started May 14 01:14:19 PM PDT 24
Finished May 14 01:14:23 PM PDT 24
Peak memory 196984 kb
Host smart-3e4e5bb0-48e6-4d22-a712-854411687578
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446251532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1446251532
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3197921430
Short name T862
Test name
Test status
Simulation time 210843083 ps
CPU time 1.11 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:20 PM PDT 24
Peak memory 192248 kb
Host smart-96612a89-52a1-42d6-b794-4c57040026f6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3197921430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3197921430
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1258822221
Short name T874
Test name
Test status
Simulation time 48064718 ps
CPU time 0.94 seconds
Started May 14 01:14:21 PM PDT 24
Finished May 14 01:14:24 PM PDT 24
Peak memory 192264 kb
Host smart-5e103d6c-3f93-427f-acc9-4b852127534c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258822221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1258822221
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3212912452
Short name T923
Test name
Test status
Simulation time 72930594 ps
CPU time 1.35 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 192260 kb
Host smart-1a073eca-3fd7-476b-bba7-86d0b8d747be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3212912452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3212912452
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2337683570
Short name T931
Test name
Test status
Simulation time 33508919 ps
CPU time 1 seconds
Started May 14 01:14:19 PM PDT 24
Finished May 14 01:14:23 PM PDT 24
Peak memory 192304 kb
Host smart-a714d7cc-113a-4f8d-8d8d-478354580a31
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337683570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2337683570
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.58829755
Short name T843
Test name
Test status
Simulation time 184043318 ps
CPU time 1.04 seconds
Started May 14 01:14:20 PM PDT 24
Finished May 14 01:14:24 PM PDT 24
Peak memory 192268 kb
Host smart-f9f98d8c-67f5-405d-8363-1433217b26e5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=58829755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.58829755
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2179041093
Short name T934
Test name
Test status
Simulation time 63158282 ps
CPU time 1.28 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 197252 kb
Host smart-9b16859c-d33e-49e9-9522-7120292dfd73
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179041093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2179041093
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2286182708
Short name T835
Test name
Test status
Simulation time 193189231 ps
CPU time 1.3 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:23 PM PDT 24
Peak memory 192232 kb
Host smart-f3860206-0b19-4df4-a8f4-e3d33b28f912
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2286182708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2286182708
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.439218465
Short name T869
Test name
Test status
Simulation time 93229480 ps
CPU time 1.15 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:20 PM PDT 24
Peak memory 198584 kb
Host smart-69395cbf-6961-48bf-90da-26d72d3ad410
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439218465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.439218465
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.66030387
Short name T888
Test name
Test status
Simulation time 75816823 ps
CPU time 1.11 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:20 PM PDT 24
Peak memory 192252 kb
Host smart-d7277451-16cd-481c-8993-7503a2ce1af4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=66030387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.66030387
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3025037183
Short name T915
Test name
Test status
Simulation time 54245559 ps
CPU time 1.42 seconds
Started May 14 01:14:19 PM PDT 24
Finished May 14 01:14:23 PM PDT 24
Peak memory 192292 kb
Host smart-2c4c5058-b9d7-4ab4-9995-372fa931d1b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025037183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3025037183
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2835147142
Short name T889
Test name
Test status
Simulation time 70190657 ps
CPU time 1.19 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:20 PM PDT 24
Peak memory 192140 kb
Host smart-58453acf-40e5-4612-8215-26ecb058c9c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2835147142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2835147142
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.639185275
Short name T881
Test name
Test status
Simulation time 122170226 ps
CPU time 1 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 198580 kb
Host smart-0b840713-95e3-4f76-bfcb-c05fad3626b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639185275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.639185275
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3286426870
Short name T891
Test name
Test status
Simulation time 123044246 ps
CPU time 1.3 seconds
Started May 14 01:14:22 PM PDT 24
Finished May 14 01:14:25 PM PDT 24
Peak memory 192256 kb
Host smart-235a5fe1-f3cf-4299-9b09-ed5f11c56b28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3286426870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3286426870
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3331617806
Short name T842
Test name
Test status
Simulation time 369483849 ps
CPU time 0.79 seconds
Started May 14 01:14:20 PM PDT 24
Finished May 14 01:14:24 PM PDT 24
Peak memory 192112 kb
Host smart-0216fbd8-627b-4f44-9d1d-0466aa2357d7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331617806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3331617806
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4048352708
Short name T925
Test name
Test status
Simulation time 73314899 ps
CPU time 1.14 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 198556 kb
Host smart-d31759f1-4c74-4a46-83aa-d4e19148abb9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4048352708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.4048352708
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1566350451
Short name T847
Test name
Test status
Simulation time 57454971 ps
CPU time 1.05 seconds
Started May 14 01:14:19 PM PDT 24
Finished May 14 01:14:23 PM PDT 24
Peak memory 198628 kb
Host smart-a7cb8872-0dfe-42b1-b4ea-29a796db34b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566350451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1566350451
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1795917708
Short name T894
Test name
Test status
Simulation time 380706480 ps
CPU time 0.91 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 196644 kb
Host smart-04deb94a-59a1-4d3f-9d67-782ceaacd9cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1795917708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1795917708
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2184216584
Short name T930
Test name
Test status
Simulation time 199801601 ps
CPU time 0.99 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 192124 kb
Host smart-ad1c6bfe-b9c8-4f40-8cb4-06b17ea3a5bf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184216584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2184216584
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.507251152
Short name T853
Test name
Test status
Simulation time 108980524 ps
CPU time 0.95 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 197604 kb
Host smart-a2910cd7-2b75-4302-8e61-1dac5ed25e43
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=507251152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.507251152
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1908412166
Short name T878
Test name
Test status
Simulation time 383368478 ps
CPU time 1.38 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 198604 kb
Host smart-de66d4bb-eab6-44c2-ad91-5b868f1f268d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908412166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1908412166
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3896945110
Short name T850
Test name
Test status
Simulation time 184583505 ps
CPU time 1.31 seconds
Started May 14 01:14:21 PM PDT 24
Finished May 14 01:14:25 PM PDT 24
Peak memory 192220 kb
Host smart-85e4571c-d285-49f9-8ab2-85e88b7f99b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3896945110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3896945110
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2113137321
Short name T887
Test name
Test status
Simulation time 234752138 ps
CPU time 1.16 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 196988 kb
Host smart-8ef0b373-9ec4-47fd-98e8-4d0b188d261d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113137321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2113137321
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2640462697
Short name T868
Test name
Test status
Simulation time 35886196 ps
CPU time 1.15 seconds
Started May 14 01:14:28 PM PDT 24
Finished May 14 01:14:32 PM PDT 24
Peak memory 192272 kb
Host smart-1508476e-ffb1-436a-a50a-0bd1aff9cba7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2640462697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2640462697
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3415342121
Short name T912
Test name
Test status
Simulation time 149825283 ps
CPU time 0.84 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:29 PM PDT 24
Peak memory 192136 kb
Host smart-ac5a8fac-47b8-4629-a02f-d080c78d4403
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415342121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3415342121
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.541619258
Short name T840
Test name
Test status
Simulation time 698203207 ps
CPU time 0.84 seconds
Started May 14 01:14:29 PM PDT 24
Finished May 14 01:14:32 PM PDT 24
Peak memory 192092 kb
Host smart-0715a48f-370f-4376-af24-43bbf8fdd84b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=541619258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.541619258
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2490343095
Short name T922
Test name
Test status
Simulation time 65729093 ps
CPU time 1.05 seconds
Started May 14 01:14:25 PM PDT 24
Finished May 14 01:14:27 PM PDT 24
Peak memory 192304 kb
Host smart-ab3c512b-79d3-4194-a156-f2a03b01d906
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490343095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2490343095
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3349163598
Short name T877
Test name
Test status
Simulation time 36043907 ps
CPU time 1.15 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:29 PM PDT 24
Peak memory 192288 kb
Host smart-5c71682e-43e4-40be-895a-8af7e7a44da2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3349163598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3349163598
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1020526511
Short name T921
Test name
Test status
Simulation time 154320538 ps
CPU time 0.86 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 192108 kb
Host smart-38027580-810e-4171-9703-90e5a3c3e490
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020526511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1020526511
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2252910209
Short name T927
Test name
Test status
Simulation time 235425995 ps
CPU time 0.97 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:30 PM PDT 24
Peak memory 192072 kb
Host smart-df45223e-eb85-4e9e-8d86-76c417226a38
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2252910209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2252910209
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3053166677
Short name T863
Test name
Test status
Simulation time 33459830 ps
CPU time 0.99 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:28 PM PDT 24
Peak memory 192532 kb
Host smart-117fda0f-1d04-4998-b083-3333cea96d0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053166677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3053166677
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1932289505
Short name T882
Test name
Test status
Simulation time 112258566 ps
CPU time 0.9 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:33 PM PDT 24
Peak memory 192076 kb
Host smart-a9c2a4ad-dabe-42fb-8163-0e1c4f4d1172
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1932289505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1932289505
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2691537087
Short name T909
Test name
Test status
Simulation time 67942291 ps
CPU time 0.88 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:29 PM PDT 24
Peak memory 197912 kb
Host smart-b88189c9-b42a-43c7-819d-b2bf166f52b5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691537087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2691537087
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.451782852
Short name T883
Test name
Test status
Simulation time 71993238 ps
CPU time 1.35 seconds
Started May 14 01:14:25 PM PDT 24
Finished May 14 01:14:28 PM PDT 24
Peak memory 198568 kb
Host smart-3cc00f60-8c85-4272-a0a7-6a79523d1666
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=451782852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.451782852
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.247210055
Short name T885
Test name
Test status
Simulation time 442651318 ps
CPU time 0.98 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 192064 kb
Host smart-d27259fa-f1c8-47c9-8173-122cbc06a6cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247210055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.247210055
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1904358614
Short name T839
Test name
Test status
Simulation time 141149787 ps
CPU time 1.11 seconds
Started May 14 01:14:25 PM PDT 24
Finished May 14 01:14:28 PM PDT 24
Peak memory 198540 kb
Host smart-370ab9c0-043f-42d6-ada8-7ac9505bb1a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1904358614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1904358614
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3913320313
Short name T837
Test name
Test status
Simulation time 312725650 ps
CPU time 1.34 seconds
Started May 14 01:14:25 PM PDT 24
Finished May 14 01:14:28 PM PDT 24
Peak memory 197096 kb
Host smart-313c6413-0434-40da-8bca-2a132eeac8b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913320313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3913320313
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3739677409
Short name T897
Test name
Test status
Simulation time 167840104 ps
CPU time 1.25 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 192216 kb
Host smart-39b1b693-1947-44fe-9a95-f815a8c803e0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3739677409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3739677409
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2346236661
Short name T916
Test name
Test status
Simulation time 213448629 ps
CPU time 1.05 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:29 PM PDT 24
Peak memory 192152 kb
Host smart-c0813b18-6684-49c5-9c3a-319817bdf474
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346236661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2346236661
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.683450472
Short name T920
Test name
Test status
Simulation time 52760219 ps
CPU time 1.15 seconds
Started May 14 01:14:30 PM PDT 24
Finished May 14 01:14:33 PM PDT 24
Peak memory 192252 kb
Host smart-e80de77d-d810-4497-a069-efcbc05c023d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=683450472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.683450472
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.925619960
Short name T841
Test name
Test status
Simulation time 75904515 ps
CPU time 1.44 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 192276 kb
Host smart-c563babf-9106-4139-983d-b25d88e38528
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925619960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.925619960
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3447388860
Short name T849
Test name
Test status
Simulation time 92330243 ps
CPU time 1.34 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:32 PM PDT 24
Peak memory 198612 kb
Host smart-42a686be-9a07-497b-a3ad-92368d5cbbac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3447388860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3447388860
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2870421896
Short name T846
Test name
Test status
Simulation time 66334330 ps
CPU time 1.27 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:30 PM PDT 24
Peak memory 192284 kb
Host smart-23e1e1e1-d099-4b49-9a7b-994f130bbf70
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870421896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2870421896
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3185830708
Short name T845
Test name
Test status
Simulation time 70239872 ps
CPU time 1.4 seconds
Started May 14 01:14:19 PM PDT 24
Finished May 14 01:14:24 PM PDT 24
Peak memory 192280 kb
Host smart-076923bb-07f2-4832-90c1-4a4b4661de6b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3185830708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3185830708
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1279783862
Short name T873
Test name
Test status
Simulation time 60437419 ps
CPU time 1.19 seconds
Started May 14 01:14:23 PM PDT 24
Finished May 14 01:14:26 PM PDT 24
Peak memory 192308 kb
Host smart-54594f6b-09cd-4e2b-8777-b162d4509b6f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279783862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1279783862
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2334122852
Short name T896
Test name
Test status
Simulation time 28100344 ps
CPU time 0.98 seconds
Started May 14 01:14:29 PM PDT 24
Finished May 14 01:14:32 PM PDT 24
Peak memory 192244 kb
Host smart-29aae872-1a50-462a-8bc7-40d9ee1ee37e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2334122852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2334122852
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4161279507
Short name T838
Test name
Test status
Simulation time 254111001 ps
CPU time 1.33 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 198624 kb
Host smart-21b79a42-9501-4d0c-b0a6-edd0314278d5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161279507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4161279507
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2551929623
Short name T848
Test name
Test status
Simulation time 49657192 ps
CPU time 0.92 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 192064 kb
Host smart-922dd771-f113-4f86-9971-a5cf88c63cfb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2551929623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2551929623
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.713890989
Short name T892
Test name
Test status
Simulation time 191697720 ps
CPU time 0.9 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:29 PM PDT 24
Peak memory 192264 kb
Host smart-d5b5ca52-87b8-40a7-ab68-1a8f8129dee0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713890989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.713890989
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3934549887
Short name T856
Test name
Test status
Simulation time 1238277398 ps
CPU time 1.19 seconds
Started May 14 01:14:24 PM PDT 24
Finished May 14 01:14:26 PM PDT 24
Peak memory 198604 kb
Host smart-d7469293-1b2f-4be1-8cd5-2d495b88a07e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3934549887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3934549887
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2470081306
Short name T865
Test name
Test status
Simulation time 279034609 ps
CPU time 1.41 seconds
Started May 14 01:14:29 PM PDT 24
Finished May 14 01:14:33 PM PDT 24
Peak memory 192264 kb
Host smart-406b6d1e-3f7e-4e7d-be41-1366a9c767a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470081306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2470081306
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.686734624
Short name T929
Test name
Test status
Simulation time 61318987 ps
CPU time 1.37 seconds
Started May 14 01:14:25 PM PDT 24
Finished May 14 01:14:28 PM PDT 24
Peak memory 192220 kb
Host smart-6727c5b4-fbec-4e90-8b20-7b8280753b11
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=686734624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.686734624
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.885560035
Short name T903
Test name
Test status
Simulation time 146166487 ps
CPU time 1.35 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 192244 kb
Host smart-0dd510e2-737f-47a2-b12e-136a7a046c58
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885560035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.885560035
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1515243626
Short name T901
Test name
Test status
Simulation time 317295649 ps
CPU time 1.31 seconds
Started May 14 01:14:24 PM PDT 24
Finished May 14 01:14:27 PM PDT 24
Peak memory 192264 kb
Host smart-7fa4c84b-0780-4f19-91e2-8281de23e0a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1515243626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1515243626
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3718676661
Short name T893
Test name
Test status
Simulation time 38700288 ps
CPU time 0.69 seconds
Started May 14 01:14:30 PM PDT 24
Finished May 14 01:14:33 PM PDT 24
Peak memory 192092 kb
Host smart-e6ec86c1-1107-4b07-bd0b-7c0ffe7de419
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718676661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3718676661
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1726692873
Short name T872
Test name
Test status
Simulation time 424438413 ps
CPU time 1.3 seconds
Started May 14 01:14:28 PM PDT 24
Finished May 14 01:14:32 PM PDT 24
Peak memory 192264 kb
Host smart-2dceb127-ae0b-41da-a12e-6dd15edb4a39
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1726692873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1726692873
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4182400874
Short name T844
Test name
Test status
Simulation time 116416155 ps
CPU time 1.27 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 198592 kb
Host smart-36679b8e-2f06-4136-bc93-0625d75cc642
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182400874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4182400874
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.907194801
Short name T908
Test name
Test status
Simulation time 51422898 ps
CPU time 0.92 seconds
Started May 14 01:14:33 PM PDT 24
Finished May 14 01:14:36 PM PDT 24
Peak memory 192040 kb
Host smart-1ab6c217-c9a9-4252-8dbc-65c0b5f74183
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=907194801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.907194801
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2724322184
Short name T864
Test name
Test status
Simulation time 101630393 ps
CPU time 1.1 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:30 PM PDT 24
Peak memory 192264 kb
Host smart-da1be33c-ae62-4474-b51f-729ab1ef7a72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724322184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2724322184
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2263621198
Short name T919
Test name
Test status
Simulation time 64451778 ps
CPU time 1.27 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:30 PM PDT 24
Peak memory 192244 kb
Host smart-4e190c18-24e3-4765-9d8e-04c16a81cac6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2263621198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2263621198
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1029672839
Short name T933
Test name
Test status
Simulation time 93509407 ps
CPU time 1.19 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:30 PM PDT 24
Peak memory 192188 kb
Host smart-a7aacb03-1810-470c-8fc0-969a6b5809cf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029672839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1029672839
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2319570639
Short name T886
Test name
Test status
Simulation time 135897664 ps
CPU time 1.15 seconds
Started May 14 01:14:25 PM PDT 24
Finished May 14 01:14:28 PM PDT 24
Peak memory 198580 kb
Host smart-235f3686-e6f0-4247-8bb1-71c8b6131b16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2319570639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2319570639
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.906015658
Short name T866
Test name
Test status
Simulation time 75927958 ps
CPU time 1.32 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 192240 kb
Host smart-9017a2b4-a35f-46ed-93b7-cba42176afc7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906015658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.906015658
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2704437396
Short name T905
Test name
Test status
Simulation time 215474149 ps
CPU time 1.15 seconds
Started May 14 01:14:28 PM PDT 24
Finished May 14 01:14:32 PM PDT 24
Peak memory 192160 kb
Host smart-e950f7a5-250f-429a-8eb7-df93009348f1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2704437396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2704437396
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1346452524
Short name T880
Test name
Test status
Simulation time 1154548718 ps
CPU time 1.46 seconds
Started May 14 01:14:29 PM PDT 24
Finished May 14 01:14:33 PM PDT 24
Peak memory 192304 kb
Host smart-c6d2d0bf-e480-4bcc-8a81-93d54a1cc032
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346452524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1346452524
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3347594667
Short name T911
Test name
Test status
Simulation time 40824535 ps
CPU time 0.87 seconds
Started May 14 01:14:23 PM PDT 24
Finished May 14 01:14:26 PM PDT 24
Peak memory 192112 kb
Host smart-155bb096-c3e1-4b12-b79a-059d1f0c7bb8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3347594667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3347594667
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2296076694
Short name T906
Test name
Test status
Simulation time 93205204 ps
CPU time 1.43 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 192308 kb
Host smart-3ee73e44-40e1-4e14-94c1-3bcd3d519061
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296076694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2296076694
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.221466238
Short name T858
Test name
Test status
Simulation time 31238500 ps
CPU time 1.03 seconds
Started May 14 01:14:28 PM PDT 24
Finished May 14 01:14:32 PM PDT 24
Peak memory 198004 kb
Host smart-ab3e6d30-b5ed-413b-836c-25d45785fa36
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=221466238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.221466238
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2799485057
Short name T854
Test name
Test status
Simulation time 46741583 ps
CPU time 1 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:29 PM PDT 24
Peak memory 192308 kb
Host smart-8c438224-f97b-4c5a-95fe-06c76d96c77f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799485057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2799485057
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1081590776
Short name T884
Test name
Test status
Simulation time 765741452 ps
CPU time 1.09 seconds
Started May 14 01:14:25 PM PDT 24
Finished May 14 01:14:28 PM PDT 24
Peak memory 192280 kb
Host smart-184549a9-2940-4a72-a0a3-307b529c8e90
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1081590776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1081590776
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3951789091
Short name T860
Test name
Test status
Simulation time 682749974 ps
CPU time 1.05 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:30 PM PDT 24
Peak memory 198556 kb
Host smart-c8c8635e-566d-455a-828e-2469cf53ed66
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951789091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3951789091
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3023268948
Short name T836
Test name
Test status
Simulation time 35569349 ps
CPU time 0.88 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:29 PM PDT 24
Peak memory 191992 kb
Host smart-eafcbd67-68ab-41a3-bd7d-68ac7a9fbe29
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3023268948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3023268948
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2250319082
Short name T910
Test name
Test status
Simulation time 163498606 ps
CPU time 1.55 seconds
Started May 14 01:14:30 PM PDT 24
Finished May 14 01:14:33 PM PDT 24
Peak memory 192296 kb
Host smart-3439415b-7149-4ea1-8349-1dab70d0bbbf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250319082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2250319082
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.446954888
Short name T898
Test name
Test status
Simulation time 65373777 ps
CPU time 0.72 seconds
Started May 14 01:14:28 PM PDT 24
Finished May 14 01:14:32 PM PDT 24
Peak memory 192060 kb
Host smart-395a2f12-bf0a-43c4-b27f-36ba8ed4d42b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=446954888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.446954888
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2062606825
Short name T902
Test name
Test status
Simulation time 38350949 ps
CPU time 1 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:30 PM PDT 24
Peak memory 198544 kb
Host smart-c4beaccd-1e6b-4151-ae58-f74f38e92f48
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062606825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2062606825
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.2387696723
Short name T876
Test name
Test status
Simulation time 153152108 ps
CPU time 1.22 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 197664 kb
Host smart-46bf4fe1-41f7-4ea6-9a76-b15aacd1d9b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2387696723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.2387696723
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.379169919
Short name T932
Test name
Test status
Simulation time 32284119 ps
CPU time 0.81 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 192008 kb
Host smart-43220a01-5c8b-47b3-86f2-c4de58e203bb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379169919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.379169919
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4139443616
Short name T890
Test name
Test status
Simulation time 247925627 ps
CPU time 1.23 seconds
Started May 14 01:14:27 PM PDT 24
Finished May 14 01:14:31 PM PDT 24
Peak memory 192276 kb
Host smart-6b7f53c3-3442-414f-917f-2d331018cd5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4139443616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4139443616
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.982345413
Short name T900
Test name
Test status
Simulation time 197187303 ps
CPU time 1.25 seconds
Started May 14 01:14:29 PM PDT 24
Finished May 14 01:14:33 PM PDT 24
Peak memory 192284 kb
Host smart-fe70b301-cde5-4a02-952d-6accbbcb5e8f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982345413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.982345413
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1432618058
Short name T875
Test name
Test status
Simulation time 245349562 ps
CPU time 1.04 seconds
Started May 14 01:14:29 PM PDT 24
Finished May 14 01:14:32 PM PDT 24
Peak memory 192256 kb
Host smart-a99b48b1-0699-4704-836f-2108101c208a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1432618058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1432618058
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1622744786
Short name T928
Test name
Test status
Simulation time 62189072 ps
CPU time 0.96 seconds
Started May 14 01:14:25 PM PDT 24
Finished May 14 01:14:27 PM PDT 24
Peak memory 192068 kb
Host smart-4c91e775-9c1a-455b-8f36-7f2ea8724f52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622744786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1622744786
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2909174748
Short name T867
Test name
Test status
Simulation time 85723673 ps
CPU time 1.41 seconds
Started May 14 01:14:26 PM PDT 24
Finished May 14 01:14:29 PM PDT 24
Peak memory 198572 kb
Host smart-5ac8c867-2424-42ee-afac-c06ecc8838ca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2909174748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2909174748
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1886705850
Short name T855
Test name
Test status
Simulation time 322734745 ps
CPU time 1.27 seconds
Started May 14 01:14:34 PM PDT 24
Finished May 14 01:14:37 PM PDT 24
Peak memory 192264 kb
Host smart-a03f3ddc-6792-4d8b-80b5-ed6366166787
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886705850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1886705850
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3611798906
Short name T857
Test name
Test status
Simulation time 52096049 ps
CPU time 1.09 seconds
Started May 14 01:14:33 PM PDT 24
Finished May 14 01:14:36 PM PDT 24
Peak memory 192264 kb
Host smart-72de0524-2cb2-49d2-ad2d-c3eb0261e222
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3611798906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3611798906
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1041388582
Short name T895
Test name
Test status
Simulation time 80415511 ps
CPU time 1.37 seconds
Started May 14 01:14:35 PM PDT 24
Finished May 14 01:14:38 PM PDT 24
Peak memory 192268 kb
Host smart-0034b3b6-1ec4-46a2-a3fa-2719ddee147a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041388582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1041388582
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3586246318
Short name T918
Test name
Test status
Simulation time 363015254 ps
CPU time 1.51 seconds
Started May 14 01:14:34 PM PDT 24
Finished May 14 01:14:37 PM PDT 24
Peak memory 198584 kb
Host smart-e2627dd0-6856-4331-86a2-080a174d38e8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3586246318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3586246318
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2503014901
Short name T904
Test name
Test status
Simulation time 32517826 ps
CPU time 1.14 seconds
Started May 14 01:14:32 PM PDT 24
Finished May 14 01:14:34 PM PDT 24
Peak memory 192232 kb
Host smart-3e581032-48f6-4f75-92ee-77bee0c7ee1c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503014901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2503014901
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2389387981
Short name T851
Test name
Test status
Simulation time 318123491 ps
CPU time 1.29 seconds
Started May 14 01:14:16 PM PDT 24
Finished May 14 01:14:20 PM PDT 24
Peak memory 192272 kb
Host smart-7e5ddd2f-1686-4a0d-89c7-b139e8614d1b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2389387981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2389387981
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3126337890
Short name T859
Test name
Test status
Simulation time 188944393 ps
CPU time 1.42 seconds
Started May 14 01:14:22 PM PDT 24
Finished May 14 01:14:25 PM PDT 24
Peak memory 192240 kb
Host smart-f96e7a49-d0f6-4528-ba26-a82c673140de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126337890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3126337890
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2880855353
Short name T861
Test name
Test status
Simulation time 77465185 ps
CPU time 1.47 seconds
Started May 14 01:14:16 PM PDT 24
Finished May 14 01:14:20 PM PDT 24
Peak memory 192308 kb
Host smart-22e90a99-79fd-41fe-be41-07e031d07ca0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2880855353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2880855353
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1668615648
Short name T907
Test name
Test status
Simulation time 77338067 ps
CPU time 0.96 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 192080 kb
Host smart-d96c0a63-6bd0-4877-9820-1c791ffedf2d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668615648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1668615648
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.460561179
Short name T913
Test name
Test status
Simulation time 46024156 ps
CPU time 1.06 seconds
Started May 14 01:14:24 PM PDT 24
Finished May 14 01:14:26 PM PDT 24
Peak memory 192268 kb
Host smart-7aa576bd-6db5-44f1-a2a5-18bae7ee47f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=460561179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.460561179
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.749151698
Short name T899
Test name
Test status
Simulation time 26247269 ps
CPU time 0.84 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 192052 kb
Host smart-5ca29331-1b65-4b97-983f-953862a76751
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749151698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.749151698
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.911747028
Short name T871
Test name
Test status
Simulation time 59576589 ps
CPU time 1.25 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:23 PM PDT 24
Peak memory 192296 kb
Host smart-6aeafa20-adb4-4921-9cf2-7f692b2687cf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=911747028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.911747028
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1806764108
Short name T879
Test name
Test status
Simulation time 69846735 ps
CPU time 0.87 seconds
Started May 14 01:14:17 PM PDT 24
Finished May 14 01:14:21 PM PDT 24
Peak memory 192012 kb
Host smart-3004034a-a313-4e0c-a62d-03d0d49cee33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806764108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1806764108
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4235957247
Short name T914
Test name
Test status
Simulation time 124201468 ps
CPU time 1.35 seconds
Started May 14 01:14:18 PM PDT 24
Finished May 14 01:14:22 PM PDT 24
Peak memory 192220 kb
Host smart-b6100502-820b-4b5c-a5d0-5944f13e343d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4235957247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.4235957247
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.284026194
Short name T926
Test name
Test status
Simulation time 305465624 ps
CPU time 1.24 seconds
Started May 14 01:14:19 PM PDT 24
Finished May 14 01:14:23 PM PDT 24
Peak memory 192252 kb
Host smart-435455d1-f384-405a-b795-a087fe2639ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284026194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.284026194
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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