Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3399931	1			T20	110		T21	1		T22	1
all_pins[1]	3399931	1			T20	110		T21	1		T22	1
all_pins[2]	3399931	1			T20	110		T21	1		T22	1
all_pins[3]	3399931	1			T20	110		T21	1		T22	1
all_pins[4]	3399931	1			T20	110		T21	1		T22	1
all_pins[5]	3399931	1			T20	110		T21	1		T22	1
all_pins[6]	3399931	1			T20	110		T21	1		T22	1
all_pins[7]	3399931	1			T20	110		T21	1		T22	1
all_pins[8]	3399931	1			T20	110		T21	1		T22	1
all_pins[9]	3399931	1			T20	110		T21	1		T22	1
all_pins[10]	3399931	1			T20	110		T21	1		T22	1
all_pins[11]	3399931	1			T20	110		T21	1		T22	1
all_pins[12]	3399931	1			T20	110		T21	1		T22	1
all_pins[13]	3399931	1			T20	110		T21	1		T22	1
all_pins[14]	3399931	1			T20	110		T21	1		T22	1
all_pins[15]	3399931	1			T20	110		T21	1		T22	1
all_pins[16]	3399931	1			T20	110		T21	1		T22	1
all_pins[17]	3399931	1			T20	110		T21	1		T22	1
all_pins[18]	3399931	1			T20	110		T21	1		T22	1
all_pins[19]	3399931	1			T20	110		T21	1		T22	1
all_pins[20]	3399931	1			T20	110		T21	1		T22	1
all_pins[21]	3399931	1			T20	110		T21	1		T22	1
all_pins[22]	3399931	1			T20	110		T21	1		T22	1
all_pins[23]	3399931	1			T20	110		T21	1		T22	1
all_pins[24]	3399931	1			T20	110		T21	1		T22	1
all_pins[25]	3399931	1			T20	110		T21	1		T22	1
all_pins[26]	3399931	1			T20	110		T21	1		T22	1
all_pins[27]	3399931	1			T20	110		T21	1		T22	1
all_pins[28]	3399931	1			T20	110		T21	1		T22	1
all_pins[29]	3399931	1			T20	110		T21	1		T22	1
all_pins[30]	3399931	1			T20	110		T21	1		T22	1
all_pins[31]	3399931	1			T20	110		T21	1		T22	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	67583339	1			T20	1725		T21	32		T22	32
values[0x1]	41214453	1			T20	1795		T23	385		T25	830
transitions[0x0=>0x1]	24694656	1			T20	850		T23	277		T25	532
transitions[0x1=>0x0]	24694499	1			T20	849		T23	277		T25	532

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2110731	1			T20	41		T21	1		T22	1
all_pins[0]	values[0x1]	1289200	1			T20	69		T23	23		T25	24
all_pins[0]	transitions[0x0=>0x1]	798160	1			T20	31		T23	17		T25	20
all_pins[0]	transitions[0x1=>0x0]	794387	1			T20	22		T23	2		T25	23
all_pins[1]	values[0x0]	2110885	1			T20	39		T21	1		T22	1
all_pins[1]	values[0x1]	1289046	1			T20	71		T23	15		T25	27
all_pins[1]	transitions[0x0=>0x1]	769426	1			T20	26		T23	5		T25	17
all_pins[1]	transitions[0x1=>0x0]	769580	1			T20	24		T23	13		T25	14
all_pins[2]	values[0x0]	2110867	1			T20	48		T21	1		T22	1
all_pins[2]	values[0x1]	1289064	1			T20	62		T23	8		T25	10
all_pins[2]	transitions[0x0=>0x1]	771078	1			T20	23		T23	3		T25	7
all_pins[2]	transitions[0x1=>0x0]	771060	1			T20	32		T23	10		T25	24
all_pins[3]	values[0x0]	2114128	1			T20	55		T21	1		T22	1
all_pins[3]	values[0x1]	1285803	1			T20	55		T23	18		T25	38
all_pins[3]	transitions[0x0=>0x1]	768613	1			T20	20		T23	15		T25	35
all_pins[3]	transitions[0x1=>0x0]	771874	1			T20	27		T23	5		T25	7
all_pins[4]	values[0x0]	2109948	1			T20	61		T21	1		T22	1
all_pins[4]	values[0x1]	1289983	1			T20	49		T23	14		T25	31
all_pins[4]	transitions[0x0=>0x1]	773606	1			T20	25		T23	9		T25	23
all_pins[4]	transitions[0x1=>0x0]	769426	1			T20	31		T23	13		T25	30
all_pins[5]	values[0x0]	2110963	1			T20	53		T21	1		T22	1
all_pins[5]	values[0x1]	1288968	1			T20	57		T23	6		T25	26
all_pins[5]	transitions[0x0=>0x1]	772581	1			T20	36		T23	3		T25	16
all_pins[5]	transitions[0x1=>0x0]	773596	1			T20	28		T23	11		T25	21
all_pins[6]	values[0x0]	2111270	1			T20	61		T21	1		T22	1
all_pins[6]	values[0x1]	1288661	1			T20	49		T23	17		T25	31
all_pins[6]	transitions[0x0=>0x1]	770125	1			T20	21		T23	15		T25	21
all_pins[6]	transitions[0x1=>0x0]	770432	1			T20	29		T23	4		T25	16
all_pins[7]	values[0x0]	2110173	1			T20	64		T21	1		T22	1
all_pins[7]	values[0x1]	1289758	1			T20	46		T23	8		T25	23
all_pins[7]	transitions[0x0=>0x1]	771299	1			T20	26		T23	3		T25	16
all_pins[7]	transitions[0x1=>0x0]	770202	1			T20	29		T23	12		T25	24
all_pins[8]	values[0x0]	2117929	1			T20	53		T21	1		T22	1
all_pins[8]	values[0x1]	1282002	1			T20	57		T23	14		T25	27
all_pins[8]	transitions[0x0=>0x1]	766815	1			T20	32		T23	10		T25	16
all_pins[8]	transitions[0x1=>0x0]	774571	1			T20	21		T23	4		T25	12
all_pins[9]	values[0x0]	2116110	1			T20	53		T21	1		T22	1
all_pins[9]	values[0x1]	1283821	1			T20	57		T23	12		T25	44
all_pins[9]	transitions[0x0=>0x1]	771497	1			T20	27		T23	8		T25	25
all_pins[9]	transitions[0x1=>0x0]	769678	1			T20	27		T23	10		T25	8
all_pins[10]	values[0x0]	2111210	1			T20	58		T21	1		T22	1
all_pins[10]	values[0x1]	1288721	1			T20	52		T23	9		T25	28
all_pins[10]	transitions[0x0=>0x1]	770973	1			T20	23		T23	5		T25	5
all_pins[10]	transitions[0x1=>0x0]	766073	1			T20	28		T23	8		T25	21
all_pins[11]	values[0x0]	2112826	1			T20	58		T21	1		T22	1
all_pins[11]	values[0x1]	1287105	1			T20	52		T23	3		T25	18
all_pins[11]	transitions[0x0=>0x1]	770303	1			T20	24		T23	3		T25	16
all_pins[11]	transitions[0x1=>0x0]	771919	1			T20	24		T23	9		T25	26
all_pins[12]	values[0x0]	2110612	1			T20	44		T21	1		T22	1
all_pins[12]	values[0x1]	1289319	1			T20	66		T23	19		T25	30
all_pins[12]	transitions[0x0=>0x1]	773359	1			T20	35		T23	17		T25	20
all_pins[12]	transitions[0x1=>0x0]	771145	1			T20	21		T23	1		T25	8
all_pins[13]	values[0x0]	2113686	1			T20	64		T21	1		T22	1
all_pins[13]	values[0x1]	1286245	1			T20	46		T23	16		T25	45
all_pins[13]	transitions[0x0=>0x1]	769907	1			T20	19		T23	12		T25	28
all_pins[13]	transitions[0x1=>0x0]	772981	1			T20	39		T23	15		T25	13
all_pins[14]	values[0x0]	2113894	1			T20	57		T21	1		T22	1
all_pins[14]	values[0x1]	1286037	1			T20	53		T23	3		T25	12
all_pins[14]	transitions[0x0=>0x1]	769587	1			T20	30		T23	3		T25	4
all_pins[14]	transitions[0x1=>0x0]	769795	1			T20	23		T23	16		T25	37
all_pins[15]	values[0x0]	2111805	1			T20	51		T21	1		T22	1
all_pins[15]	values[0x1]	1288126	1			T20	59		T23	9		T25	11
all_pins[15]	transitions[0x0=>0x1]	772465	1			T20	33		T23	9		T25	9
all_pins[15]	transitions[0x1=>0x0]	770376	1			T20	27		T23	3		T25	10
all_pins[16]	values[0x0]	2109738	1			T20	49		T21	1		T22	1
all_pins[16]	values[0x1]	1290193	1			T20	61		T23	4		T25	23
all_pins[16]	transitions[0x0=>0x1]	772276	1			T20	26		T23	2		T25	16
all_pins[16]	transitions[0x1=>0x0]	770209	1			T20	24		T23	7		T25	4
all_pins[17]	values[0x0]	2108718	1			T20	56		T21	1		T22	1
all_pins[17]	values[0x1]	1291213	1			T20	54		T23	16		T25	30
all_pins[17]	transitions[0x0=>0x1]	771084	1			T20	22		T23	15		T25	19
all_pins[17]	transitions[0x1=>0x0]	770064	1			T20	29		T23	3		T25	12
all_pins[18]	values[0x0]	2111982	1			T20	53		T21	1		T22	1
all_pins[18]	values[0x1]	1287949	1			T20	57		T23	4		T25	25
all_pins[18]	transitions[0x0=>0x1]	768457	1			T20	26		T25	8		T28	12
all_pins[18]	transitions[0x1=>0x0]	771721	1			T20	23		T23	12		T25	13
all_pins[19]	values[0x0]	2112978	1			T20	47		T21	1		T22	1
all_pins[19]	values[0x1]	1286953	1			T20	63		T23	11		T25	33
all_pins[19]	transitions[0x0=>0x1]	769080	1			T20	28		T23	11		T25	25
all_pins[19]	transitions[0x1=>0x0]	770076	1			T20	22		T23	4		T25	17
all_pins[20]	values[0x0]	2109322	1			T20	44		T21	1		T22	1
all_pins[20]	values[0x1]	1290609	1			T20	66		T23	26		T25	6
all_pins[20]	transitions[0x0=>0x1]	771972	1			T20	29		T23	20		T28	12
all_pins[20]	transitions[0x1=>0x0]	768316	1			T20	26		T23	5		T25	27
all_pins[21]	values[0x0]	2113070	1			T20	55		T21	1		T22	1
all_pins[21]	values[0x1]	1286861	1			T20	55		T23	3		T25	31
all_pins[21]	transitions[0x0=>0x1]	770202	1			T20	26		T25	31		T28	14
all_pins[21]	transitions[0x1=>0x0]	773950	1			T20	37		T23	23		T25	6
all_pins[22]	values[0x0]	2108899	1			T20	54		T21	1		T22	1
all_pins[22]	values[0x1]	1291032	1			T20	56		T23	7		T25	27
all_pins[22]	transitions[0x0=>0x1]	776430	1			T20	33		T23	7		T25	15
all_pins[22]	transitions[0x1=>0x0]	772259	1			T20	32		T23	3		T25	19
all_pins[23]	values[0x0]	2113457	1			T20	59		T21	1		T22	1
all_pins[23]	values[0x1]	1286474	1			T20	51		T23	16		T25	31
all_pins[23]	transitions[0x0=>0x1]	770400	1			T20	24		T23	14		T25	16
all_pins[23]	transitions[0x1=>0x0]	774958	1			T20	29		T23	5		T25	12
all_pins[24]	values[0x0]	2115552	1			T20	45		T21	1		T22	1
all_pins[24]	values[0x1]	1284379	1			T20	65		T23	16		T25	36
all_pins[24]	transitions[0x0=>0x1]	769036	1			T20	33		T23	9		T25	18
all_pins[24]	transitions[0x1=>0x0]	771131	1			T20	19		T23	9		T25	13
all_pins[25]	values[0x0]	2110214	1			T20	51		T21	1		T22	1
all_pins[25]	values[0x1]	1289717	1			T20	59		T23	13		T25	29
all_pins[25]	transitions[0x0=>0x1]	773214	1			T20	24		T23	7		T25	22
all_pins[25]	transitions[0x1=>0x0]	767876	1			T20	30		T23	10		T25	29
all_pins[26]	values[0x0]	2115468	1			T20	56		T21	1		T22	1
all_pins[26]	values[0x1]	1284463	1			T20	54		T23	20		T25	23
all_pins[26]	transitions[0x0=>0x1]	768379	1			T20	19		T23	18		T25	13
all_pins[26]	transitions[0x1=>0x0]	773633	1			T20	24		T23	11		T25	19
all_pins[27]	values[0x0]	2106662	1			T20	56		T21	1		T22	1
all_pins[27]	values[0x1]	1293269	1			T20	54		T23	13		T25	14
all_pins[27]	transitions[0x0=>0x1]	775002	1			T20	28		T23	9		T25	10
all_pins[27]	transitions[0x1=>0x0]	766196	1			T20	28		T23	16		T25	19
all_pins[28]	values[0x0]	2110061	1			T20	59		T21	1		T22	1
all_pins[28]	values[0x1]	1289870	1			T20	51		T23	13		T25	35
all_pins[28]	transitions[0x0=>0x1]	769565	1			T20	20		T23	9		T25	28
all_pins[28]	transitions[0x1=>0x0]	772964	1			T20	23		T23	9		T25	7
all_pins[29]	values[0x0]	2113065	1			T20	69		T21	1		T22	1
all_pins[29]	values[0x1]	1286866	1			T20	41		T23	13		T25	9
all_pins[29]	transitions[0x0=>0x1]	770179	1			T20	20		T23	9		T25	3
all_pins[29]	transitions[0x1=>0x0]	773183	1			T20	30		T23	9		T25	29
all_pins[30]	values[0x0]	2112769	1			T20	63		T21	1		T22	1
all_pins[30]	values[0x1]	1287162	1			T20	47		T23	8		T25	26
all_pins[30]	transitions[0x0=>0x1]	771541	1			T20	29		T23	2		T25	18
all_pins[30]	transitions[0x1=>0x0]	771245	1			T20	23		T23	7		T25	1
all_pins[31]	values[0x0]	2114347	1			T20	49		T21	1		T22	1
all_pins[31]	values[0x1]	1285584	1			T20	61		T23	8		T25	27
all_pins[31]	transitions[0x0=>0x1]	768045	1			T20	32		T23	8		T25	12
all_pins[31]	transitions[0x1=>0x0]	769623	1			T20	18		T23	8		T25	11