Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[1]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[2]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[3]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[4]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[5]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[6]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[7]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[8]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[9]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[10]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[11]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[12]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[13]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[14]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[15]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[16]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[17]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[18]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[19]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[20]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[21]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[22]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[23]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[24]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[25]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[26]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[27]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[28]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[29]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[30]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[31]	11580789	1			T20	1749		T21	811		T22	397

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

216213615

1

T20

28261

T21

17943

T22

9283

auto[1]

154371633

1

T20

27707

T21

8009

T22

3421

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300048789

1

T20

55968

T21

16285

T22

7000

auto[1]

70536459

1

T21

9667

T22

5704

T23

252

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

279385082

1

T20

55968

T21

16238

T22

6963

auto[1]

91200166

1

T21

9714

T22

5741

T23

631

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4309988	1			T20	942		T21	259		T22	109
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3315849	1			T20	807		T21	99		T22	17
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1107446	1			T21	145		T22	83		T23	3
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1350245	1			T21	152		T22	82		T23	25
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	399077	1			T24	12		T29	3096		T52	96
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1098184	1			T21	156		T22	106		T24	4
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4296529	1			T20	907		T21	252		T22	115
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3322766	1			T20	842		T21	101		T22	20
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1107414	1			T21	154		T22	102		T27	42
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1347599	1			T21	146		T22	86		T23	5
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	403505	1			T23	13		T24	12		T29	3160
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1102976	1			T21	158		T22	74		T23	7
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4291212	1			T20	882		T21	245		T22	116
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3331033	1			T20	867		T21	99		T22	20
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1106567	1			T21	160		T22	98		T24	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1352074	1			T21	162		T22	77		T23	8
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	399241	1			T23	4		T24	25		T29	3170
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1100662	1			T21	145		T22	86		T24	18
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4288546	1			T20	773		T21	271		T22	80
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3330482	1			T20	976		T21	105		T22	18
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1108207	1			T21	128		T22	91		T23	4
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1349065	1			T21	159		T22	98		T23	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	401981	1			T23	10		T24	14		T29	3123
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1102508	1			T21	148		T22	110		T23	5
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4299910	1			T20	940		T21	277		T22	111
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3326024	1			T20	809		T21	100		T22	17
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1105924	1			T21	158		T22	78		T23	17
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1347797	1			T21	142		T22	101		T23	8
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	403584	1			T23	1		T24	24		T29	3230
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1097550	1			T21	134		T22	90		T24	10
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4293044	1			T20	925		T21	257		T22	88
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3321973	1			T20	824		T21	97		T22	18
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1108764	1			T21	118		T22	107		T23	5
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1349977	1			T21	165		T22	66		T23	7
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	402772	1			T23	9		T24	17		T29	3179
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1104259	1			T21	174		T22	118		T23	4
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4298112	1			T20	856		T21	208		T22	93
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3319357	1			T20	893		T21	106		T22	19
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1106905	1			T21	157		T22	106		T23	9
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1354471	1			T21	160		T22	97		T23	4
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	403498	1			T23	7		T24	27		T29	3195
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1098446	1			T21	180		T22	82		T23	12
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4311014	1			T20	955		T21	251		T22	103
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3311800	1			T20	794		T21	104		T22	17
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1111314	1			T21	124		T22	94		T23	3
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1343455	1			T21	184		T22	89		T23	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	401096	1			T23	11		T24	14		T29	2978
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1102110	1			T21	148		T22	94		T23	16
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4296480	1			T20	910		T21	270		T22	124
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3322008	1			T20	839		T21	104		T22	18
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1114797	1			T21	162		T22	52		T24	10
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1348978	1			T21	128		T22	110		T23	4
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	403030	1			T23	15		T24	11		T29	3264
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1095496	1			T21	147		T22	93		T23	10
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4285389	1			T20	945		T21	243		T22	122
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3331606	1			T20	804		T21	98		T22	14
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1114152	1			T21	142		T22	105		T23	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1349178	1			T21	178		T22	72		T23	13
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	401751	1			T23	12		T24	18		T29	3206
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1098713	1			T21	150		T22	84		T23	10
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4292724	1			T20	703		T21	256		T22	121
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3326705	1			T20	1046		T21	98		T22	17
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1109612	1			T21	209		T22	107		T23	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1351152	1			T21	108		T22	82		T23	16
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	401271	1			T23	11		T24	7		T29	3274
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1099325	1			T21	140		T22	70		T23	9
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4301611	1			T20	845		T21	240		T22	133
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3325087	1			T20	904		T21	100		T22	17
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1112080	1			T21	155		T22	75		T24	6
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1341808	1			T21	182		T22	98		T23	15
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	399756	1			T23	16		T24	15		T29	2978
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1100447	1			T21	134		T22	74		T23	5
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4301041	1			T20	853		T21	261		T22	113
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3319316	1			T20	896		T21	115		T22	17
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1109827	1			T21	132		T22	92		T24	13
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1348569	1			T21	155		T22	95		T23	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	401522	1			T23	6		T24	9		T29	3078
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1100514	1			T21	148		T22	80		T23	5
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4302551	1			T20	899		T21	227		T22	124
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3323012	1			T20	850		T21	102		T22	18
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1108363	1			T21	150		T22	84		T23	22
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1347056	1			T21	138		T22	99		T23	5
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	401372	1			T23	7		T24	17		T29	3165
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1098435	1			T21	194		T22	72		T23	12
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4300670	1			T20	819		T21	228		T22	104
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3321154	1			T20	930		T21	108		T22	21
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1106387	1			T21	164		T22	76		T23	3
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1353957	1			T21	150		T22	100		T23	5
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	402694	1			T23	8		T24	22		T29	2999
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1095927	1			T21	161		T22	96		T24	4
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4296836	1			T20	848		T21	259		T22	107
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3318465	1			T20	901		T21	91		T22	18
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1107742	1			T21	154		T22	84		T23	5
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1354907	1			T21	180		T22	100		T23	9
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	402560	1			T23	4		T24	17		T29	3243
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1100279	1			T21	127		T22	88		T24	4
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4296242	1			T20	914		T21	233		T22	112
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3327025	1			T20	835		T21	99		T22	18
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1103393	1			T21	147		T22	99		T23	6
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1356140	1			T21	138		T22	90		T23	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	405038	1			T24	14		T29	3189		T52	100
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1092951	1			T21	194		T22	78		T24	2
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4295136	1			T20	809		T21	252		T22	133
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3332521	1			T20	940		T21	102		T22	17
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1107039	1			T21	150		T22	75		T23	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1354087	1			T21	161		T22	90		T23	3
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	400571	1			T23	16		T24	19		T29	3139
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1091435	1			T21	146		T22	82		T23	3
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4316712	1			T20	928		T21	298		T22	108
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3318412	1			T20	821		T21	82		T22	20
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1109152	1			T21	136		T22	94		T24	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1340790	1			T21	163		T22	81		T23	3
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	399490	1			T23	13		T24	9		T29	3051
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1096233	1			T21	132		T22	94		T24	4
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4309821	1			T20	879		T21	297		T22	111
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3323331	1			T20	870		T21	93		T22	21
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1107943	1			T21	162		T22	90		T23	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1350193	1			T21	145		T22	92		T24	19
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	400212	1			T23	11		T24	2		T29	3102
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1089289	1			T21	114		T22	83		T24	4
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4295149	1			T20	1006		T21	254		T22	92
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3330522	1			T20	743		T21	98		T22	16
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1102134	1			T21	156		T22	70		T23	2
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1355169	1			T21	150		T22	116		T23	6
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	404004	1			T23	3		T24	7		T29	3409
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1093811	1			T21	153		T22	103		T27	39
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4288537	1			T20	819		T21	228		T22	97
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3338162	1			T20	930		T21	102		T22	21
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1104119	1			T21	218		T22	96		T23	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1354790	1			T21	133		T22	90		T23	1
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	400218	1			T23	17		T24	14		T29	3099
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1094963	1			T21	130		T22	93		T23	5
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4310764	1			T20	990		T21	213		T22	125
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3316452	1			T20	759		T21	101		T22	17
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1105031	1			T21	133		T22	83		T24	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1354347	1			T21	168		T22	90		T23	16
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	401387	1			T24	20		T29	3147		T52	98
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1092808	1			T21	196		T22	82		T24	12
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4301376	1			T20	848		T21	244		T22	109
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3323845	1			T20	901		T21	100		T22	19
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1105164	1			T21	124		T22	89		T27	31
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1352755	1			T21	191		T22	64		T23	20
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	400850	1			T23	1		T24	7		T29	3044
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1096799	1			T21	152		T22	116		T27	38
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4302892	1			T20	830		T21	308		T22	128
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3318320	1			T20	919		T21	103		T22	13
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1105728	1			T21	136		T22	88		T23	6
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1352036	1			T21	148		T22	80		T23	17
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	406828	1			T24	2		T29	3255		T52	147
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1094985	1			T21	116		T22	88		T24	2
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4294719	1			T20	890		T21	223		T22	106
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3328141	1			T20	859		T21	101		T22	18
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1102838	1			T21	160		T22	98		T23	8
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1353578	1			T21	151		T22	72		T23	8
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	403150	1			T23	4		T24	35		T29	3248
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1098363	1			T21	176		T22	103		T23	9
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4303770	1			T20	877		T21	283		T22	86
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3319869	1			T20	872		T21	83		T22	20
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1107514	1			T21	182		T22	91		T23	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1349826	1			T21	124		T22	102		T24	53
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	401149	1			T23	9		T24	17		T29	3160
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1098661	1			T21	139		T22	98		T23	2
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4296192	1			T20	883		T21	266		T22	108
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3331784	1			T20	866		T21	100		T22	18
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1104146	1			T21	134		T22	79		T23	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1353866	1			T21	145		T22	118		T23	9
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	402921	1			T23	3		T24	16		T29	3073
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1091880	1			T21	166		T22	74		T23	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4290324	1			T20	884		T21	244		T22	107
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3331461	1			T20	865		T21	98		T22	19
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1103950	1			T21	161		T22	95		T23	6
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1354458	1			T21	144		T22	90		T23	13
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	403996	1			T24	19		T29	3146		T52	128
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1096600	1			T21	164		T22	86		T24	2
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4293446	1			T20	951		T21	246		T22	90
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3333366	1			T20	798		T21	112		T22	20
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1105921	1			T21	161		T22	88		T24	4
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1350915	1			T21	164		T22	94		T23	14
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	401199	1			T23	13		T24	21		T29	3153
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1095942	1			T21	128		T22	105		T24	4
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4299640	1			T20	890		T21	280		T22	122
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3327116	1			T20	859		T21	96		T22	14
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1105311	1			T21	152		T22	78		T23	4
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1353331	1			T21	147		T22	100		T23	4
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	402699	1			T23	6		T24	21		T29	3132
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1092692	1			T21	136		T22	83		T23	5
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4297237	1			T20	861		T21	311		T22	131
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3331118	1			T20	888		T21	101		T22	19
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1104502	1			T21	132		T22	112		T23	4
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1350046	1			T21	142		T22	75		T23	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	404056	1			T23	13		T24	17		T29	3139
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1093830	1			T21	125		T22	60		T23	1

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal