Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[1]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[2]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[3]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[4]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[5]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[6]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[7]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[8]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[9]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[10]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[11]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[12]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[13]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[14]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[15]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[16]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[17]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[18]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[19]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[20]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[21]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[22]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[23]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[24]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[25]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[26]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[27]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[28]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[29]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[30]	11580789	1			T20	1749		T21	811		T22	397
bins_for_gpio_bits[31]	11580789	1			T20	1749		T21	811		T22	397

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

216213615

1

T20

28261

T21

17943

T22

9283

auto[1]

154371633

1

T20

27707

T21

8009

T22

3421

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

216207068

1

T20

28261

T21

17936

T22

9276

auto[1]

154378180

1

T20

27707

T21

8016

T22

3428

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6569874	1			T20	942		T21	515		T22	253
bins_for_gpio_bits[0]	auto[0]	auto[1]	197620	1			T21	41		T22	21		T24	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	197805	1			T21	41		T22	21		T24	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	4615490	1			T20	807		T21	214		T22	102
bins_for_gpio_bits[1]	auto[0]	auto[0]	6554390	1			T20	907		T21	510		T22	286
bins_for_gpio_bits[1]	auto[0]	auto[1]	196927	1			T21	42		T22	17		T24	4
bins_for_gpio_bits[1]	auto[1]	auto[0]	197152	1			T21	42		T22	17		T24	4
bins_for_gpio_bits[1]	auto[1]	auto[1]	4632320	1			T20	842		T21	217		T22	77
bins_for_gpio_bits[2]	auto[0]	auto[0]	6552057	1			T20	882		T21	530		T22	267
bins_for_gpio_bits[2]	auto[0]	auto[1]	197582	1			T21	36		T22	24		T24	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	197796	1			T21	37		T22	24		T24	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	4633354	1			T20	867		T21	208		T22	82
bins_for_gpio_bits[3]	auto[0]	auto[0]	6548616	1			T20	773		T21	517		T22	246
bins_for_gpio_bits[3]	auto[0]	auto[1]	197004	1			T21	41		T22	23		T24	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	197202	1			T21	41		T22	23		T24	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	4637967	1			T20	976		T21	212		T22	105
bins_for_gpio_bits[4]	auto[0]	auto[0]	6556330	1			T20	940		T21	537		T22	266
bins_for_gpio_bits[4]	auto[0]	auto[1]	197091	1			T21	40		T22	24		T23	1
bins_for_gpio_bits[4]	auto[1]	auto[0]	197301	1			T21	40		T22	24		T24	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	4630067	1			T20	809		T21	194		T22	83
bins_for_gpio_bits[5]	auto[0]	auto[0]	6554021	1			T20	925		T21	501		T22	237
bins_for_gpio_bits[5]	auto[0]	auto[1]	197543	1			T21	39		T22	24		T23	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	197764	1			T21	39		T22	24		T23	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	4631461	1			T20	824		T21	232		T22	112
bins_for_gpio_bits[6]	auto[0]	auto[0]	6561791	1			T20	856		T21	482		T22	271
bins_for_gpio_bits[6]	auto[0]	auto[1]	197542	1			T21	43		T22	25		T23	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	197697	1			T21	43		T22	25		T23	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	4623759	1			T20	893		T21	243		T22	76
bins_for_gpio_bits[7]	auto[0]	auto[0]	6568296	1			T20	955		T21	520		T22	264
bins_for_gpio_bits[7]	auto[0]	auto[1]	197281	1			T21	39		T22	22		T24	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	197487	1			T21	39		T22	22		T24	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	4617725	1			T20	794		T21	213		T22	89
bins_for_gpio_bits[8]	auto[0]	auto[0]	6563481	1			T20	910		T21	521		T22	262
bins_for_gpio_bits[8]	auto[0]	auto[1]	196539	1			T21	38		T22	23		T24	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	196774	1			T21	39		T22	24		T24	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	4623995	1			T20	839		T21	213		T22	88
bins_for_gpio_bits[9]	auto[0]	auto[0]	6551062	1			T20	945		T21	525		T22	276
bins_for_gpio_bits[9]	auto[0]	auto[1]	197461	1			T21	38		T22	23		T24	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	197657	1			T21	38		T22	23		T24	3
bins_for_gpio_bits[9]	auto[1]	auto[1]	4634609	1			T20	804		T21	210		T22	75
bins_for_gpio_bits[10]	auto[0]	auto[0]	6555318	1			T20	703		T21	538		T22	291
bins_for_gpio_bits[10]	auto[0]	auto[1]	198002	1			T21	35		T22	19		T24	1
bins_for_gpio_bits[10]	auto[1]	auto[0]	198170	1			T21	35		T22	19		T24	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	4629299	1			T20	1046		T21	203		T22	68
bins_for_gpio_bits[11]	auto[0]	auto[0]	6558422	1			T20	845		T21	537		T22	283
bins_for_gpio_bits[11]	auto[0]	auto[1]	196855	1			T21	40		T22	23		T24	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	197077	1			T21	40		T22	23		T24	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	4628435	1			T20	904		T21	194		T22	68
bins_for_gpio_bits[12]	auto[0]	auto[0]	6561769	1			T20	853		T21	509		T22	280
bins_for_gpio_bits[12]	auto[0]	auto[1]	197455	1			T21	39		T22	20		T24	2
bins_for_gpio_bits[12]	auto[1]	auto[0]	197668	1			T21	39		T22	20		T24	2
bins_for_gpio_bits[12]	auto[1]	auto[1]	4623897	1			T20	896		T21	224		T22	77
bins_for_gpio_bits[13]	auto[0]	auto[0]	6560463	1			T20	899		T21	467		T22	283
bins_for_gpio_bits[13]	auto[0]	auto[1]	197302	1			T21	48		T22	24		T23	1
bins_for_gpio_bits[13]	auto[1]	auto[0]	197507	1			T21	48		T22	24		T24	2
bins_for_gpio_bits[13]	auto[1]	auto[1]	4625517	1			T20	850		T21	248		T22	66
bins_for_gpio_bits[14]	auto[0]	auto[0]	6563418	1			T20	819		T21	501		T22	255
bins_for_gpio_bits[14]	auto[0]	auto[1]	197372	1			T21	40		T22	25		T24	2
bins_for_gpio_bits[14]	auto[1]	auto[0]	197596	1			T21	41		T22	25		T24	2
bins_for_gpio_bits[14]	auto[1]	auto[1]	4622403	1			T20	930		T21	229		T22	92
bins_for_gpio_bits[15]	auto[0]	auto[0]	6562849	1			T20	848		T21	559		T22	270
bins_for_gpio_bits[15]	auto[0]	auto[1]	196442	1			T21	33		T22	21		T24	2
bins_for_gpio_bits[15]	auto[1]	auto[0]	196636	1			T21	34		T22	21		T24	2
bins_for_gpio_bits[15]	auto[1]	auto[1]	4624862	1			T20	901		T21	185		T22	85
bins_for_gpio_bits[16]	auto[0]	auto[0]	6558456	1			T20	914		T21	482		T22	275
bins_for_gpio_bits[16]	auto[0]	auto[1]	197091	1			T21	36		T22	26		T23	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	197319	1			T21	36		T22	26		T23	1
bins_for_gpio_bits[16]	auto[1]	auto[1]	4627923	1			T20	835		T21	257		T22	70
bins_for_gpio_bits[17]	auto[0]	auto[0]	6559280	1			T20	809		T21	523		T22	275
bins_for_gpio_bits[17]	auto[0]	auto[1]	196793	1			T21	40		T22	23		T23	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	196982	1			T21	40		T22	23		T23	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	4627734	1			T20	940		T21	208		T22	76
bins_for_gpio_bits[18]	auto[0]	auto[0]	6569209	1			T20	928		T21	563		T22	260
bins_for_gpio_bits[18]	auto[0]	auto[1]	197181	1			T21	34		T22	23		T24	1
bins_for_gpio_bits[18]	auto[1]	auto[0]	197445	1			T21	34		T22	23		T24	1
bins_for_gpio_bits[18]	auto[1]	auto[1]	4616954	1			T20	821		T21	180		T22	91
bins_for_gpio_bits[19]	auto[0]	auto[0]	6571391	1			T20	879		T21	569		T22	268
bins_for_gpio_bits[19]	auto[0]	auto[1]	196351	1			T21	35		T22	24		T23	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	196566	1			T21	35		T22	25		T23	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	4616481	1			T20	870		T21	172		T22	80
bins_for_gpio_bits[20]	auto[0]	auto[0]	6555134	1			T20	1006		T21	523		T22	250
bins_for_gpio_bits[20]	auto[0]	auto[1]	197121	1			T21	36		T22	27		T27	9
bins_for_gpio_bits[20]	auto[1]	auto[0]	197318	1			T21	37		T22	28		T27	10
bins_for_gpio_bits[20]	auto[1]	auto[1]	4631216	1			T20	743		T21	215		T22	92
bins_for_gpio_bits[21]	auto[0]	auto[0]	6549521	1			T20	819		T21	544		T22	264
bins_for_gpio_bits[21]	auto[0]	auto[1]	197728	1			T21	35		T22	18		T24	3
bins_for_gpio_bits[21]	auto[1]	auto[0]	197925	1			T21	35		T22	19		T24	3
bins_for_gpio_bits[21]	auto[1]	auto[1]	4635615	1			T20	930		T21	197		T22	96
bins_for_gpio_bits[22]	auto[0]	auto[0]	6572830	1			T20	990		T21	468		T22	275
bins_for_gpio_bits[22]	auto[0]	auto[1]	197100	1			T21	46		T22	23		T24	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	197312	1			T21	46		T22	23		T24	2
bins_for_gpio_bits[22]	auto[1]	auto[1]	4613547	1			T20	759		T21	251		T22	76
bins_for_gpio_bits[23]	auto[0]	auto[0]	6561813	1			T20	848		T21	520		T22	240
bins_for_gpio_bits[23]	auto[0]	auto[1]	197296	1			T21	39		T22	22		T27	10
bins_for_gpio_bits[23]	auto[1]	auto[0]	197482	1			T21	39		T22	22		T27	10
bins_for_gpio_bits[23]	auto[1]	auto[1]	4624198	1			T20	901		T21	213		T22	113
bins_for_gpio_bits[24]	auto[0]	auto[0]	6563433	1			T20	830		T21	561		T22	274
bins_for_gpio_bits[24]	auto[0]	auto[1]	197027	1			T21	31		T22	22		T24	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	197223	1			T21	31		T22	22		T24	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	4623106	1			T20	919		T21	188		T22	79
bins_for_gpio_bits[25]	auto[0]	auto[0]	6554192	1			T20	890		T21	494		T22	251
bins_for_gpio_bits[25]	auto[0]	auto[1]	196782	1			T21	40		T22	24		T23	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	196943	1			T21	40		T22	25		T23	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	4632872	1			T20	859		T21	237		T22	97
bins_for_gpio_bits[26]	auto[0]	auto[0]	6563733	1			T20	877		T21	555		T22	254
bins_for_gpio_bits[26]	auto[0]	auto[1]	197171	1			T21	33		T22	25		T24	3
bins_for_gpio_bits[26]	auto[1]	auto[0]	197377	1			T21	34		T22	25		T24	3
bins_for_gpio_bits[26]	auto[1]	auto[1]	4622508	1			T20	872		T21	189		T22	93
bins_for_gpio_bits[27]	auto[0]	auto[0]	6557152	1			T20	883		T21	504		T22	281
bins_for_gpio_bits[27]	auto[0]	auto[1]	196862	1			T21	41		T22	24		T23	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	197052	1			T21	41		T22	24		T23	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	4629723	1			T20	866		T21	225		T22	68
bins_for_gpio_bits[28]	auto[0]	auto[0]	6551383	1			T20	884		T21	507		T22	267
bins_for_gpio_bits[28]	auto[0]	auto[1]	197116	1			T21	42		T22	25		T24	1
bins_for_gpio_bits[28]	auto[1]	auto[0]	197349	1			T21	42		T22	25		T24	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	4634941	1			T20	865		T21	220		T22	80
bins_for_gpio_bits[29]	auto[0]	auto[0]	6552655	1			T20	951		T21	539		T22	250
bins_for_gpio_bits[29]	auto[0]	auto[1]	197456	1			T21	32		T22	21		T24	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	197627	1			T21	32		T22	22		T24	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	4633051	1			T20	798		T21	208		T22	104
bins_for_gpio_bits[30]	auto[0]	auto[0]	6561021	1			T20	890		T21	543		T22	277
bins_for_gpio_bits[30]	auto[0]	auto[1]	197043	1			T21	36		T22	22		T24	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	197261	1			T21	36		T22	23		T24	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	4625464	1			T20	859		T21	196		T22	75
bins_for_gpio_bits[31]	auto[0]	auto[0]	6554800	1			T20	861		T21	558		T22	300
bins_for_gpio_bits[31]	auto[0]	auto[1]	196772	1			T21	26		T22	18		T23	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	196985	1			T21	27		T22	18		T23	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	4632232	1			T20	888		T21	200		T22	61