Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11146630 |
1 |
|
|
T20 |
1749 |
|
T21 |
505 |
|
T22 |
217 |
| auto[1] |
615749 |
1 |
|
|
T23 |
4 |
|
T25 |
1 |
|
T29 |
17898 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6976004 |
1 |
|
|
T20 |
1749 |
|
T21 |
505 |
|
T22 |
217 |
| auto[1] |
4786375 |
1 |
|
|
T23 |
51 |
|
T25 |
39 |
|
T29 |
143181 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2092977 |
1 |
|
|
T23 |
26 |
|
T25 |
17 |
|
T29 |
66450 |
| auto[1] |
auto[0] |
auto[1] |
309558 |
1 |
|
|
T23 |
2 |
|
T25 |
1 |
|
T29 |
9736 |
| auto[1] |
auto[1] |
auto[0] |
2077649 |
1 |
|
|
T23 |
21 |
|
T25 |
21 |
|
T29 |
58833 |
| auto[1] |
auto[1] |
auto[1] |
306191 |
1 |
|
|
T23 |
2 |
|
T29 |
8162 |
|
T112 |
96 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |