Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6995510 |
1 |
|
|
T20 |
1749 |
|
T21 |
505 |
|
T22 |
217 |
| auto[1] |
4766869 |
1 |
|
|
T23 |
14 |
|
T25 |
32 |
|
T29 |
145036 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9760353 |
1 |
|
|
T20 |
1749 |
|
T21 |
505 |
|
T22 |
217 |
| auto[1] |
2002026 |
1 |
|
|
T23 |
3 |
|
T25 |
11 |
|
T29 |
51476 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6997623 |
1 |
|
|
T20 |
1749 |
|
T21 |
505 |
|
T22 |
217 |
| auto[1] |
4764756 |
1 |
|
|
T23 |
15 |
|
T25 |
30 |
|
T29 |
139325 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1386242 |
1 |
|
|
T23 |
4 |
|
T25 |
10 |
|
T29 |
41852 |
| auto[1] |
auto[0] |
auto[1] |
1005676 |
1 |
|
|
T23 |
3 |
|
T25 |
7 |
|
T29 |
25166 |
| auto[1] |
auto[1] |
auto[0] |
1376488 |
1 |
|
|
T23 |
8 |
|
T25 |
9 |
|
T29 |
45997 |
| auto[1] |
auto[1] |
auto[1] |
996350 |
1 |
|
|
T25 |
4 |
|
T29 |
26310 |
|
T112 |
280 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |