Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6985526 |
1 |
|
|
T20 |
1749 |
|
T21 |
505 |
|
T22 |
217 |
| auto[1] |
4776853 |
1 |
|
|
T23 |
17 |
|
T25 |
67 |
|
T29 |
145297 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9764797 |
1 |
|
|
T20 |
1749 |
|
T21 |
505 |
|
T22 |
217 |
| auto[1] |
1997582 |
1 |
|
|
T23 |
8 |
|
T25 |
43 |
|
T29 |
51396 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7007207 |
1 |
|
|
T20 |
1749 |
|
T21 |
505 |
|
T22 |
217 |
| auto[1] |
4755172 |
1 |
|
|
T23 |
26 |
|
T25 |
62 |
|
T29 |
138552 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1377965 |
1 |
|
|
T23 |
17 |
|
T25 |
4 |
|
T29 |
42551 |
| auto[1] |
auto[0] |
auto[1] |
999973 |
1 |
|
|
T23 |
6 |
|
T25 |
17 |
|
T29 |
25113 |
| auto[1] |
auto[1] |
auto[0] |
1379625 |
1 |
|
|
T23 |
1 |
|
T25 |
15 |
|
T29 |
44605 |
| auto[1] |
auto[1] |
auto[1] |
997609 |
1 |
|
|
T23 |
2 |
|
T25 |
26 |
|
T29 |
26283 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |