Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4918485	1			T21	535		T22	1		T23	24204
all_pins[1]	4918485	1			T21	535		T22	1		T23	24204
all_pins[2]	4918485	1			T21	535		T22	1		T23	24204
all_pins[3]	4918485	1			T21	535		T22	1		T23	24204
all_pins[4]	4918485	1			T21	535		T22	1		T23	24204
all_pins[5]	4918485	1			T21	535		T22	1		T23	24204
all_pins[6]	4918485	1			T21	535		T22	1		T23	24204
all_pins[7]	4918485	1			T21	535		T22	1		T23	24204
all_pins[8]	4918485	1			T21	535		T22	1		T23	24204
all_pins[9]	4918485	1			T21	535		T22	1		T23	24204
all_pins[10]	4918485	1			T21	535		T22	1		T23	24204
all_pins[11]	4918485	1			T21	535		T22	1		T23	24204
all_pins[12]	4918485	1			T21	535		T22	1		T23	24204
all_pins[13]	4918485	1			T21	535		T22	1		T23	24204
all_pins[14]	4918485	1			T21	535		T22	1		T23	24204
all_pins[15]	4918485	1			T21	535		T22	1		T23	24204
all_pins[16]	4918485	1			T21	535		T22	1		T23	24204
all_pins[17]	4918485	1			T21	535		T22	1		T23	24204
all_pins[18]	4918485	1			T21	535		T22	1		T23	24204
all_pins[19]	4918485	1			T21	535		T22	1		T23	24204
all_pins[20]	4918485	1			T21	535		T22	1		T23	24204
all_pins[21]	4918485	1			T21	535		T22	1		T23	24204
all_pins[22]	4918485	1			T21	535		T22	1		T23	24204
all_pins[23]	4918485	1			T21	535		T22	1		T23	24204
all_pins[24]	4918485	1			T21	535		T22	1		T23	24204
all_pins[25]	4918485	1			T21	535		T22	1		T23	24204
all_pins[26]	4918485	1			T21	535		T22	1		T23	24204
all_pins[27]	4918485	1			T21	535		T22	1		T23	24204
all_pins[28]	4918485	1			T21	535		T22	1		T23	24204
all_pins[29]	4918485	1			T21	535		T22	1		T23	24204
all_pins[30]	4918485	1			T21	535		T22	1		T23	24204
all_pins[31]	4918485	1			T21	535		T22	1		T23	24204

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	97743147	1			T21	10607		T22	32		T23	485283
values[0x1]	59648373	1			T21	6513		T23	289245		T25	7534
transitions[0x0=>0x1]	35752199	1			T21	3877		T23	175580		T25	4379
transitions[0x1=>0x0]	35752064	1			T21	3877		T23	175579		T25	4379

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3048361	1			T21	311		T22	1		T23	15135
all_pins[0]	values[0x1]	1870124	1			T21	224		T23	9069		T25	249
all_pins[0]	transitions[0x0=>0x1]	1161277	1			T21	141		T23	5599		T25	129
all_pins[0]	transitions[0x1=>0x0]	1148807	1			T21	103		T23	5405		T25	129
all_pins[1]	values[0x0]	3053634	1			T21	271		T22	1		T23	14965
all_pins[1]	values[0x1]	1864851	1			T21	264		T23	9239		T25	205
all_pins[1]	transitions[0x0=>0x1]	1116070	1			T21	133		T23	5625		T25	135
all_pins[1]	transitions[0x1=>0x0]	1121343	1			T21	93		T23	5455		T25	179
all_pins[2]	values[0x0]	3059810	1			T21	302		T22	1		T23	14630
all_pins[2]	values[0x1]	1858675	1			T21	233		T23	9574		T25	268
all_pins[2]	transitions[0x0=>0x1]	1114949	1			T21	123		T23	5667		T25	214
all_pins[2]	transitions[0x1=>0x0]	1121125	1			T21	154		T23	5332		T25	151
all_pins[3]	values[0x0]	3052866	1			T21	317		T22	1		T23	14968
all_pins[3]	values[0x1]	1865619	1			T21	218		T23	9236		T25	270
all_pins[3]	transitions[0x0=>0x1]	1120392	1			T21	113		T23	5398		T25	122
all_pins[3]	transitions[0x1=>0x0]	1113448	1			T21	128		T23	5736		T25	120
all_pins[4]	values[0x0]	3053725	1			T21	348		T22	1		T23	15260
all_pins[4]	values[0x1]	1864760	1			T21	187		T23	8944		T25	231
all_pins[4]	transitions[0x0=>0x1]	1112908	1			T21	83		T23	5391		T25	146
all_pins[4]	transitions[0x1=>0x0]	1113767	1			T21	114		T23	5683		T25	185
all_pins[5]	values[0x0]	3053195	1			T21	324		T22	1		T23	15457
all_pins[5]	values[0x1]	1865290	1			T21	211		T23	8747		T25	266
all_pins[5]	transitions[0x0=>0x1]	1119094	1			T21	166		T23	5482		T25	180
all_pins[5]	transitions[0x1=>0x0]	1118564	1			T21	142		T23	5679		T25	145
all_pins[6]	values[0x0]	3050854	1			T21	298		T22	1		T23	15147
all_pins[6]	values[0x1]	1867631	1			T21	237		T23	9057		T25	203
all_pins[6]	transitions[0x0=>0x1]	1114592	1			T21	122		T23	5703		T25	97
all_pins[6]	transitions[0x1=>0x0]	1112251	1			T21	96		T23	5393		T25	160
all_pins[7]	values[0x0]	3058560	1			T21	314		T22	1		T23	15499
all_pins[7]	values[0x1]	1859925	1			T21	221		T23	8705		T25	281
all_pins[7]	transitions[0x0=>0x1]	1112442	1			T21	139		T23	5211		T25	167
all_pins[7]	transitions[0x1=>0x0]	1120148	1			T21	155		T23	5563		T25	89
all_pins[8]	values[0x0]	3053445	1			T21	333		T22	1		T23	14980
all_pins[8]	values[0x1]	1865040	1			T21	202		T23	9224		T25	264
all_pins[8]	transitions[0x0=>0x1]	1119630	1			T21	104		T23	5708		T25	117
all_pins[8]	transitions[0x1=>0x0]	1114515	1			T21	123		T23	5189		T25	134
all_pins[9]	values[0x0]	3054078	1			T21	313		T22	1		T23	14997
all_pins[9]	values[0x1]	1864407	1			T21	222		T23	9207		T25	221
all_pins[9]	transitions[0x0=>0x1]	1118244	1			T21	124		T23	5575		T25	148
all_pins[9]	transitions[0x1=>0x0]	1118877	1			T21	104		T23	5592		T25	191
all_pins[10]	values[0x0]	3057959	1			T21	380		T22	1		T23	14952
all_pins[10]	values[0x1]	1860526	1			T21	155		T23	9252		T25	199
all_pins[10]	transitions[0x0=>0x1]	1112145	1			T21	95		T23	5431		T25	109
all_pins[10]	transitions[0x1=>0x0]	1116026	1			T21	162		T23	5386		T25	131
all_pins[11]	values[0x0]	3049553	1			T21	410		T22	1		T23	15138
all_pins[11]	values[0x1]	1868932	1			T21	125		T23	9066		T25	286
all_pins[11]	transitions[0x0=>0x1]	1120799	1			T21	93		T23	5516		T25	183
all_pins[11]	transitions[0x1=>0x0]	1112393	1			T21	123		T23	5702		T25	96
all_pins[12]	values[0x0]	3058196	1			T21	347		T22	1		T23	15475
all_pins[12]	values[0x1]	1860289	1			T21	188		T23	8729		T25	203
all_pins[12]	transitions[0x0=>0x1]	1111792	1			T21	135		T23	5373		T25	94
all_pins[12]	transitions[0x1=>0x0]	1120435	1			T21	72		T23	5710		T25	177
all_pins[13]	values[0x0]	3060265	1			T21	359		T22	1		T23	15442
all_pins[13]	values[0x1]	1858220	1			T21	176		T23	8762		T25	256
all_pins[13]	transitions[0x0=>0x1]	1113114	1			T21	100		T23	5373		T25	137
all_pins[13]	transitions[0x1=>0x0]	1115183	1			T21	112		T23	5340		T25	84
all_pins[14]	values[0x0]	3054643	1			T21	334		T22	1		T23	15376
all_pins[14]	values[0x1]	1863842	1			T21	201		T23	8828		T25	194
all_pins[14]	transitions[0x0=>0x1]	1115735	1			T21	107		T23	5463		T25	103
all_pins[14]	transitions[0x1=>0x0]	1110113	1			T21	82		T23	5397		T25	165
all_pins[15]	values[0x0]	3053754	1			T21	313		T22	1		T23	15183
all_pins[15]	values[0x1]	1864731	1			T21	222		T23	9021		T25	283
all_pins[15]	transitions[0x0=>0x1]	1118218	1			T21	121		T23	5544		T25	185
all_pins[15]	transitions[0x1=>0x0]	1117329	1			T21	100		T23	5351		T25	96
all_pins[16]	values[0x0]	3057141	1			T21	370		T22	1		T23	14977
all_pins[16]	values[0x1]	1861344	1			T21	165		T23	9227		T25	229
all_pins[16]	transitions[0x0=>0x1]	1112360	1			T21	112		T23	5712		T25	88
all_pins[16]	transitions[0x1=>0x0]	1115747	1			T21	169		T23	5506		T25	142
all_pins[17]	values[0x0]	3053703	1			T21	318		T22	1		T23	14599
all_pins[17]	values[0x1]	1864782	1			T21	217		T23	9605		T25	230
all_pins[17]	transitions[0x0=>0x1]	1118419	1			T21	151		T23	5682		T25	109
all_pins[17]	transitions[0x1=>0x0]	1114981	1			T21	99		T23	5304		T25	108
all_pins[18]	values[0x0]	3057702	1			T21	341		T22	1		T23	15110
all_pins[18]	values[0x1]	1860783	1			T21	194		T23	9094		T25	266
all_pins[18]	transitions[0x0=>0x1]	1115814	1			T21	105		T23	5416		T25	146
all_pins[18]	transitions[0x1=>0x0]	1119813	1			T21	128		T23	5927		T25	110
all_pins[19]	values[0x0]	3055122	1			T21	340		T22	1		T23	15151
all_pins[19]	values[0x1]	1863363	1			T21	195		T23	9053		T25	247
all_pins[19]	transitions[0x0=>0x1]	1115779	1			T21	125		T23	5407		T25	148
all_pins[19]	transitions[0x1=>0x0]	1113199	1			T21	124		T23	5448		T25	167
all_pins[20]	values[0x0]	3057591	1			T21	383		T22	1		T23	15481
all_pins[20]	values[0x1]	1860894	1			T21	152		T23	8723		T25	231
all_pins[20]	transitions[0x0=>0x1]	1114279	1			T21	91		T23	5146		T25	117
all_pins[20]	transitions[0x1=>0x0]	1116748	1			T21	134		T23	5476		T25	133
all_pins[21]	values[0x0]	3061565	1			T21	357		T22	1		T23	15063
all_pins[21]	values[0x1]	1856920	1			T21	178		T23	9141		T25	285
all_pins[21]	transitions[0x0=>0x1]	1112083	1			T21	142		T23	5796		T25	191
all_pins[21]	transitions[0x1=>0x0]	1116057	1			T21	116		T23	5378		T25	137
all_pins[22]	values[0x0]	3056149	1			T21	321		T22	1		T23	15456
all_pins[22]	values[0x1]	1862336	1			T21	214		T23	8748		T25	258
all_pins[22]	transitions[0x0=>0x1]	1116009	1			T21	153		T23	5201		T25	120
all_pins[22]	transitions[0x1=>0x0]	1110593	1			T21	117		T23	5594		T25	147
all_pins[23]	values[0x0]	3051560	1			T21	296		T22	1		T23	14973
all_pins[23]	values[0x1]	1866925	1			T21	239		T23	9231		T25	213
all_pins[23]	transitions[0x0=>0x1]	1119698	1			T21	142		T23	5764		T25	120
all_pins[23]	transitions[0x1=>0x0]	1115109	1			T21	117		T23	5281		T25	165
all_pins[24]	values[0x0]	3050620	1			T21	346		T22	1		T23	15248
all_pins[24]	values[0x1]	1867865	1			T21	189		T23	8956		T25	214
all_pins[24]	transitions[0x0=>0x1]	1116859	1			T21	91		T23	5304		T25	130
all_pins[24]	transitions[0x1=>0x0]	1115919	1			T21	141		T23	5579		T25	129
all_pins[25]	values[0x0]	3045650	1			T21	325		T22	1		T23	15289
all_pins[25]	values[0x1]	1872835	1			T21	210		T23	8915		T25	208
all_pins[25]	transitions[0x0=>0x1]	1118923	1			T21	125		T23	5419		T25	129
all_pins[25]	transitions[0x1=>0x0]	1113953	1			T21	104		T23	5460		T25	135
all_pins[26]	values[0x0]	3052032	1			T21	345		T22	1		T23	14616
all_pins[26]	values[0x1]	1866453	1			T21	190		T23	9588		T25	169
all_pins[26]	transitions[0x0=>0x1]	1114381	1			T21	114		T23	5765		T25	92
all_pins[26]	transitions[0x1=>0x0]	1120763	1			T21	134		T23	5092		T25	131
all_pins[27]	values[0x0]	3056649	1			T21	366		T22	1		T23	15204
all_pins[27]	values[0x1]	1861836	1			T21	169		T23	9000		T25	195
all_pins[27]	transitions[0x0=>0x1]	1112245	1			T21	93		T23	5320		T25	150
all_pins[27]	transitions[0x1=>0x0]	1116862	1			T21	114		T23	5908		T25	124
all_pins[28]	values[0x0]	3042272	1			T21	337		T22	1		T23	15454
all_pins[28]	values[0x1]	1876213	1			T21	198		T23	8750		T25	269
all_pins[28]	transitions[0x0=>0x1]	1124738	1			T21	136		T23	5352		T25	182
all_pins[28]	transitions[0x1=>0x0]	1110361	1			T21	107		T23	5602		T25	108
all_pins[29]	values[0x0]	3052678	1			T21	256		T22	1		T23	15477
all_pins[29]	values[0x1]	1865807	1			T21	279		T23	8727		T25	215
all_pins[29]	transitions[0x0=>0x1]	1111339	1			T21	182		T23	5485		T25	105
all_pins[29]	transitions[0x1=>0x0]	1121745	1			T21	101		T23	5508		T25	159
all_pins[30]	values[0x0]	3059119	1			T21	283		T22	1		T23	15253
all_pins[30]	values[0x1]	1859366	1			T21	252		T23	8951		T25	177
all_pins[30]	transitions[0x0=>0x1]	1111952	1			T21	95		T23	5368		T25	110
all_pins[30]	transitions[0x1=>0x0]	1118393	1			T21	122		T23	5144		T25	148
all_pins[31]	values[0x0]	3060696	1			T21	349		T22	1		T23	15328
all_pins[31]	values[0x1]	1857789	1			T21	186		T23	8876		T25	249
all_pins[31]	transitions[0x0=>0x1]	1115920	1			T21	121		T23	5384		T25	176
all_pins[31]	transitions[0x1=>0x0]	1117497	1			T21	187		T23	5459		T25	104