Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[1]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[2]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[3]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[4]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[5]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[6]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[7]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[8]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[9]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[10]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[11]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[12]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[13]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[14]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[15]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[16]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[17]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[18]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[19]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[20]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[21]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[22]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[23]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[24]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[25]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[26]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[27]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[28]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[29]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[30]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[31]	15728977	1			T21	1334		T22	1		T23	70947

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305442001

1

T21

32747

T22

32

T23

147684

auto[1]

197885263

1

T21

9941

T23

793460

T24

2087

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

403041666

1

T21

24235

T22

32

T23

179995

auto[1]

100285598

1

T21

18453

T23

470348

T24

474

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

373946891

1

T21

21239

T22

32

T23

164093

auto[1]

129380373

1

T21

21449

T23

629373

T24

3599

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5905987	1			T21	242		T22	1		T23	27328
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4204436	1			T21	3		T23	16773		T24	38
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1572291	1			T21	261		T23	7500		T24	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2063743	1			T21	448		T23	11444		T24	75
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	416997	1			T21	14		T23	885		T24	18
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1565523	1			T21	366		T23	7017		T1	360
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5894097	1			T21	308		T22	1		T23	27311
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4212942	1			T21	8		T23	16534		T24	27
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1576845	1			T21	296		T23	7388		T24	7
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2067644	1			T21	352		T23	11507		T24	84
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	416486	1			T21	16		T23	964		T24	30
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1560963	1			T21	354		T23	7243		T24	9
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5908187	1			T21	294		T22	1		T23	27078
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4203043	1			T21	11		T23	16508		T24	9
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1582817	1			T21	301		T23	7265		T24	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2060013	1			T21	376		T23	11629		T24	155
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	417730	1			T21	10		T23	995		T24	49
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1557187	1			T21	342		T23	7472		T24	14
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5894694	1			T21	352		T22	1		T23	27225
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4210579	1			T21	16		T23	16350		T24	28
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1576587	1			T21	276		T23	7439		T24	9
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2062039	1			T21	399		T23	11771		T24	104
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	419283	1			T21	10		T23	960		T24	39
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1565795	1			T21	281		T23	7202		T24	7
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5908002	1			T21	510		T22	1		T23	27316
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4201966	1			T21	15		T23	16492		T24	44
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1578268	1			T21	307		T23	7296		T24	14
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2060923	1			T21	319		T23	11445		T24	50
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	416941	1			T21	7		T23	963		T24	22
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1562877	1			T21	176		T23	7435		T24	2
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5908792	1			T21	354		T22	1		T23	27395
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4200519	1			T21	14		T23	16479		T24	43
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1573441	1			T21	298		T23	7479		T24	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2066587	1			T21	398		T23	11405		T24	67
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	418372	1			T21	15		T23	833		T24	17
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1561266	1			T21	255		T23	7356		T24	2
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5898231	1			T21	381		T22	1		T23	27197
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4204719	1			T21	12		T23	16393		T24	16
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1577829	1			T21	294		T23	7017		T24	6
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2059757	1			T21	324		T23	12023		T24	134
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	418482	1			T21	11		T23	907		T24	48
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1569959	1			T21	312		T23	7410		T24	4
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5918929	1			T21	318		T22	1		T23	28084
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4191177	1			T21	10		T23	16469		T24	59
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1578698	1			T21	317		T23	7502		T24	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2062453	1			T21	393		T23	10958		T24	26
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	416446	1			T21	16		T23	856		T24	4
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1561274	1			T21	280		T23	7078		T24	2
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5905248	1			T21	358		T22	1		T23	28271
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4209690	1			T21	17		T23	16594		T24	27
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1577980	1			T21	306		T23	7527		T24	7
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2059613	1			T21	339		T23	10807		T24	77
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	418311	1			T21	5		T23	800		T24	38
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1558135	1			T21	309		T23	6948		T24	4
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5898997	1			T21	322		T22	1		T23	28037
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4210489	1			T21	11		T23	16165		T24	32
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1577794	1			T21	247		T23	7319		T24	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2058893	1			T21	497		T23	11343		T24	80
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	417489	1			T21	16		T23	906		T24	33
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1565315	1			T21	241		T23	7177		T1	397
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5908822	1			T21	329		T22	1		T23	27645
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4194391	1			T21	11		T23	16688		T24	35
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1574012	1			T21	293		T23	7438		T24	5
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2071316	1			T21	421		T23	10819		T24	55
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	417118	1			T21	17		T23	877		T24	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1563318	1			T21	263		T23	7480		T1	416
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5899636	1			T21	277		T22	1		T23	27043
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4209134	1			T21	11		T23	16695		T24	36
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1571519	1			T21	232		T23	7334		T24	9
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2066724	1			T21	414		T23	11654		T24	90
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	418420	1			T21	15		T23	942		T24	25
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1563544	1			T21	385		T23	7279		T24	4
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5912720	1			T21	396		T22	1		T23	27069
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4199287	1			T21	15		T23	16539		T24	37
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1576148	1			T21	307		T23	7072		T24	14
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2062398	1			T21	400		T23	11730		T24	60
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	418683	1			T21	15		T23	913		T24	20
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1559741	1			T21	201		T23	7624		T24	3
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5902793	1			T21	314		T22	1		T23	26870
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4205608	1			T21	11		T23	16591		T24	12
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1582447	1			T21	347		T23	7473		T24	9
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2055244	1			T21	288		T23	11450		T24	113
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	416993	1			T21	10		T23	889		T24	49
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1565892	1			T21	364		T23	7674		T24	15
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5904371	1			T21	345		T22	1		T23	27069
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4200071	1			T21	14		T23	16642		T24	41
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1571668	1			T21	208		T23	7372		T24	6
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2069231	1			T21	457		T23	11539		T24	77
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	419056	1			T21	10		T23	976		T24	29
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1564580	1			T21	300		T23	7349		T24	2
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5897962	1			T21	366		T22	1		T23	27395
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4203970	1			T21	21		T23	16568		T24	37
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1579460	1			T21	368		T23	7312		T24	9
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2066599	1			T21	304		T23	11611		T24	44
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	416614	1			T21	8		T23	922		T24	26
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1564372	1			T21	267		T23	7139		T24	10
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5902358	1			T21	319		T22	1		T23	27167
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4215217	1			T21	16		T23	16468		T24	18
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1569046	1			T21	322		T23	7243		T24	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2067140	1			T21	345		T23	11578		T24	113
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	420254	1			T21	11		T23	949		T24	37
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1554962	1			T21	321		T23	7542		T24	4
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5909606	1			T21	319		T22	1		T23	27560
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4203824	1			T23	16485		T24	16		T25	753
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1570518	1			T21	307		T23	7243		T24	6
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2070612	1			T21	329		T23	11447		T24	142
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	419803	1			T21	17		T23	898		T24	38
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1554614	1			T21	362		T23	7314		T24	4
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5917123	1			T21	360		T22	1		T23	27635
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4201293	1			T21	6		T23	16676		T24	17
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1569966	1			T21	288		T23	7242		T24	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2063115	1			T21	411		T23	11278		T24	123
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	417680	1			T21	14		T23	880		T24	59
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1559800	1			T21	255		T23	7236		T24	8
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5909485	1			T21	398		T22	1		T23	27298
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4207175	1			T21	21		T23	16395		T24	58
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1574041	1			T21	292		T23	7222		T24	15
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2066207	1			T21	402		T23	11796		T24	10
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	421152	1			T21	8		T23	975		T24	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1550917	1			T21	213		T23	7261		T24	4
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5894689	1			T21	410		T22	1		T23	27124
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4218437	1			T21	11		T23	16786		T24	28
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1570229	1			T21	197		T23	7234		T24	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2074989	1			T21	411		T23	11360		T24	94
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	418998	1			T21	13		T23	911		T24	22
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1551635	1			T21	292		T23	7532		T24	8
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5907776	1			T21	502		T22	1		T23	27406
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4208744	1			T21	15		T23	16554		T24	7
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1573828	1			T21	313		T23	7442		T24	2
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2065712	1			T21	252		T23	11515		T24	168
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	415729	1			T21	7		T23	900		T24	44
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1557188	1			T21	245		T23	7130		T24	6
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5908638	1			T21	383		T22	1		T23	27596
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4208147	1			T21	13		T23	16580		T24	36
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1569333	1			T21	221		T23	7458		T24	13
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2067040	1			T21	357		T23	11184		T24	81
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	417098	1			T21	14		T23	957		T24	21
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1558721	1			T21	346		T23	7172		T1	460
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5918798	1			T21	468		T22	1		T23	27192
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4199580	1			T21	16		T23	16694		T24	35
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1567883	1			T21	213		T23	7496		T24	9
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2069408	1			T21	356		T23	11402		T24	70
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	417742	1			T21	7		T23	900		T24	31
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1555566	1			T21	274		T23	7263		T24	12
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5912160	1			T21	379		T22	1		T23	26951
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4204966	1			T21	9		T23	16612		T24	36
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1570112	1			T21	329		T23	7355		T24	10
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2065378	1			T21	360		T23	11823		T24	66
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	415644	1			T21	11		T23	890		T24	20
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1560717	1			T21	246		T23	7316		T1	354
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5912916	1			T21	368		T22	1		T23	27313
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4201296	1			T21	3		T23	16502		T24	46
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1571956	1			T21	324		T23	7532		T24	11
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2064480	1			T21	382		T23	11489		T24	76
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	420267	1			T21	16		T23	931		T24	23
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1558062	1			T21	241		T23	7180		T24	4
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5903698	1			T21	367		T22	1		T23	27793
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4210212	1			T21	9		T23	16489		T24	45
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1572108	1			T21	293		T23	7232		T24	26
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2067787	1			T21	377		T23	11184		T24	19
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	418640	1			T21	16		T23	807		T24	7
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1556532	1			T21	272		T23	7442		T24	2
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5897880	1			T21	380		T22	1		T23	27125
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4213941	1			T21	10		T23	16680		T24	42
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1573678	1			T21	341		T23	7668		T24	14
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2068638	1			T21	345		T23	11335		T24	74
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	417976	1			T21	12		T23	925		T24	17
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1556864	1			T21	246		T23	7214		T24	6
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5901728	1			T21	355		T22	1		T23	27616
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4214226	1			T21	15		T23	16605		T24	40
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1569224	1			T21	368		T23	7331		T24	9
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2068478	1			T21	301		T23	11027		T24	78
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	417930	1			T21	6		T23	768		T24	21
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1557391	1			T21	289		T23	7600		T24	12
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5909529	1			T21	366		T22	1		T23	27423
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4208587	1			T21	10		T23	16752		T24	44
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1572292	1			T21	203		T23	7754		T24	13
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2066827	1			T21	455		T23	10844		T24	50
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	417796	1			T21	13		T23	803		T24	28
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1553946	1			T21	287		T23	7371		T24	4
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5908162	1			T21	391		T22	1		T23	26672
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4206707	1			T21	14		T23	16478		T24	34
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1573907	1			T21	397		T23	7226		T24	11
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2065549	1			T21	246		T23	11948		T24	59
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	416989	1			T21	11		T23	953		T24	26
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1557663	1			T21	275		T23	7670		T24	2
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5900034	1			T21	359		T22	1		T23	27124
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4211418	1			T21	8		T23	16663		T24	39
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1573127	1			T21	207		T23	7293		T24	14
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2066364	1			T21	426		T23	11467		T24	60
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	415807	1			T21	14		T23	882		T24	11
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1562227	1			T21	320		T23	7518		T24	6

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal