Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[1]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[2]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[3]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[4]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[5]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[6]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[7]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[8]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[9]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[10]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[11]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[12]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[13]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[14]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[15]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[16]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[17]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[18]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[19]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[20]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[21]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[22]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[23]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[24]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[25]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[26]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[27]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[28]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[29]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[30]	15728977	1			T21	1334		T22	1		T23	70947
bins_for_gpio_bits[31]	15728977	1			T21	1334		T22	1		T23	70947

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305442001

1

T21

32747

T22

32

T23

147684

auto[1]

197885263

1

T21

9941

T23

793460

T24

2087

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305433669

1

T21

32738

T22

32

T23

147662

auto[1]

197893595

1

T21

9950

T23

793678

T24

2087

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9260831	1			T21	901		T22	1		T23	44892
bins_for_gpio_bits[0]	auto[0]	auto[1]	280936	1			T21	50		T23	1373		T1	56
bins_for_gpio_bits[0]	auto[1]	auto[0]	281190	1			T21	50		T23	1380		T1	56
bins_for_gpio_bits[0]	auto[1]	auto[1]	5906020	1			T21	333		T23	23302		T24	56
bins_for_gpio_bits[1]	auto[0]	auto[0]	9258643	1			T21	900		T22	1		T23	44770
bins_for_gpio_bits[1]	auto[0]	auto[1]	279673	1			T21	55		T23	1431		T24	3
bins_for_gpio_bits[1]	auto[1]	auto[0]	279943	1			T21	56		T23	1436		T24	3
bins_for_gpio_bits[1]	auto[1]	auto[1]	5910718	1			T21	323		T23	23310		T24	63
bins_for_gpio_bits[2]	auto[0]	auto[0]	9270717	1			T21	918		T22	1		T23	44550
bins_for_gpio_bits[2]	auto[0]	auto[1]	280021	1			T21	53		T23	1419		T24	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	280300	1			T21	53		T23	1422		T24	4
bins_for_gpio_bits[2]	auto[1]	auto[1]	5897939	1			T21	310		T23	23556		T24	68
bins_for_gpio_bits[3]	auto[0]	auto[0]	9252708	1			T21	984		T22	1		T23	45065
bins_for_gpio_bits[3]	auto[0]	auto[1]	280377	1			T21	43		T23	1363		T24	3
bins_for_gpio_bits[3]	auto[1]	auto[0]	280612	1			T21	43		T23	1370		T24	3
bins_for_gpio_bits[3]	auto[1]	auto[1]	5915280	1			T21	264		T23	23149		T24	71
bins_for_gpio_bits[4]	auto[0]	auto[0]	9266421	1			T21	1106		T22	1		T23	44616
bins_for_gpio_bits[4]	auto[0]	auto[1]	280512	1			T21	30		T23	1431		T24	1
bins_for_gpio_bits[4]	auto[1]	auto[0]	280772	1			T21	30		T23	1441		T24	1
bins_for_gpio_bits[4]	auto[1]	auto[1]	5901272	1			T21	168		T23	23459		T24	67
bins_for_gpio_bits[5]	auto[0]	auto[0]	9268844	1			T21	1006		T22	1		T23	44865
bins_for_gpio_bits[5]	auto[0]	auto[1]	279735	1			T21	44		T23	1410		T24	1
bins_for_gpio_bits[5]	auto[1]	auto[0]	279976	1			T21	44		T23	1414		T24	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	5900422	1			T21	240		T23	23258		T24	61
bins_for_gpio_bits[6]	auto[0]	auto[0]	9255470	1			T21	954		T22	1		T23	44806
bins_for_gpio_bits[6]	auto[0]	auto[1]	280098	1			T21	44		T23	1424		T24	2
bins_for_gpio_bits[6]	auto[1]	auto[0]	280347	1			T21	45		T23	1431		T24	2
bins_for_gpio_bits[6]	auto[1]	auto[1]	5913062	1			T21	291		T23	23286		T24	66
bins_for_gpio_bits[7]	auto[0]	auto[0]	9280231	1			T21	987		T22	1		T23	45165
bins_for_gpio_bits[7]	auto[0]	auto[1]	279580	1			T21	41		T23	1376		T24	1
bins_for_gpio_bits[7]	auto[1]	auto[0]	279849	1			T21	41		T23	1379		T24	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	5889317	1			T21	265		T23	23027		T24	64
bins_for_gpio_bits[8]	auto[0]	auto[0]	9262784	1			T21	968		T22	1		T23	45251
bins_for_gpio_bits[8]	auto[0]	auto[1]	279804	1			T21	35		T23	1349		T24	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	280057	1			T21	35		T23	1354		T24	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	5906332	1			T21	296		T23	22993		T24	67
bins_for_gpio_bits[9]	auto[0]	auto[0]	9255858	1			T21	1028		T22	1		T23	45313
bins_for_gpio_bits[9]	auto[0]	auto[1]	279545	1			T21	38		T23	1376		T1	63
bins_for_gpio_bits[9]	auto[1]	auto[0]	279826	1			T21	38		T23	1386		T1	63
bins_for_gpio_bits[9]	auto[1]	auto[1]	5913748	1			T21	230		T23	22872		T24	65
bins_for_gpio_bits[10]	auto[0]	auto[0]	9274063	1			T21	993		T22	1		T23	44479
bins_for_gpio_bits[10]	auto[0]	auto[1]	279819	1			T21	49		T23	1418		T1	53
bins_for_gpio_bits[10]	auto[1]	auto[0]	280087	1			T21	50		T23	1423		T1	53
bins_for_gpio_bits[10]	auto[1]	auto[1]	5895008	1			T21	242		T23	23627		T24	46
bins_for_gpio_bits[11]	auto[0]	auto[0]	9257731	1			T21	873		T22	1		T23	44664
bins_for_gpio_bits[11]	auto[0]	auto[1]	279888	1			T21	49		T23	1361		T24	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	280148	1			T21	50		T23	1367		T24	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	5911210	1			T21	362		T23	23555		T24	64
bins_for_gpio_bits[12]	auto[0]	auto[0]	9271325	1			T21	1064		T22	1		T23	44428
bins_for_gpio_bits[12]	auto[0]	auto[1]	279705	1			T21	39		T23	1437		T24	1
bins_for_gpio_bits[12]	auto[1]	auto[0]	279941	1			T21	39		T23	1443		T24	1
bins_for_gpio_bits[12]	auto[1]	auto[1]	5898006	1			T21	192		T23	23639		T24	59
bins_for_gpio_bits[13]	auto[0]	auto[0]	9260174	1			T21	900		T22	1		T23	44360
bins_for_gpio_bits[13]	auto[0]	auto[1]	280048	1			T21	49		T23	1426		T24	3
bins_for_gpio_bits[13]	auto[1]	auto[0]	280310	1			T21	49		T23	1433		T24	3
bins_for_gpio_bits[13]	auto[1]	auto[1]	5908445	1			T21	336		T23	23728		T24	73
bins_for_gpio_bits[14]	auto[0]	auto[0]	9264661	1			T21	965		T22	1		T23	44603
bins_for_gpio_bits[14]	auto[0]	auto[1]	280345	1			T21	45		T23	1370		T24	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	280609	1			T21	45		T23	1377		T24	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	5903362	1			T21	279		T23	23597		T24	71
bins_for_gpio_bits[15]	auto[0]	auto[0]	9262926	1			T21	990		T22	1		T23	44921
bins_for_gpio_bits[15]	auto[0]	auto[1]	280797	1			T21	48		T23	1391		T24	3
bins_for_gpio_bits[15]	auto[1]	auto[0]	281095	1			T21	48		T23	1397		T24	3
bins_for_gpio_bits[15]	auto[1]	auto[1]	5904159	1			T21	248		T23	23238		T24	70
bins_for_gpio_bits[16]	auto[0]	auto[0]	9257937	1			T21	942		T22	1		T23	44491
bins_for_gpio_bits[16]	auto[0]	auto[1]	280355	1			T21	44		T23	1485		T24	2
bins_for_gpio_bits[16]	auto[1]	auto[0]	280607	1			T21	44		T23	1497		T24	2
bins_for_gpio_bits[16]	auto[1]	auto[1]	5910078	1			T21	304		T23	23474		T24	57
bins_for_gpio_bits[17]	auto[0]	auto[0]	9270838	1			T21	911		T22	1		T23	44854
bins_for_gpio_bits[17]	auto[0]	auto[1]	279605	1			T21	44		T23	1388		T24	1
bins_for_gpio_bits[17]	auto[1]	auto[0]	279898	1			T21	44		T23	1396		T24	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	5898636	1			T21	335		T23	23309		T24	57
bins_for_gpio_bits[18]	auto[0]	auto[0]	9269802	1			T21	1019		T22	1		T23	44788
bins_for_gpio_bits[18]	auto[0]	auto[1]	280141	1			T21	40		T23	1359		T24	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	280402	1			T21	40		T23	1367		T24	4
bins_for_gpio_bits[18]	auto[1]	auto[1]	5898632	1			T21	235		T23	23433		T24	80
bins_for_gpio_bits[19]	auto[0]	auto[0]	9270319	1			T21	1055		T22	1		T23	44927
bins_for_gpio_bits[19]	auto[0]	auto[1]	279188	1			T21	37		T23	1383		T24	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	279414	1			T21	37		T23	1389		T24	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	5900056	1			T21	205		T23	23248		T24	62
bins_for_gpio_bits[20]	auto[0]	auto[0]	9259838	1			T21	980		T22	1		T23	44270
bins_for_gpio_bits[20]	auto[0]	auto[1]	279801	1			T21	38		T23	1441		T24	4
bins_for_gpio_bits[20]	auto[1]	auto[0]	280069	1			T21	38		T23	1448		T24	4
bins_for_gpio_bits[20]	auto[1]	auto[1]	5909269	1			T21	278		T23	23788		T24	54
bins_for_gpio_bits[21]	auto[0]	auto[0]	9266759	1			T21	1032		T22	1		T23	44955
bins_for_gpio_bits[21]	auto[0]	auto[1]	280265	1			T21	35		T23	1399		T24	3
bins_for_gpio_bits[21]	auto[1]	auto[0]	280557	1			T21	35		T23	1408		T24	3
bins_for_gpio_bits[21]	auto[1]	auto[1]	5901396	1			T21	232		T23	23185		T24	54
bins_for_gpio_bits[22]	auto[0]	auto[0]	9264643	1			T21	916		T22	1		T23	44873
bins_for_gpio_bits[22]	auto[0]	auto[1]	280112	1			T21	44		T23	1358		T1	56
bins_for_gpio_bits[22]	auto[1]	auto[0]	280368	1			T21	45		T23	1365		T1	57
bins_for_gpio_bits[22]	auto[1]	auto[1]	5903854	1			T21	329		T23	23351		T24	57
bins_for_gpio_bits[23]	auto[0]	auto[0]	9275674	1			T21	1000		T22	1		T23	44687
bins_for_gpio_bits[23]	auto[0]	auto[1]	280142	1			T21	37		T23	1394		T24	3
bins_for_gpio_bits[23]	auto[1]	auto[0]	280415	1			T21	37		T23	1403		T24	3
bins_for_gpio_bits[23]	auto[1]	auto[1]	5892746	1			T21	260		T23	23463		T24	75
bins_for_gpio_bits[24]	auto[0]	auto[0]	9266961	1			T21	1028		T22	1		T23	44702
bins_for_gpio_bits[24]	auto[0]	auto[1]	280451	1			T21	39		T23	1423		T1	49
bins_for_gpio_bits[24]	auto[1]	auto[0]	280689	1			T21	40		T23	1427		T1	49
bins_for_gpio_bits[24]	auto[1]	auto[1]	5900876	1			T21	227		T23	23395		T24	56
bins_for_gpio_bits[25]	auto[0]	auto[0]	9269277	1			T21	1034		T22	1		T23	44909
bins_for_gpio_bits[25]	auto[0]	auto[1]	279819	1			T21	39		T23	1418		T24	1
bins_for_gpio_bits[25]	auto[1]	auto[0]	280075	1			T21	40		T23	1425		T24	1
bins_for_gpio_bits[25]	auto[1]	auto[1]	5899806	1			T21	221		T23	23195		T24	72
bins_for_gpio_bits[26]	auto[0]	auto[0]	9263402	1			T21	999		T22	1		T23	44793
bins_for_gpio_bits[26]	auto[0]	auto[1]	279957	1			T21	37		T23	1408		T24	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	280191	1			T21	38		T23	1416		T24	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	5905427	1			T21	260		T23	23330		T24	53
bins_for_gpio_bits[27]	auto[0]	auto[0]	9259071	1			T21	1027		T22	1		T23	44688
bins_for_gpio_bits[27]	auto[0]	auto[1]	280830	1			T21	39		T23	1433		T24	2
bins_for_gpio_bits[27]	auto[1]	auto[0]	281125	1			T21	39		T23	1440		T24	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	5907951	1			T21	229		T23	23386		T24	63
bins_for_gpio_bits[28]	auto[0]	auto[0]	9258742	1			T21	981		T22	1		T23	44507
bins_for_gpio_bits[28]	auto[0]	auto[1]	280442	1			T21	43		T23	1457		T24	4
bins_for_gpio_bits[28]	auto[1]	auto[0]	280688	1			T21	43		T23	1467		T24	4
bins_for_gpio_bits[28]	auto[1]	auto[1]	5909105	1			T21	267		T23	23516		T24	69
bins_for_gpio_bits[29]	auto[0]	auto[0]	9268217	1			T21	991		T22	1		T23	44611
bins_for_gpio_bits[29]	auto[0]	auto[1]	280187	1			T21	32		T23	1403		T24	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	280431	1			T21	33		T23	1410		T24	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	5900142	1			T21	278		T23	23523		T24	74
bins_for_gpio_bits[30]	auto[0]	auto[0]	9266967	1			T21	994		T22	1		T23	44381
bins_for_gpio_bits[30]	auto[0]	auto[1]	280374	1			T21	40		T23	1460		T24	1
bins_for_gpio_bits[30]	auto[1]	auto[0]	280651	1			T21	40		T23	1465		T24	1
bins_for_gpio_bits[30]	auto[1]	auto[1]	5900985	1			T21	260		T23	23641		T24	61
bins_for_gpio_bits[31]	auto[0]	auto[0]	9258569	1			T21	946		T22	1		T23	44451
bins_for_gpio_bits[31]	auto[0]	auto[1]	280714	1			T21	46		T23	1427		T24	1
bins_for_gpio_bits[31]	auto[1]	auto[0]	280956	1			T21	46		T23	1433		T24	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	5908738	1			T21	296		T23	23636		T24	55