Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9076002 |
1 |
|
|
T21 |
660 |
|
T22 |
1 |
|
T23 |
41714 |
| auto[1] |
6980047 |
1 |
|
|
T21 |
752 |
|
T23 |
29467 |
|
T25 |
1036 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15161299 |
1 |
|
|
T21 |
1384 |
|
T22 |
1 |
|
T23 |
67031 |
| auto[1] |
894750 |
1 |
|
|
T21 |
28 |
|
T23 |
4150 |
|
T25 |
230 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9106009 |
1 |
|
|
T21 |
779 |
|
T22 |
1 |
|
T23 |
40152 |
| auto[1] |
6950040 |
1 |
|
|
T21 |
633 |
|
T23 |
31029 |
|
T25 |
1214 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3022446 |
1 |
|
|
T21 |
285 |
|
T23 |
13896 |
|
T25 |
484 |
| auto[1] |
auto[0] |
auto[1] |
446334 |
1 |
|
|
T21 |
17 |
|
T23 |
2122 |
|
T25 |
112 |
| auto[1] |
auto[1] |
auto[0] |
3032844 |
1 |
|
|
T21 |
320 |
|
T23 |
12983 |
|
T25 |
500 |
| auto[1] |
auto[1] |
auto[1] |
448416 |
1 |
|
|
T21 |
11 |
|
T23 |
2028 |
|
T25 |
118 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9114499 |
1 |
|
|
T21 |
529 |
|
T22 |
1 |
|
T23 |
41606 |
| auto[1] |
6941550 |
1 |
|
|
T21 |
883 |
|
T23 |
29575 |
|
T25 |
911 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15161224 |
1 |
|
|
T21 |
1388 |
|
T22 |
1 |
|
T23 |
67065 |
| auto[1] |
894825 |
1 |
|
|
T21 |
24 |
|
T23 |
4116 |
|
T25 |
199 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9109103 |
1 |
|
|
T21 |
844 |
|
T22 |
1 |
|
T23 |
40785 |
| auto[1] |
6946946 |
1 |
|
|
T21 |
568 |
|
T23 |
30396 |
|
T25 |
1038 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3025102 |
1 |
|
|
T21 |
187 |
|
T23 |
13163 |
|
T25 |
414 |
| auto[1] |
auto[0] |
auto[1] |
446310 |
1 |
|
|
T21 |
6 |
|
T23 |
2043 |
|
T25 |
98 |
| auto[1] |
auto[1] |
auto[0] |
3027019 |
1 |
|
|
T21 |
357 |
|
T23 |
13117 |
|
T25 |
425 |
| auto[1] |
auto[1] |
auto[1] |
448515 |
1 |
|
|
T21 |
18 |
|
T23 |
2073 |
|
T25 |
101 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9107257 |
1 |
|
|
T21 |
773 |
|
T22 |
1 |
|
T23 |
40458 |
| auto[1] |
6948792 |
1 |
|
|
T21 |
639 |
|
T23 |
30723 |
|
T25 |
939 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15158144 |
1 |
|
|
T21 |
1380 |
|
T22 |
1 |
|
T23 |
67050 |
| auto[1] |
897905 |
1 |
|
|
T21 |
32 |
|
T23 |
4131 |
|
T25 |
181 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9088437 |
1 |
|
|
T21 |
631 |
|
T22 |
1 |
|
T23 |
40417 |
| auto[1] |
6967612 |
1 |
|
|
T21 |
781 |
|
T23 |
30764 |
|
T25 |
963 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3030025 |
1 |
|
|
T21 |
308 |
|
T23 |
13569 |
|
T25 |
431 |
| auto[1] |
auto[0] |
auto[1] |
448235 |
1 |
|
|
T21 |
11 |
|
T23 |
2150 |
|
T25 |
98 |
| auto[1] |
auto[1] |
auto[0] |
3039682 |
1 |
|
|
T21 |
441 |
|
T23 |
13064 |
|
T25 |
351 |
| auto[1] |
auto[1] |
auto[1] |
449670 |
1 |
|
|
T21 |
21 |
|
T23 |
1981 |
|
T25 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9095796 |
1 |
|
|
T21 |
950 |
|
T22 |
1 |
|
T23 |
41356 |
| auto[1] |
6960253 |
1 |
|
|
T21 |
462 |
|
T23 |
29825 |
|
T25 |
1226 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15154217 |
1 |
|
|
T21 |
1385 |
|
T22 |
1 |
|
T23 |
67301 |
| auto[1] |
901832 |
1 |
|
|
T21 |
27 |
|
T23 |
3880 |
|
T25 |
174 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9071368 |
1 |
|
|
T21 |
838 |
|
T22 |
1 |
|
T23 |
41581 |
| auto[1] |
6984681 |
1 |
|
|
T21 |
574 |
|
T23 |
29600 |
|
T25 |
906 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3037035 |
1 |
|
|
T21 |
416 |
|
T23 |
12821 |
|
T25 |
296 |
| auto[1] |
auto[0] |
auto[1] |
451538 |
1 |
|
|
T21 |
19 |
|
T23 |
1883 |
|
T25 |
71 |
| auto[1] |
auto[1] |
auto[0] |
3045814 |
1 |
|
|
T21 |
131 |
|
T23 |
12899 |
|
T25 |
436 |
| auto[1] |
auto[1] |
auto[1] |
450294 |
1 |
|
|
T21 |
8 |
|
T23 |
1997 |
|
T25 |
103 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9115370 |
1 |
|
|
T21 |
759 |
|
T22 |
1 |
|
T23 |
42686 |
| auto[1] |
6940679 |
1 |
|
|
T21 |
653 |
|
T23 |
28495 |
|
T25 |
996 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15156293 |
1 |
|
|
T21 |
1383 |
|
T22 |
1 |
|
T23 |
67128 |
| auto[1] |
899756 |
1 |
|
|
T21 |
29 |
|
T23 |
4053 |
|
T25 |
208 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9076150 |
1 |
|
|
T21 |
703 |
|
T22 |
1 |
|
T23 |
41288 |
| auto[1] |
6979899 |
1 |
|
|
T21 |
709 |
|
T23 |
29893 |
|
T25 |
998 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3057278 |
1 |
|
|
T21 |
348 |
|
T23 |
13501 |
|
T25 |
316 |
| auto[1] |
auto[0] |
auto[1] |
452510 |
1 |
|
|
T21 |
12 |
|
T23 |
2157 |
|
T25 |
78 |
| auto[1] |
auto[1] |
auto[0] |
3022865 |
1 |
|
|
T21 |
332 |
|
T23 |
12339 |
|
T25 |
474 |
| auto[1] |
auto[1] |
auto[1] |
447246 |
1 |
|
|
T21 |
17 |
|
T23 |
1896 |
|
T25 |
130 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9114973 |
1 |
|
|
T21 |
747 |
|
T22 |
1 |
|
T23 |
40834 |
| auto[1] |
6941076 |
1 |
|
|
T21 |
665 |
|
T23 |
30347 |
|
T25 |
1142 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15161052 |
1 |
|
|
T21 |
1378 |
|
T22 |
1 |
|
T23 |
67454 |
| auto[1] |
894997 |
1 |
|
|
T21 |
34 |
|
T23 |
3727 |
|
T25 |
186 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9106789 |
1 |
|
|
T21 |
603 |
|
T22 |
1 |
|
T23 |
42842 |
| auto[1] |
6949260 |
1 |
|
|
T21 |
809 |
|
T23 |
28339 |
|
T25 |
1000 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3040565 |
1 |
|
|
T21 |
408 |
|
T23 |
12319 |
|
T25 |
352 |
| auto[1] |
auto[0] |
auto[1] |
449457 |
1 |
|
|
T21 |
15 |
|
T23 |
1904 |
|
T25 |
72 |
| auto[1] |
auto[1] |
auto[0] |
3013698 |
1 |
|
|
T21 |
367 |
|
T23 |
12293 |
|
T25 |
462 |
| auto[1] |
auto[1] |
auto[1] |
445540 |
1 |
|
|
T21 |
19 |
|
T23 |
1823 |
|
T25 |
114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9048483 |
1 |
|
|
T21 |
690 |
|
T22 |
1 |
|
T23 |
41541 |
| auto[1] |
7007566 |
1 |
|
|
T21 |
722 |
|
T23 |
29640 |
|
T25 |
865 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15162549 |
1 |
|
|
T21 |
1380 |
|
T22 |
1 |
|
T23 |
67516 |
| auto[1] |
893500 |
1 |
|
|
T21 |
32 |
|
T23 |
3665 |
|
T25 |
172 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9106942 |
1 |
|
|
T21 |
548 |
|
T22 |
1 |
|
T23 |
42452 |
| auto[1] |
6949107 |
1 |
|
|
T21 |
864 |
|
T23 |
28729 |
|
T25 |
917 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3011341 |
1 |
|
|
T21 |
412 |
|
T23 |
12899 |
|
T25 |
441 |
| auto[1] |
auto[0] |
auto[1] |
444391 |
1 |
|
|
T21 |
16 |
|
T23 |
1885 |
|
T25 |
103 |
| auto[1] |
auto[1] |
auto[0] |
3044266 |
1 |
|
|
T21 |
420 |
|
T23 |
12165 |
|
T25 |
304 |
| auto[1] |
auto[1] |
auto[1] |
449109 |
1 |
|
|
T21 |
16 |
|
T23 |
1780 |
|
T25 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9051435 |
1 |
|
|
T21 |
648 |
|
T22 |
1 |
|
T23 |
42270 |
| auto[1] |
7004614 |
1 |
|
|
T21 |
764 |
|
T23 |
28911 |
|
T25 |
1216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15155065 |
1 |
|
|
T21 |
1393 |
|
T22 |
1 |
|
T23 |
67194 |
| auto[1] |
900984 |
1 |
|
|
T21 |
19 |
|
T23 |
3987 |
|
T25 |
153 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9073952 |
1 |
|
|
T21 |
771 |
|
T22 |
1 |
|
T23 |
41609 |
| auto[1] |
6982097 |
1 |
|
|
T21 |
641 |
|
T23 |
29572 |
|
T25 |
807 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3037566 |
1 |
|
|
T21 |
313 |
|
T23 |
13511 |
|
T25 |
339 |
| auto[1] |
auto[0] |
auto[1] |
452049 |
1 |
|
|
T21 |
8 |
|
T23 |
2131 |
|
T25 |
78 |
| auto[1] |
auto[1] |
auto[0] |
3043547 |
1 |
|
|
T21 |
309 |
|
T23 |
12074 |
|
T25 |
315 |
| auto[1] |
auto[1] |
auto[1] |
448935 |
1 |
|
|
T21 |
11 |
|
T23 |
1856 |
|
T25 |
75 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9072463 |
1 |
|
|
T21 |
795 |
|
T22 |
1 |
|
T23 |
41102 |
| auto[1] |
6983586 |
1 |
|
|
T21 |
617 |
|
T23 |
30079 |
|
T25 |
897 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15160949 |
1 |
|
|
T21 |
1385 |
|
T22 |
1 |
|
T23 |
67398 |
| auto[1] |
895100 |
1 |
|
|
T21 |
27 |
|
T23 |
3783 |
|
T25 |
155 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9106775 |
1 |
|
|
T21 |
777 |
|
T22 |
1 |
|
T23 |
42742 |
| auto[1] |
6949274 |
1 |
|
|
T21 |
635 |
|
T23 |
28439 |
|
T25 |
796 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3028175 |
1 |
|
|
T21 |
312 |
|
T23 |
12103 |
|
T25 |
280 |
| auto[1] |
auto[0] |
auto[1] |
448106 |
1 |
|
|
T21 |
13 |
|
T23 |
1736 |
|
T25 |
70 |
| auto[1] |
auto[1] |
auto[0] |
3025999 |
1 |
|
|
T21 |
296 |
|
T23 |
12553 |
|
T25 |
361 |
| auto[1] |
auto[1] |
auto[1] |
446994 |
1 |
|
|
T21 |
14 |
|
T23 |
2047 |
|
T25 |
85 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9093984 |
1 |
|
|
T21 |
674 |
|
T22 |
1 |
|
T23 |
41139 |
| auto[1] |
6962065 |
1 |
|
|
T21 |
738 |
|
T23 |
30042 |
|
T25 |
1027 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15155557 |
1 |
|
|
T21 |
1375 |
|
T22 |
1 |
|
T23 |
67268 |
| auto[1] |
900492 |
1 |
|
|
T21 |
37 |
|
T23 |
3913 |
|
T25 |
236 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9075061 |
1 |
|
|
T21 |
663 |
|
T22 |
1 |
|
T23 |
42036 |
| auto[1] |
6980988 |
1 |
|
|
T21 |
749 |
|
T23 |
29145 |
|
T25 |
1197 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3046833 |
1 |
|
|
T21 |
440 |
|
T23 |
12507 |
|
T25 |
495 |
| auto[1] |
auto[0] |
auto[1] |
451734 |
1 |
|
|
T21 |
24 |
|
T23 |
1938 |
|
T25 |
134 |
| auto[1] |
auto[1] |
auto[0] |
3033663 |
1 |
|
|
T21 |
272 |
|
T23 |
12725 |
|
T25 |
466 |
| auto[1] |
auto[1] |
auto[1] |
448758 |
1 |
|
|
T21 |
13 |
|
T23 |
1975 |
|
T25 |
102 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9137978 |
1 |
|
|
T21 |
736 |
|
T22 |
1 |
|
T23 |
42630 |
| auto[1] |
6918071 |
1 |
|
|
T21 |
676 |
|
T23 |
28551 |
|
T25 |
1031 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15164060 |
1 |
|
|
T21 |
1389 |
|
T22 |
1 |
|
T23 |
67151 |
| auto[1] |
891989 |
1 |
|
|
T21 |
23 |
|
T23 |
4030 |
|
T25 |
132 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9124705 |
1 |
|
|
T21 |
790 |
|
T22 |
1 |
|
T23 |
41506 |
| auto[1] |
6931344 |
1 |
|
|
T21 |
622 |
|
T23 |
29675 |
|
T25 |
667 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3032490 |
1 |
|
|
T21 |
246 |
|
T23 |
13913 |
|
T25 |
212 |
| auto[1] |
auto[0] |
auto[1] |
448242 |
1 |
|
|
T21 |
12 |
|
T23 |
2175 |
|
T25 |
59 |
| auto[1] |
auto[1] |
auto[0] |
3006865 |
1 |
|
|
T21 |
353 |
|
T23 |
11732 |
|
T25 |
323 |
| auto[1] |
auto[1] |
auto[1] |
443747 |
1 |
|
|
T21 |
11 |
|
T23 |
1855 |
|
T25 |
73 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9093632 |
1 |
|
|
T21 |
703 |
|
T22 |
1 |
|
T23 |
40971 |
| auto[1] |
6962417 |
1 |
|
|
T21 |
709 |
|
T23 |
30210 |
|
T25 |
1094 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15157122 |
1 |
|
|
T21 |
1380 |
|
T22 |
1 |
|
T23 |
67255 |
| auto[1] |
898927 |
1 |
|
|
T21 |
32 |
|
T23 |
3926 |
|
T25 |
170 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9068420 |
1 |
|
|
T21 |
633 |
|
T22 |
1 |
|
T23 |
41910 |
| auto[1] |
6987629 |
1 |
|
|
T21 |
779 |
|
T23 |
29271 |
|
T25 |
878 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3054705 |
1 |
|
|
T21 |
398 |
|
T23 |
12822 |
|
T25 |
314 |
| auto[1] |
auto[0] |
auto[1] |
451968 |
1 |
|
|
T21 |
16 |
|
T23 |
1998 |
|
T25 |
70 |
| auto[1] |
auto[1] |
auto[0] |
3033997 |
1 |
|
|
T21 |
349 |
|
T23 |
12523 |
|
T25 |
394 |
| auto[1] |
auto[1] |
auto[1] |
446959 |
1 |
|
|
T21 |
16 |
|
T23 |
1928 |
|
T25 |
100 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9129948 |
1 |
|
|
T21 |
483 |
|
T22 |
1 |
|
T23 |
40104 |
| auto[1] |
6926101 |
1 |
|
|
T21 |
929 |
|
T23 |
31077 |
|
T25 |
1075 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15156827 |
1 |
|
|
T21 |
1383 |
|
T22 |
1 |
|
T23 |
66812 |
| auto[1] |
899222 |
1 |
|
|
T21 |
29 |
|
T23 |
4369 |
|
T25 |
215 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9081932 |
1 |
|
|
T21 |
774 |
|
T22 |
1 |
|
T23 |
39307 |
| auto[1] |
6974117 |
1 |
|
|
T21 |
638 |
|
T23 |
31874 |
|
T25 |
1134 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3064011 |
1 |
|
|
T21 |
217 |
|
T23 |
13271 |
|
T25 |
402 |
| auto[1] |
auto[0] |
auto[1] |
454217 |
1 |
|
|
T21 |
10 |
|
T23 |
2078 |
|
T25 |
91 |
| auto[1] |
auto[1] |
auto[0] |
3010884 |
1 |
|
|
T21 |
392 |
|
T23 |
14234 |
|
T25 |
517 |
| auto[1] |
auto[1] |
auto[1] |
445005 |
1 |
|
|
T21 |
19 |
|
T23 |
2291 |
|
T25 |
124 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9078967 |
1 |
|
|
T21 |
774 |
|
T22 |
1 |
|
T23 |
43091 |
| auto[1] |
6977082 |
1 |
|
|
T21 |
638 |
|
T23 |
28090 |
|
T25 |
991 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15156189 |
1 |
|
|
T21 |
1389 |
|
T22 |
1 |
|
T23 |
67184 |
| auto[1] |
899860 |
1 |
|
|
T21 |
23 |
|
T23 |
3997 |
|
T25 |
178 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9075269 |
1 |
|
|
T21 |
726 |
|
T22 |
1 |
|
T23 |
41054 |
| auto[1] |
6980780 |
1 |
|
|
T21 |
686 |
|
T23 |
30127 |
|
T25 |
927 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3054513 |
1 |
|
|
T21 |
363 |
|
T23 |
13933 |
|
T25 |
371 |
| auto[1] |
auto[0] |
auto[1] |
451438 |
1 |
|
|
T21 |
9 |
|
T23 |
2155 |
|
T25 |
95 |
| auto[1] |
auto[1] |
auto[0] |
3026407 |
1 |
|
|
T21 |
300 |
|
T23 |
12197 |
|
T25 |
378 |
| auto[1] |
auto[1] |
auto[1] |
448422 |
1 |
|
|
T21 |
14 |
|
T23 |
1842 |
|
T25 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9139415 |
1 |
|
|
T21 |
747 |
|
T22 |
1 |
|
T23 |
40815 |
| auto[1] |
6916634 |
1 |
|
|
T21 |
665 |
|
T23 |
30366 |
|
T25 |
1096 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15155325 |
1 |
|
|
T21 |
1379 |
|
T22 |
1 |
|
T23 |
67305 |
| auto[1] |
900724 |
1 |
|
|
T21 |
33 |
|
T23 |
3876 |
|
T25 |
171 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9071193 |
1 |
|
|
T21 |
626 |
|
T22 |
1 |
|
T23 |
42074 |
| auto[1] |
6984856 |
1 |
|
|
T21 |
786 |
|
T23 |
29107 |
|
T25 |
848 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3064828 |
1 |
|
|
T21 |
317 |
|
T23 |
13052 |
|
T25 |
266 |
| auto[1] |
auto[0] |
auto[1] |
453797 |
1 |
|
|
T21 |
17 |
|
T23 |
2053 |
|
T25 |
55 |
| auto[1] |
auto[1] |
auto[0] |
3019304 |
1 |
|
|
T21 |
436 |
|
T23 |
12179 |
|
T25 |
411 |
| auto[1] |
auto[1] |
auto[1] |
446927 |
1 |
|
|
T21 |
16 |
|
T23 |
1823 |
|
T25 |
116 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9063270 |
1 |
|
|
T21 |
564 |
|
T22 |
1 |
|
T23 |
42845 |
| auto[1] |
6992779 |
1 |
|
|
T21 |
848 |
|
T23 |
28336 |
|
T25 |
1034 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15162189 |
1 |
|
|
T21 |
1384 |
|
T22 |
1 |
|
T23 |
67369 |
| auto[1] |
893860 |
1 |
|
|
T21 |
28 |
|
T23 |
3812 |
|
T25 |
196 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9098088 |
1 |
|
|
T21 |
763 |
|
T22 |
1 |
|
T23 |
41873 |
| auto[1] |
6957961 |
1 |
|
|
T21 |
649 |
|
T23 |
29308 |
|
T25 |
1016 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3037303 |
1 |
|
|
T21 |
258 |
|
T23 |
13249 |
|
T25 |
347 |
| auto[1] |
auto[0] |
auto[1] |
448003 |
1 |
|
|
T21 |
10 |
|
T23 |
2070 |
|
T25 |
84 |
| auto[1] |
auto[1] |
auto[0] |
3026798 |
1 |
|
|
T21 |
363 |
|
T23 |
12247 |
|
T25 |
473 |
| auto[1] |
auto[1] |
auto[1] |
445857 |
1 |
|
|
T21 |
18 |
|
T23 |
1742 |
|
T25 |
112 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9089488 |
1 |
|
|
T21 |
640 |
|
T22 |
1 |
|
T23 |
40547 |
| auto[1] |
6966561 |
1 |
|
|
T21 |
772 |
|
T23 |
30634 |
|
T25 |
962 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15162010 |
1 |
|
|
T21 |
1378 |
|
T22 |
1 |
|
T23 |
67377 |
| auto[1] |
894039 |
1 |
|
|
T21 |
34 |
|
T23 |
3804 |
|
T25 |
228 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9119740 |
1 |
|
|
T21 |
638 |
|
T22 |
1 |
|
T23 |
42363 |
| auto[1] |
6936309 |
1 |
|
|
T21 |
774 |
|
T23 |
28818 |
|
T25 |
1128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3023060 |
1 |
|
|
T21 |
347 |
|
T23 |
12601 |
|
T25 |
457 |
| auto[1] |
auto[0] |
auto[1] |
446437 |
1 |
|
|
T21 |
14 |
|
T23 |
1853 |
|
T25 |
123 |
| auto[1] |
auto[1] |
auto[0] |
3019210 |
1 |
|
|
T21 |
393 |
|
T23 |
12413 |
|
T25 |
443 |
| auto[1] |
auto[1] |
auto[1] |
447602 |
1 |
|
|
T21 |
20 |
|
T23 |
1951 |
|
T25 |
105 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9067323 |
1 |
|
|
T21 |
647 |
|
T22 |
1 |
|
T23 |
42145 |
| auto[1] |
6988726 |
1 |
|
|
T21 |
765 |
|
T23 |
29036 |
|
T25 |
932 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15158314 |
1 |
|
|
T21 |
1389 |
|
T22 |
1 |
|
T23 |
67458 |
| auto[1] |
897735 |
1 |
|
|
T21 |
23 |
|
T23 |
3723 |
|
T25 |
189 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9095955 |
1 |
|
|
T21 |
776 |
|
T22 |
1 |
|
T23 |
43248 |
| auto[1] |
6960094 |
1 |
|
|
T21 |
636 |
|
T23 |
27933 |
|
T25 |
935 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3019977 |
1 |
|
|
T21 |
284 |
|
T23 |
13120 |
|
T25 |
447 |
| auto[1] |
auto[0] |
auto[1] |
446615 |
1 |
|
|
T21 |
14 |
|
T23 |
2029 |
|
T25 |
123 |
| auto[1] |
auto[1] |
auto[0] |
3042382 |
1 |
|
|
T21 |
329 |
|
T23 |
11090 |
|
T25 |
299 |
| auto[1] |
auto[1] |
auto[1] |
451120 |
1 |
|
|
T21 |
9 |
|
T23 |
1694 |
|
T25 |
66 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9054474 |
1 |
|
|
T21 |
714 |
|
T22 |
1 |
|
T23 |
41325 |
| auto[1] |
7001575 |
1 |
|
|
T21 |
698 |
|
T23 |
29856 |
|
T25 |
917 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15155883 |
1 |
|
|
T21 |
1381 |
|
T22 |
1 |
|
T23 |
67179 |
| auto[1] |
900166 |
1 |
|
|
T21 |
31 |
|
T23 |
4002 |
|
T25 |
194 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9078641 |
1 |
|
|
T21 |
634 |
|
T22 |
1 |
|
T23 |
41179 |
| auto[1] |
6977408 |
1 |
|
|
T21 |
778 |
|
T23 |
30002 |
|
T25 |
997 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3023017 |
1 |
|
|
T21 |
359 |
|
T23 |
13043 |
|
T25 |
377 |
| auto[1] |
auto[0] |
auto[1] |
447602 |
1 |
|
|
T21 |
11 |
|
T23 |
2051 |
|
T25 |
98 |
| auto[1] |
auto[1] |
auto[0] |
3054225 |
1 |
|
|
T21 |
388 |
|
T23 |
12957 |
|
T25 |
426 |
| auto[1] |
auto[1] |
auto[1] |
452564 |
1 |
|
|
T21 |
20 |
|
T23 |
1951 |
|
T25 |
96 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9099836 |
1 |
|
|
T21 |
644 |
|
T22 |
1 |
|
T23 |
40104 |
| auto[1] |
6956213 |
1 |
|
|
T21 |
768 |
|
T23 |
31077 |
|
T25 |
760 |