Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15155434 |
1 |
|
|
T21 |
1390 |
|
T22 |
1 |
|
T23 |
67110 |
| auto[1] |
900615 |
1 |
|
|
T21 |
22 |
|
T23 |
4071 |
|
T25 |
259 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9082426 |
1 |
|
|
T21 |
780 |
|
T22 |
1 |
|
T23 |
41372 |
| auto[1] |
6973623 |
1 |
|
|
T21 |
632 |
|
T23 |
29809 |
|
T25 |
1291 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3030695 |
1 |
|
|
T21 |
197 |
|
T23 |
12196 |
|
T25 |
533 |
| auto[1] |
auto[0] |
auto[1] |
449201 |
1 |
|
|
T21 |
5 |
|
T23 |
1925 |
|
T25 |
135 |
| auto[1] |
auto[1] |
auto[0] |
3042313 |
1 |
|
|
T21 |
413 |
|
T23 |
13542 |
|
T25 |
499 |
| auto[1] |
auto[1] |
auto[1] |
451414 |
1 |
|
|
T21 |
17 |
|
T23 |
2146 |
|
T25 |
124 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |