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Summary for Variable intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9063270 1 T21 564 T22 1 T23 42845
auto[1] 6992779 1 T21 848 T23 28336 T25 1034


Summary for Variable intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 13235943 1 T21 1313 T22 1 T23 58992
auto[1] 2820106 1 T21 99 T23 12189 T25 631


Summary for Variable type_ctrl_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for type_ctrl_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9112627 1 T21 848 T22 1 T23 41410
auto[1] 6943422 1 T21 564 T23 29771 T25 1253


Summary for Cross cp_cross_type_en_state

Samples crossed: type_ctrl_en intr_en intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 0 4 100.00
Automatically Generated Cross Bins 4 0 4 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cp_cross_type_en_state

Bins
type_ctrl_enintr_enintr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] auto[0] auto[0] 2050788 1 T21 186 T23 9146 T25 310
auto[1] auto[0] auto[1] 1405590 1 T21 48 T23 6368 T25 305
auto[1] auto[1] auto[0] 2072528 1 T21 279 T23 8436 T25 312
auto[1] auto[1] auto[1] 1414516 1 T21 51 T23 5821 T25 326


User Defined Cross Bins for cp_cross_type_en_state

Excluded/Illegal bins
NAMECOUNTSTATUS
intr_type_disabled 0 Excluded

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