Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9136621 |
1 |
|
|
T21 |
781 |
|
T22 |
1 |
|
T23 |
41499 |
| auto[1] |
6919428 |
1 |
|
|
T21 |
631 |
|
T23 |
29682 |
|
T25 |
1082 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15155280 |
1 |
|
|
T21 |
1394 |
|
T22 |
1 |
|
T23 |
67246 |
| auto[1] |
900769 |
1 |
|
|
T21 |
18 |
|
T23 |
3935 |
|
T25 |
127 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9071282 |
1 |
|
|
T21 |
842 |
|
T22 |
1 |
|
T23 |
41272 |
| auto[1] |
6984767 |
1 |
|
|
T21 |
570 |
|
T23 |
29909 |
|
T25 |
593 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3063782 |
1 |
|
|
T21 |
309 |
|
T23 |
13457 |
|
T25 |
147 |
| auto[1] |
auto[0] |
auto[1] |
453656 |
1 |
|
|
T21 |
10 |
|
T23 |
2029 |
|
T25 |
38 |
| auto[1] |
auto[1] |
auto[0] |
3020216 |
1 |
|
|
T21 |
243 |
|
T23 |
12517 |
|
T25 |
319 |
| auto[1] |
auto[1] |
auto[1] |
447113 |
1 |
|
|
T21 |
8 |
|
T23 |
1906 |
|
T25 |
89 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |