Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 944
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T763 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1942183267 May 19 12:22:18 PM PDT 24 May 19 12:22:19 PM PDT 24 30704434 ps
T764 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1990977966 May 19 12:23:31 PM PDT 24 May 19 12:23:53 PM PDT 24 1410831260 ps
T94 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3494096545 May 19 12:19:08 PM PDT 24 May 19 12:19:12 PM PDT 24 64127430 ps
T765 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.836019789 May 19 12:22:17 PM PDT 24 May 19 12:22:19 PM PDT 24 103306067 ps
T766 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2998447570 May 19 12:23:31 PM PDT 24 May 19 12:23:51 PM PDT 24 14102458 ps
T767 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.884953593 May 19 12:19:10 PM PDT 24 May 19 12:19:13 PM PDT 24 13212591 ps
T768 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3520859956 May 19 12:23:26 PM PDT 24 May 19 12:23:43 PM PDT 24 37830374 ps
T769 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3884871803 May 19 12:23:26 PM PDT 24 May 19 12:23:45 PM PDT 24 129488459 ps
T770 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.453286950 May 19 12:22:23 PM PDT 24 May 19 12:22:25 PM PDT 24 112919723 ps
T95 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1914065798 May 19 12:19:15 PM PDT 24 May 19 12:19:16 PM PDT 24 18866066 ps
T40 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.307259186 May 19 12:23:11 PM PDT 24 May 19 12:23:16 PM PDT 24 297779802 ps
T771 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3790061894 May 19 12:22:21 PM PDT 24 May 19 12:22:22 PM PDT 24 29278743 ps
T772 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3268661616 May 19 12:20:49 PM PDT 24 May 19 12:20:51 PM PDT 24 14985375 ps
T773 /workspace/coverage/cover_reg_top/23.gpio_intr_test.1953406580 May 19 12:22:40 PM PDT 24 May 19 12:22:41 PM PDT 24 45306979 ps
T774 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2076011152 May 19 12:19:10 PM PDT 24 May 19 12:19:13 PM PDT 24 18732893 ps
T775 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1926239387 May 19 12:22:21 PM PDT 24 May 19 12:22:23 PM PDT 24 296305729 ps
T776 /workspace/coverage/cover_reg_top/8.gpio_intr_test.464331681 May 19 12:19:45 PM PDT 24 May 19 12:19:46 PM PDT 24 14675461 ps
T777 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.188570070 May 19 12:22:33 PM PDT 24 May 19 12:22:36 PM PDT 24 18946821 ps
T778 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.232075795 May 19 12:20:03 PM PDT 24 May 19 12:20:04 PM PDT 24 59091718 ps
T779 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1897542693 May 19 12:20:12 PM PDT 24 May 19 12:20:13 PM PDT 24 93731925 ps
T780 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2456382371 May 19 12:22:47 PM PDT 24 May 19 12:22:49 PM PDT 24 53364951 ps
T781 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2529608189 May 19 12:22:33 PM PDT 24 May 19 12:22:36 PM PDT 24 72462994 ps
T782 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1501274952 May 19 12:19:25 PM PDT 24 May 19 12:19:27 PM PDT 24 77232723 ps
T783 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1714900115 May 19 12:22:15 PM PDT 24 May 19 12:22:17 PM PDT 24 42633689 ps
T784 /workspace/coverage/cover_reg_top/42.gpio_intr_test.826311919 May 19 12:22:52 PM PDT 24 May 19 12:22:54 PM PDT 24 24100180 ps
T785 /workspace/coverage/cover_reg_top/7.gpio_intr_test.969957878 May 19 12:19:56 PM PDT 24 May 19 12:19:57 PM PDT 24 43987366 ps
T81 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2233171683 May 19 12:22:33 PM PDT 24 May 19 12:22:36 PM PDT 24 24833288 ps
T786 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3688366581 May 19 12:22:20 PM PDT 24 May 19 12:22:22 PM PDT 24 21663034 ps
T99 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.459876519 May 19 12:21:19 PM PDT 24 May 19 12:21:22 PM PDT 24 264945173 ps
T787 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1277966218 May 19 12:19:26 PM PDT 24 May 19 12:19:27 PM PDT 24 54085892 ps
T788 /workspace/coverage/cover_reg_top/18.gpio_intr_test.1503454080 May 19 12:22:34 PM PDT 24 May 19 12:22:36 PM PDT 24 15334584 ps
T789 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2837727717 May 19 12:23:37 PM PDT 24 May 19 12:23:58 PM PDT 24 120268043 ps
T790 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3812569567 May 19 12:22:41 PM PDT 24 May 19 12:22:43 PM PDT 24 118873430 ps
T791 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.904872747 May 19 12:22:27 PM PDT 24 May 19 12:22:28 PM PDT 24 89416096 ps
T792 /workspace/coverage/cover_reg_top/15.gpio_intr_test.853281987 May 19 12:22:30 PM PDT 24 May 19 12:22:31 PM PDT 24 36672544 ps
T793 /workspace/coverage/cover_reg_top/13.gpio_intr_test.105428003 May 19 12:22:58 PM PDT 24 May 19 12:23:00 PM PDT 24 14398667 ps
T794 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3033083665 May 19 12:22:57 PM PDT 24 May 19 12:22:59 PM PDT 24 12607288 ps
T795 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2627483396 May 19 12:19:01 PM PDT 24 May 19 12:19:02 PM PDT 24 71895111 ps
T796 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2799058408 May 19 12:23:31 PM PDT 24 May 19 12:23:53 PM PDT 24 288492709 ps
T797 /workspace/coverage/cover_reg_top/38.gpio_intr_test.224746172 May 19 12:22:54 PM PDT 24 May 19 12:22:55 PM PDT 24 47921170 ps
T798 /workspace/coverage/cover_reg_top/33.gpio_intr_test.1938007523 May 19 12:22:45 PM PDT 24 May 19 12:22:47 PM PDT 24 38234240 ps
T82 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.258265394 May 19 12:23:33 PM PDT 24 May 19 12:23:54 PM PDT 24 45655396 ps
T799 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3890992300 May 19 12:22:41 PM PDT 24 May 19 12:22:43 PM PDT 24 20748804 ps
T800 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1270996043 May 19 12:23:21 PM PDT 24 May 19 12:23:31 PM PDT 24 30796311 ps
T801 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3012566139 May 19 12:23:11 PM PDT 24 May 19 12:23:15 PM PDT 24 562796755 ps
T83 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.177372224 May 19 12:19:02 PM PDT 24 May 19 12:19:03 PM PDT 24 130204702 ps
T802 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3614083371 May 19 12:23:18 PM PDT 24 May 19 12:23:25 PM PDT 24 62317432 ps
T803 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4056106894 May 19 12:23:32 PM PDT 24 May 19 12:23:53 PM PDT 24 119506309 ps
T804 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1834702627 May 19 12:18:42 PM PDT 24 May 19 12:18:46 PM PDT 24 808807950 ps
T100 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1278322583 May 19 12:23:32 PM PDT 24 May 19 12:23:53 PM PDT 24 83725922 ps
T805 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2008879876 May 19 12:17:53 PM PDT 24 May 19 12:17:55 PM PDT 24 94198381 ps
T806 /workspace/coverage/cover_reg_top/46.gpio_intr_test.3061703600 May 19 12:22:48 PM PDT 24 May 19 12:22:50 PM PDT 24 14662807 ps
T807 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1466768999 May 19 12:18:58 PM PDT 24 May 19 12:19:01 PM PDT 24 86551578 ps
T808 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1561489593 May 19 12:22:34 PM PDT 24 May 19 12:22:38 PM PDT 24 304402437 ps
T84 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3527425535 May 19 12:21:48 PM PDT 24 May 19 12:21:50 PM PDT 24 22100969 ps
T41 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1477562947 May 19 12:22:28 PM PDT 24 May 19 12:22:30 PM PDT 24 301391819 ps
T809 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1924601645 May 19 12:20:02 PM PDT 24 May 19 12:20:03 PM PDT 24 20172980 ps
T810 /workspace/coverage/cover_reg_top/35.gpio_intr_test.2382873691 May 19 12:22:49 PM PDT 24 May 19 12:22:50 PM PDT 24 13879249 ps
T811 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1053579827 May 19 12:20:50 PM PDT 24 May 19 12:20:53 PM PDT 24 682140905 ps
T812 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3418093464 May 19 12:23:25 PM PDT 24 May 19 12:23:39 PM PDT 24 19269071 ps
T813 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2128789695 May 19 12:19:07 PM PDT 24 May 19 12:19:11 PM PDT 24 39819878 ps
T814 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.653704991 May 19 12:23:32 PM PDT 24 May 19 12:23:54 PM PDT 24 318855648 ps
T815 /workspace/coverage/cover_reg_top/14.gpio_intr_test.544251892 May 19 12:22:22 PM PDT 24 May 19 12:22:23 PM PDT 24 14187999 ps
T816 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2809143848 May 19 12:22:41 PM PDT 24 May 19 12:22:43 PM PDT 24 32610432 ps
T817 /workspace/coverage/cover_reg_top/43.gpio_intr_test.1924780848 May 19 12:24:31 PM PDT 24 May 19 12:24:40 PM PDT 24 16841821 ps
T818 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2207258620 May 19 12:22:32 PM PDT 24 May 19 12:22:34 PM PDT 24 82280375 ps
T819 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.713463582 May 19 12:22:28 PM PDT 24 May 19 12:22:30 PM PDT 24 21658297 ps
T820 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2510205724 May 19 12:22:45 PM PDT 24 May 19 12:22:47 PM PDT 24 37827216 ps
T86 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1770127969 May 19 12:23:32 PM PDT 24 May 19 12:23:52 PM PDT 24 19267472 ps
T821 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.391996195 May 19 12:21:14 PM PDT 24 May 19 12:21:17 PM PDT 24 46709941 ps
T822 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.919982125 May 19 12:18:21 PM PDT 24 May 19 12:18:23 PM PDT 24 22733245 ps
T823 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3684865317 May 19 12:20:49 PM PDT 24 May 19 12:20:51 PM PDT 24 14860909 ps
T824 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1439525034 May 19 12:22:21 PM PDT 24 May 19 12:22:22 PM PDT 24 19996817 ps
T825 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2605365706 May 19 12:22:58 PM PDT 24 May 19 12:23:00 PM PDT 24 553912487 ps
T826 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.870274775 May 19 12:23:27 PM PDT 24 May 19 12:23:47 PM PDT 24 23328109 ps
T827 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2753587958 May 19 12:22:49 PM PDT 24 May 19 12:22:51 PM PDT 24 15234072 ps
T828 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3911227140 May 19 12:17:52 PM PDT 24 May 19 12:17:54 PM PDT 24 26660184 ps
T829 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.834165653 May 19 12:23:33 PM PDT 24 May 19 12:23:55 PM PDT 24 75911772 ps
T830 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1706472357 May 19 12:23:25 PM PDT 24 May 19 12:23:43 PM PDT 24 132980560 ps
T831 /workspace/coverage/cover_reg_top/24.gpio_intr_test.872360069 May 19 12:22:38 PM PDT 24 May 19 12:22:39 PM PDT 24 13167057 ps
T832 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1711253210 May 19 12:23:11 PM PDT 24 May 19 12:23:17 PM PDT 24 110083466 ps
T833 /workspace/coverage/cover_reg_top/2.gpio_intr_test.3431273814 May 19 12:19:10 PM PDT 24 May 19 12:19:13 PM PDT 24 56470863 ps
T834 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2087472497 May 19 12:22:27 PM PDT 24 May 19 12:22:29 PM PDT 24 67720847 ps
T835 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4143294533 May 19 12:23:15 PM PDT 24 May 19 12:23:20 PM PDT 24 17580706 ps
T836 /workspace/coverage/cover_reg_top/31.gpio_intr_test.4018451113 May 19 12:22:42 PM PDT 24 May 19 12:22:44 PM PDT 24 17227861 ps
T87 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.843181942 May 19 12:18:53 PM PDT 24 May 19 12:18:55 PM PDT 24 15718933 ps
T837 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.685224604 May 19 12:18:50 PM PDT 24 May 19 12:18:53 PM PDT 24 406766699 ps
T838 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1406582401 May 19 12:22:38 PM PDT 24 May 19 12:22:39 PM PDT 24 42250086 ps
T839 /workspace/coverage/cover_reg_top/47.gpio_intr_test.4112579085 May 19 12:22:57 PM PDT 24 May 19 12:22:59 PM PDT 24 22048996 ps
T840 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1648264809 May 19 12:18:58 PM PDT 24 May 19 12:19:00 PM PDT 24 81176051 ps
T841 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1974842361 May 19 12:22:33 PM PDT 24 May 19 12:22:35 PM PDT 24 87138353 ps
T842 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3091183331 May 19 12:23:28 PM PDT 24 May 19 12:23:49 PM PDT 24 105359035 ps
T843 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.95575573 May 19 12:23:38 PM PDT 24 May 19 12:23:58 PM PDT 24 159362558 ps
T844 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2678064538 May 19 12:22:31 PM PDT 24 May 19 12:22:32 PM PDT 24 41875638 ps
T845 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.765822045 May 19 12:55:08 PM PDT 24 May 19 12:55:13 PM PDT 24 75762848 ps
T846 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1257639717 May 19 12:54:27 PM PDT 24 May 19 12:54:35 PM PDT 24 66601756 ps
T847 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2470562733 May 19 12:55:04 PM PDT 24 May 19 12:55:08 PM PDT 24 67489991 ps
T848 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1452731682 May 19 12:55:01 PM PDT 24 May 19 12:55:05 PM PDT 24 116970879 ps
T849 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.38035205 May 19 12:54:28 PM PDT 24 May 19 12:54:31 PM PDT 24 199556604 ps
T850 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4040053373 May 19 12:54:50 PM PDT 24 May 19 12:54:53 PM PDT 24 310644780 ps
T851 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2255251315 May 19 12:54:50 PM PDT 24 May 19 12:54:53 PM PDT 24 58431105 ps
T852 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1535159143 May 19 12:54:49 PM PDT 24 May 19 12:54:53 PM PDT 24 570607823 ps
T853 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2248108821 May 19 12:55:07 PM PDT 24 May 19 12:55:12 PM PDT 24 149336183 ps
T854 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.60878992 May 19 12:55:00 PM PDT 24 May 19 12:55:03 PM PDT 24 106449332 ps
T855 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1615217353 May 19 12:55:06 PM PDT 24 May 19 12:55:11 PM PDT 24 254699628 ps
T856 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4251668061 May 19 12:54:27 PM PDT 24 May 19 12:54:31 PM PDT 24 135616895 ps
T857 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2308934782 May 19 12:54:33 PM PDT 24 May 19 12:54:35 PM PDT 24 129295305 ps
T858 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2420788542 May 19 12:54:38 PM PDT 24 May 19 12:54:40 PM PDT 24 300535447 ps
T859 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3946592824 May 19 12:55:02 PM PDT 24 May 19 12:55:06 PM PDT 24 122995545 ps
T860 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2090088120 May 19 12:54:59 PM PDT 24 May 19 12:55:01 PM PDT 24 167844254 ps
T861 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1010139470 May 19 12:54:49 PM PDT 24 May 19 12:54:52 PM PDT 24 37255326 ps
T862 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4026264508 May 19 12:55:04 PM PDT 24 May 19 12:55:08 PM PDT 24 102520533 ps
T863 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2218898296 May 19 12:55:03 PM PDT 24 May 19 12:55:07 PM PDT 24 43468116 ps
T864 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2982420454 May 19 12:54:45 PM PDT 24 May 19 12:54:48 PM PDT 24 123507030 ps
T865 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3443555246 May 19 12:54:43 PM PDT 24 May 19 12:54:45 PM PDT 24 57535743 ps
T866 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2145507359 May 19 12:54:49 PM PDT 24 May 19 12:54:52 PM PDT 24 156664593 ps
T867 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3116473568 May 19 12:54:32 PM PDT 24 May 19 12:54:34 PM PDT 24 114958803 ps
T868 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2998695408 May 19 12:54:41 PM PDT 24 May 19 12:54:43 PM PDT 24 92791590 ps
T869 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3331390110 May 19 12:55:06 PM PDT 24 May 19 12:55:12 PM PDT 24 68084914 ps
T870 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3273122057 May 19 12:55:00 PM PDT 24 May 19 12:55:03 PM PDT 24 397423678 ps
T871 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4121412395 May 19 12:54:43 PM PDT 24 May 19 12:54:45 PM PDT 24 74405774 ps
T872 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2027249910 May 19 12:54:33 PM PDT 24 May 19 12:54:37 PM PDT 24 386537143 ps
T873 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3518211672 May 19 12:54:56 PM PDT 24 May 19 12:54:58 PM PDT 24 70270592 ps
T874 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2482866863 May 19 12:54:36 PM PDT 24 May 19 12:54:38 PM PDT 24 33981592 ps
T875 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2688626635 May 19 12:54:40 PM PDT 24 May 19 12:54:43 PM PDT 24 69693593 ps
T876 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2513279808 May 19 12:55:00 PM PDT 24 May 19 12:55:04 PM PDT 24 679793486 ps
T877 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2707067072 May 19 12:54:37 PM PDT 24 May 19 12:54:40 PM PDT 24 46928437 ps
T878 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.560747768 May 19 12:54:39 PM PDT 24 May 19 12:54:41 PM PDT 24 177437671 ps
T879 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3127121546 May 19 12:55:00 PM PDT 24 May 19 12:55:03 PM PDT 24 24206046 ps
T880 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1494717681 May 19 12:54:40 PM PDT 24 May 19 12:54:43 PM PDT 24 139520835 ps
T881 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4251285211 May 19 12:54:39 PM PDT 24 May 19 12:54:41 PM PDT 24 294317997 ps
T882 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.465161835 May 19 12:55:00 PM PDT 24 May 19 12:55:04 PM PDT 24 278258757 ps
T883 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3112248653 May 19 12:54:57 PM PDT 24 May 19 12:55:00 PM PDT 24 164881812 ps
T884 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1061557578 May 19 12:54:53 PM PDT 24 May 19 12:54:55 PM PDT 24 120519671 ps
T885 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1826507108 May 19 12:55:02 PM PDT 24 May 19 12:55:06 PM PDT 24 38470075 ps
T886 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.444348950 May 19 12:54:46 PM PDT 24 May 19 12:54:49 PM PDT 24 76855692 ps
T887 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3611398432 May 19 12:55:00 PM PDT 24 May 19 12:55:03 PM PDT 24 104809343 ps
T888 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.493047788 May 19 12:54:41 PM PDT 24 May 19 12:54:43 PM PDT 24 76557381 ps
T889 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2970457516 May 19 12:55:02 PM PDT 24 May 19 12:55:05 PM PDT 24 510089509 ps
T890 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2765001108 May 19 12:54:46 PM PDT 24 May 19 12:54:49 PM PDT 24 460093615 ps
T891 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3073912639 May 19 12:54:51 PM PDT 24 May 19 12:54:54 PM PDT 24 183729568 ps
T892 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4176714069 May 19 12:54:56 PM PDT 24 May 19 12:54:58 PM PDT 24 117565544 ps
T893 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1260559161 May 19 12:54:38 PM PDT 24 May 19 12:54:40 PM PDT 24 299972811 ps
T894 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.507967449 May 19 12:54:50 PM PDT 24 May 19 12:54:53 PM PDT 24 117218589 ps
T895 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3550805886 May 19 12:54:45 PM PDT 24 May 19 12:54:49 PM PDT 24 152263303 ps
T896 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.860766237 May 19 12:54:23 PM PDT 24 May 19 12:54:26 PM PDT 24 91153206 ps
T897 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3294999747 May 19 12:54:46 PM PDT 24 May 19 12:54:49 PM PDT 24 241208566 ps
T898 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1360565645 May 19 12:54:51 PM PDT 24 May 19 12:54:54 PM PDT 24 414412520 ps
T899 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1614285981 May 19 12:54:46 PM PDT 24 May 19 12:54:49 PM PDT 24 302202415 ps
T900 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2916614069 May 19 12:55:08 PM PDT 24 May 19 12:55:13 PM PDT 24 237212786 ps
T901 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2520288327 May 19 12:54:48 PM PDT 24 May 19 12:54:50 PM PDT 24 30352761 ps
T902 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3006551393 May 19 12:54:49 PM PDT 24 May 19 12:54:52 PM PDT 24 215137366 ps
T903 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2759415215 May 19 12:54:40 PM PDT 24 May 19 12:54:42 PM PDT 24 29593686 ps
T904 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1364665562 May 19 12:54:59 PM PDT 24 May 19 12:55:01 PM PDT 24 65524316 ps
T905 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2616723815 May 19 12:54:54 PM PDT 24 May 19 12:54:56 PM PDT 24 226581272 ps
T906 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.93081062 May 19 12:54:36 PM PDT 24 May 19 12:54:39 PM PDT 24 406116671 ps
T907 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.778019552 May 19 12:54:45 PM PDT 24 May 19 12:54:48 PM PDT 24 267934047 ps
T908 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3638278759 May 19 12:54:32 PM PDT 24 May 19 12:54:34 PM PDT 24 34367905 ps
T909 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3883001333 May 19 12:54:44 PM PDT 24 May 19 12:54:46 PM PDT 24 74832862 ps
T910 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.598309727 May 19 12:54:48 PM PDT 24 May 19 12:54:51 PM PDT 24 337863557 ps
T911 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1802946935 May 19 12:55:02 PM PDT 24 May 19 12:55:07 PM PDT 24 46689499 ps
T912 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3871844088 May 19 12:55:02 PM PDT 24 May 19 12:55:06 PM PDT 24 49151904 ps
T913 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4013969703 May 19 12:55:00 PM PDT 24 May 19 12:55:02 PM PDT 24 284825658 ps
T914 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3178115527 May 19 12:54:50 PM PDT 24 May 19 12:54:54 PM PDT 24 45385025 ps
T915 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1540575176 May 19 12:54:47 PM PDT 24 May 19 12:54:50 PM PDT 24 228847772 ps
T916 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3637327056 May 19 12:55:03 PM PDT 24 May 19 12:55:07 PM PDT 24 137064493 ps
T917 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1097962860 May 19 12:54:34 PM PDT 24 May 19 12:54:37 PM PDT 24 165784902 ps
T918 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2242238372 May 19 12:55:04 PM PDT 24 May 19 12:55:08 PM PDT 24 120843673 ps
T919 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.633668983 May 19 12:55:06 PM PDT 24 May 19 12:55:12 PM PDT 24 166135472 ps
T920 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1410558760 May 19 12:54:42 PM PDT 24 May 19 12:54:44 PM PDT 24 212884135 ps
T921 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1014107033 May 19 12:55:01 PM PDT 24 May 19 12:55:03 PM PDT 24 632914301 ps
T922 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1462824047 May 19 12:54:44 PM PDT 24 May 19 12:54:46 PM PDT 24 58212005 ps
T923 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2497230023 May 19 12:54:49 PM PDT 24 May 19 12:54:51 PM PDT 24 47951986 ps
T924 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2601519335 May 19 12:54:37 PM PDT 24 May 19 12:54:41 PM PDT 24 99614176 ps
T925 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.310348881 May 19 12:55:08 PM PDT 24 May 19 12:55:13 PM PDT 24 88367318 ps
T926 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2685962760 May 19 12:55:04 PM PDT 24 May 19 12:55:09 PM PDT 24 48005850 ps
T927 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4030281426 May 19 12:55:00 PM PDT 24 May 19 12:55:03 PM PDT 24 329453419 ps
T928 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4216378715 May 19 12:54:47 PM PDT 24 May 19 12:54:50 PM PDT 24 268519570 ps
T929 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2370621057 May 19 12:54:34 PM PDT 24 May 19 12:54:37 PM PDT 24 51712410 ps
T930 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.564548292 May 19 12:54:28 PM PDT 24 May 19 12:54:31 PM PDT 24 79845804 ps
T931 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2618093626 May 19 12:54:52 PM PDT 24 May 19 12:54:55 PM PDT 24 934290591 ps
T932 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.148345858 May 19 12:54:31 PM PDT 24 May 19 12:54:34 PM PDT 24 157527517 ps
T933 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3345959324 May 19 12:54:49 PM PDT 24 May 19 12:54:51 PM PDT 24 96866420 ps
T934 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1382293089 May 19 12:54:34 PM PDT 24 May 19 12:54:37 PM PDT 24 70251599 ps
T935 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1762187345 May 19 12:54:46 PM PDT 24 May 19 12:54:49 PM PDT 24 362722512 ps
T936 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2150121350 May 19 12:55:05 PM PDT 24 May 19 12:55:10 PM PDT 24 70641603 ps
T937 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3371563965 May 19 12:54:40 PM PDT 24 May 19 12:54:43 PM PDT 24 107833620 ps
T938 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3719309635 May 19 12:54:55 PM PDT 24 May 19 12:54:58 PM PDT 24 84242893 ps
T939 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3402964930 May 19 12:54:37 PM PDT 24 May 19 12:54:40 PM PDT 24 232781549 ps
T940 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.570407344 May 19 12:54:55 PM PDT 24 May 19 12:54:57 PM PDT 24 238067729 ps
T941 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1753790885 May 19 12:54:38 PM PDT 24 May 19 12:54:41 PM PDT 24 44006126 ps
T942 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3163181228 May 19 12:54:45 PM PDT 24 May 19 12:54:48 PM PDT 24 258391438 ps
T943 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1024723631 May 19 12:54:56 PM PDT 24 May 19 12:54:59 PM PDT 24 51480060 ps
T944 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.884318166 May 19 12:55:02 PM PDT 24 May 19 12:55:06 PM PDT 24 55224607 ps

Test location /workspace/coverage/default/8.gpio_full_random.1807213665
Short name T11
Test name
Test status
Simulation time 1446092233 ps
CPU time 0.95 seconds
Started May 19 12:24:59 PM PDT 24
Finished May 19 12:25:03 PM PDT 24
Peak memory 197232 kb
Host smart-276a3f5b-5e26-4462-ad82-55c686dfa3bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807213665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1807213665
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2206380550
Short name T26
Test name
Test status
Simulation time 545741875 ps
CPU time 2.8 seconds
Started May 19 12:24:01 PM PDT 24
Finished May 19 12:24:11 PM PDT 24
Peak memory 198012 kb
Host smart-c2349778-ceba-4769-872b-13b139839580
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206380550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2206380550
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2781529664
Short name T2
Test name
Test status
Simulation time 137637158 ps
CPU time 1.88 seconds
Started May 19 12:24:23 PM PDT 24
Finished May 19 12:24:33 PM PDT 24
Peak memory 197772 kb
Host smart-1fe03dde-eeab-48ec-850d-335a1c7960be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781529664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2781529664
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2050381354
Short name T28
Test name
Test status
Simulation time 21183226525 ps
CPU time 545.39 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:34:12 PM PDT 24
Peak memory 198032 kb
Host smart-9c9972a4-5c50-47ee-bcfc-86a94b394d0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2050381354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2050381354
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.4199013083
Short name T35
Test name
Test status
Simulation time 83093124 ps
CPU time 1 seconds
Started May 19 12:20:22 PM PDT 24
Finished May 19 12:20:25 PM PDT 24
Peak memory 214704 kb
Host smart-0021238e-8381-4485-ad25-80dcd03848eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199013083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.4199013083
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.178897738
Short name T74
Test name
Test status
Simulation time 27268240 ps
CPU time 0.78 seconds
Started May 19 12:19:10 PM PDT 24
Finished May 19 12:19:13 PM PDT 24
Peak memory 196140 kb
Host smart-9342c0dc-fc7e-4bec-94c6-755ffc92b88b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178897738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.178897738
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2839506809
Short name T39
Test name
Test status
Simulation time 219277769 ps
CPU time 1.46 seconds
Started May 19 12:23:08 PM PDT 24
Finished May 19 12:23:12 PM PDT 24
Peak memory 197872 kb
Host smart-a5d15d44-85f4-49e6-97da-e48c606784b9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839506809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2839506809
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_alert_test.905039865
Short name T176
Test name
Test status
Simulation time 15978338 ps
CPU time 0.6 seconds
Started May 19 12:20:56 PM PDT 24
Finished May 19 12:20:57 PM PDT 24
Peak memory 194332 kb
Host smart-7987d969-f41c-4b37-b183-bd195f5c36d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905039865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.905039865
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1696235398
Short name T88
Test name
Test status
Simulation time 46213321 ps
CPU time 0.79 seconds
Started May 19 12:18:36 PM PDT 24
Finished May 19 12:18:39 PM PDT 24
Peak memory 195912 kb
Host smart-6609e835-742c-4bec-9054-0f768a623b6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696235398 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1696235398
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.459876519
Short name T99
Test name
Test status
Simulation time 264945173 ps
CPU time 1.4 seconds
Started May 19 12:21:19 PM PDT 24
Finished May 19 12:21:22 PM PDT 24
Peak memory 197824 kb
Host smart-aeff29e9-d807-4e92-b06e-57c679aa9e75
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459876519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.459876519
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2559723022
Short name T3
Test name
Test status
Simulation time 479744057 ps
CPU time 3.43 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:24:56 PM PDT 24
Peak memory 195752 kb
Host smart-14d4556a-b1ff-4f8d-8e60-023a5de9cc58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559723022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2559723022
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.258265394
Short name T82
Test name
Test status
Simulation time 45655396 ps
CPU time 0.71 seconds
Started May 19 12:23:33 PM PDT 24
Finished May 19 12:23:54 PM PDT 24
Peak memory 195548 kb
Host smart-f29aaf15-9484-4413-996e-0d58e0911be2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258265394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.258265394
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.653704991
Short name T814
Test name
Test status
Simulation time 318855648 ps
CPU time 1.36 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:54 PM PDT 24
Peak memory 196256 kb
Host smart-dc0e8917-6fdc-4aca-b171-d771f8f4f9df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653704991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.653704991
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1924601645
Short name T809
Test name
Test status
Simulation time 20172980 ps
CPU time 0.6 seconds
Started May 19 12:20:02 PM PDT 24
Finished May 19 12:20:03 PM PDT 24
Peak memory 194604 kb
Host smart-96cb5895-8335-4086-9c8b-9ad3291d2f9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924601645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1924601645
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.870274775
Short name T826
Test name
Test status
Simulation time 23328109 ps
CPU time 0.74 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:47 PM PDT 24
Peak memory 197480 kb
Host smart-bb20ee3a-ce7b-4b8e-b90b-f1f497bbaf45
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870274775 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.870274775
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3072480598
Short name T97
Test name
Test status
Simulation time 13535864 ps
CPU time 0.59 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:47 PM PDT 24
Peak memory 194268 kb
Host smart-6795a076-7ef7-40e2-925a-7d2b07ff8068
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072480598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3072480598
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1650690022
Short name T723
Test name
Test status
Simulation time 38466190 ps
CPU time 0.61 seconds
Started May 19 12:23:24 PM PDT 24
Finished May 19 12:23:37 PM PDT 24
Peak memory 192800 kb
Host smart-81b649f8-c224-428c-9921-4b82c3adfb5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650690022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1650690022
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1097543069
Short name T749
Test name
Test status
Simulation time 176386468 ps
CPU time 1.74 seconds
Started May 19 12:18:33 PM PDT 24
Finished May 19 12:18:35 PM PDT 24
Peak memory 197764 kb
Host smart-b6a66bf3-fd36-48ed-bcfc-a6debd0db9ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097543069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1097543069
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4056106894
Short name T803
Test name
Test status
Simulation time 119506309 ps
CPU time 1.4 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 197592 kb
Host smart-b4a844b8-7912-42b3-b62c-727ee922d56f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056106894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.4056106894
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2397668206
Short name T80
Test name
Test status
Simulation time 28077684 ps
CPU time 0.74 seconds
Started May 19 12:19:10 PM PDT 24
Finished May 19 12:19:13 PM PDT 24
Peak memory 195376 kb
Host smart-3bca1651-7b95-4e6c-b070-ba10cddcc7f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397668206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2397668206
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1750418440
Short name T76
Test name
Test status
Simulation time 109089247 ps
CPU time 1.35 seconds
Started May 19 12:19:09 PM PDT 24
Finished May 19 12:19:13 PM PDT 24
Peak memory 195076 kb
Host smart-b4dc56c9-329f-4112-82cb-1c3388858bb1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750418440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1750418440
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.3911227140
Short name T828
Test name
Test status
Simulation time 26660184 ps
CPU time 0.71 seconds
Started May 19 12:17:52 PM PDT 24
Finished May 19 12:17:54 PM PDT 24
Peak memory 194528 kb
Host smart-71651d17-8125-4f45-a714-acc15aac02b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911227140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.3911227140
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2008879876
Short name T805
Test name
Test status
Simulation time 94198381 ps
CPU time 1.59 seconds
Started May 19 12:17:53 PM PDT 24
Finished May 19 12:17:55 PM PDT 24
Peak memory 197604 kb
Host smart-eb793bb6-46ed-432a-a726-e9d7deedb823
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008879876 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2008879876
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1770127969
Short name T86
Test name
Test status
Simulation time 19267472 ps
CPU time 0.6 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:52 PM PDT 24
Peak memory 194396 kb
Host smart-c7e462b5-2122-4adc-a20b-b9328a90c55b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770127969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1770127969
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2076011152
Short name T774
Test name
Test status
Simulation time 18732893 ps
CPU time 0.58 seconds
Started May 19 12:19:10 PM PDT 24
Finished May 19 12:19:13 PM PDT 24
Peak memory 193192 kb
Host smart-86ceaafe-f246-4904-8288-722997d863fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076011152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2076011152
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3494096545
Short name T94
Test name
Test status
Simulation time 64127430 ps
CPU time 0.72 seconds
Started May 19 12:19:08 PM PDT 24
Finished May 19 12:19:12 PM PDT 24
Peak memory 195536 kb
Host smart-5969b90a-3d09-4054-a18e-2e8bf8ec7abf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494096545 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3494096545
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1674460327
Short name T737
Test name
Test status
Simulation time 114643020 ps
CPU time 2.36 seconds
Started May 19 12:19:10 PM PDT 24
Finished May 19 12:19:15 PM PDT 24
Peak memory 197516 kb
Host smart-91867c14-a62f-4cc1-972e-da5430610a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674460327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1674460327
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.212234865
Short name T33
Test name
Test status
Simulation time 620192077 ps
CPU time 1.23 seconds
Started May 19 12:19:07 PM PDT 24
Finished May 19 12:19:10 PM PDT 24
Peak memory 196676 kb
Host smart-c0c8cb74-483c-4b47-9a99-087936e6c0ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212234865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.212234865
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1701289149
Short name T758
Test name
Test status
Simulation time 116887727 ps
CPU time 1.52 seconds
Started May 19 12:23:31 PM PDT 24
Finished May 19 12:23:52 PM PDT 24
Peak memory 197428 kb
Host smart-bec603e3-4f42-4bec-b2bf-5f22851989a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701289149 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1701289149
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2012920480
Short name T79
Test name
Test status
Simulation time 11471666 ps
CPU time 0.61 seconds
Started May 19 12:20:06 PM PDT 24
Finished May 19 12:20:07 PM PDT 24
Peak memory 194552 kb
Host smart-ca9288af-ac5a-449a-9f7e-c37fa6bef48a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012920480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2012920480
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2386185007
Short name T744
Test name
Test status
Simulation time 51906978 ps
CPU time 0.64 seconds
Started May 19 12:21:48 PM PDT 24
Finished May 19 12:21:51 PM PDT 24
Peak memory 193400 kb
Host smart-5ec78da8-abc8-41a2-ae26-4bcee33992bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386185007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2386185007
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1914065798
Short name T95
Test name
Test status
Simulation time 18866066 ps
CPU time 0.93 seconds
Started May 19 12:19:15 PM PDT 24
Finished May 19 12:19:16 PM PDT 24
Peak memory 196544 kb
Host smart-ccb65da8-0a03-482a-9665-c573242e044f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914065798 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1914065798
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3873044661
Short name T747
Test name
Test status
Simulation time 39349519 ps
CPU time 1.08 seconds
Started May 19 12:20:16 PM PDT 24
Finished May 19 12:20:18 PM PDT 24
Peak memory 197688 kb
Host smart-40695348-c769-48d8-9b15-72c350c6d294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873044661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3873044661
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3959605370
Short name T760
Test name
Test status
Simulation time 22600743 ps
CPU time 1.11 seconds
Started May 19 12:22:48 PM PDT 24
Finished May 19 12:22:50 PM PDT 24
Peak memory 197716 kb
Host smart-167f7b0b-2fac-4b8d-ab39-dd8bd225375f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959605370 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3959605370
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1163195998
Short name T761
Test name
Test status
Simulation time 16215117 ps
CPU time 0.58 seconds
Started May 19 12:21:47 PM PDT 24
Finished May 19 12:21:49 PM PDT 24
Peak memory 193440 kb
Host smart-4a83a142-f53a-44a6-a353-ec24c211a119
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163195998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1163195998
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3385186362
Short name T748
Test name
Test status
Simulation time 40763474 ps
CPU time 0.64 seconds
Started May 19 12:19:56 PM PDT 24
Finished May 19 12:19:57 PM PDT 24
Peak memory 193140 kb
Host smart-b1c56469-193e-4cb1-8a6a-14e835ffb7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385186362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3385186362
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2456382371
Short name T780
Test name
Test status
Simulation time 53364951 ps
CPU time 0.76 seconds
Started May 19 12:22:47 PM PDT 24
Finished May 19 12:22:49 PM PDT 24
Peak memory 196044 kb
Host smart-9f87bfcc-3bbb-4480-bb1c-fa03323c0903
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456382371 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2456382371
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.1846769438
Short name T730
Test name
Test status
Simulation time 39414798 ps
CPU time 1.93 seconds
Started May 19 12:18:42 PM PDT 24
Finished May 19 12:18:46 PM PDT 24
Peak memory 197824 kb
Host smart-63d1f3c3-5400-45e2-b21d-d12b1d7135e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846769438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.1846769438
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.307259186
Short name T40
Test name
Test status
Simulation time 297779802 ps
CPU time 1.11 seconds
Started May 19 12:23:11 PM PDT 24
Finished May 19 12:23:16 PM PDT 24
Peak memory 197588 kb
Host smart-68a1a964-c2ad-452e-8001-f6d849302c33
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307259186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.307259186
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1470914740
Short name T731
Test name
Test status
Simulation time 31052661 ps
CPU time 1.32 seconds
Started May 19 12:21:57 PM PDT 24
Finished May 19 12:21:59 PM PDT 24
Peak memory 198212 kb
Host smart-97a03910-654c-44c6-b09f-d5e2bf0f9009
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470914740 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1470914740
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3527425535
Short name T84
Test name
Test status
Simulation time 22100969 ps
CPU time 0.64 seconds
Started May 19 12:21:48 PM PDT 24
Finished May 19 12:21:50 PM PDT 24
Peak memory 194444 kb
Host smart-00dd0c83-5da9-46e1-8b7f-1fb7d65f3d49
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527425535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3527425535
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3575054730
Short name T734
Test name
Test status
Simulation time 65671208 ps
CPU time 0.53 seconds
Started May 19 12:23:34 PM PDT 24
Finished May 19 12:23:55 PM PDT 24
Peak memory 193112 kb
Host smart-14073e98-3426-4c40-a2f1-9bc0ab01a990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575054730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3575054730
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1501274952
Short name T782
Test name
Test status
Simulation time 77232723 ps
CPU time 0.74 seconds
Started May 19 12:19:25 PM PDT 24
Finished May 19 12:19:27 PM PDT 24
Peak memory 196100 kb
Host smart-c291b39f-c525-4562-b796-48acc21a3f1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501274952 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1501274952
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.834165653
Short name T829
Test name
Test status
Simulation time 75911772 ps
CPU time 2.18 seconds
Started May 19 12:23:33 PM PDT 24
Finished May 19 12:23:55 PM PDT 24
Peak memory 196528 kb
Host smart-3263f71c-5b24-41f2-ae30-477287ff7867
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834165653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.834165653
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.769951239
Short name T42
Test name
Test status
Simulation time 41536174 ps
CPU time 0.84 seconds
Started May 19 12:23:33 PM PDT 24
Finished May 19 12:23:54 PM PDT 24
Peak memory 196900 kb
Host smart-308fad1c-a910-4d17-92f6-2fc038326e86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769951239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.769951239
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1270996043
Short name T800
Test name
Test status
Simulation time 30796311 ps
CPU time 0.85 seconds
Started May 19 12:23:21 PM PDT 24
Finished May 19 12:23:31 PM PDT 24
Peak memory 197056 kb
Host smart-4b0f0a08-8239-4bd0-9a5a-4050d0902831
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270996043 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1270996043
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4114061979
Short name T96
Test name
Test status
Simulation time 38607541 ps
CPU time 0.59 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:23:57 PM PDT 24
Peak memory 194760 kb
Host smart-cfb108ed-3f93-4776-8f5e-dfb76d1ec8e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114061979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4114061979
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.105428003
Short name T793
Test name
Test status
Simulation time 14398667 ps
CPU time 0.62 seconds
Started May 19 12:22:58 PM PDT 24
Finished May 19 12:23:00 PM PDT 24
Peak memory 193820 kb
Host smart-68c2ba64-ec63-45f4-8135-5a687e7f19e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105428003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.105428003
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2389170809
Short name T75
Test name
Test status
Simulation time 36779125 ps
CPU time 0.63 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 194164 kb
Host smart-95a877b8-7af4-421c-b59c-fa2d67986271
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389170809 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2389170809
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.836019789
Short name T765
Test name
Test status
Simulation time 103306067 ps
CPU time 1.3 seconds
Started May 19 12:22:17 PM PDT 24
Finished May 19 12:22:19 PM PDT 24
Peak memory 197796 kb
Host smart-021baad0-c3d9-48ac-8363-ca746ec265c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836019789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.836019789
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1278322583
Short name T100
Test name
Test status
Simulation time 83725922 ps
CPU time 0.84 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 197420 kb
Host smart-59f72123-312b-4650-b576-a8b17a6419d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278322583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1278322583
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3688366581
Short name T786
Test name
Test status
Simulation time 21663034 ps
CPU time 0.98 seconds
Started May 19 12:22:20 PM PDT 24
Finished May 19 12:22:22 PM PDT 24
Peak memory 197840 kb
Host smart-3ece05d4-6a0f-4887-80ab-3684c26518e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688366581 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3688366581
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1942183267
Short name T763
Test name
Test status
Simulation time 30704434 ps
CPU time 0.63 seconds
Started May 19 12:22:18 PM PDT 24
Finished May 19 12:22:19 PM PDT 24
Peak memory 194836 kb
Host smart-ab006ecd-f98d-4767-8770-6d0cabb5034c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942183267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1942183267
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.544251892
Short name T815
Test name
Test status
Simulation time 14187999 ps
CPU time 0.61 seconds
Started May 19 12:22:22 PM PDT 24
Finished May 19 12:22:23 PM PDT 24
Peak memory 193440 kb
Host smart-eda11c22-73b3-4df9-9688-d3fd114b1c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544251892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.544251892
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2678064538
Short name T844
Test name
Test status
Simulation time 41875638 ps
CPU time 0.68 seconds
Started May 19 12:22:31 PM PDT 24
Finished May 19 12:22:32 PM PDT 24
Peak memory 194792 kb
Host smart-b800403c-c774-4182-b781-d6a7677bc64f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678064538 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2678064538
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.448165458
Short name T762
Test name
Test status
Simulation time 861390497 ps
CPU time 2.87 seconds
Started May 19 12:22:16 PM PDT 24
Finished May 19 12:22:20 PM PDT 24
Peak memory 197836 kb
Host smart-606a7b26-d716-45e6-b1db-dbe7ec6981bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448165458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.448165458
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.977830427
Short name T101
Test name
Test status
Simulation time 153960099 ps
CPU time 1 seconds
Started May 19 12:22:18 PM PDT 24
Finished May 19 12:22:20 PM PDT 24
Peak memory 197624 kb
Host smart-990733c4-5d85-4b97-a1e8-16840d7f1d80
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977830427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.977830427
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2532197612
Short name T724
Test name
Test status
Simulation time 75831993 ps
CPU time 0.73 seconds
Started May 19 12:22:19 PM PDT 24
Finished May 19 12:22:21 PM PDT 24
Peak memory 197032 kb
Host smart-2b8134ff-2847-4e5e-abe3-73df73c74cbc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532197612 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2532197612
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1714900115
Short name T783
Test name
Test status
Simulation time 42633689 ps
CPU time 0.61 seconds
Started May 19 12:22:15 PM PDT 24
Finished May 19 12:22:17 PM PDT 24
Peak memory 194548 kb
Host smart-5bf25401-d903-4185-8fcf-78c563e57b90
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714900115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1714900115
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.853281987
Short name T792
Test name
Test status
Simulation time 36672544 ps
CPU time 0.62 seconds
Started May 19 12:22:30 PM PDT 24
Finished May 19 12:22:31 PM PDT 24
Peak memory 193820 kb
Host smart-6b7a6af1-fcec-407f-9539-a062fb4240dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853281987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.853281987
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1439525034
Short name T824
Test name
Test status
Simulation time 19996817 ps
CPU time 0.92 seconds
Started May 19 12:22:21 PM PDT 24
Finished May 19 12:22:22 PM PDT 24
Peak memory 195992 kb
Host smart-a85e23ab-9fa6-4fdf-9031-f1646be0c8a0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439525034 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1439525034
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1926239387
Short name T775
Test name
Test status
Simulation time 296305729 ps
CPU time 1.73 seconds
Started May 19 12:22:21 PM PDT 24
Finished May 19 12:22:23 PM PDT 24
Peak memory 197820 kb
Host smart-3e7fcc38-2d6b-4f80-ab7c-d61c359df59f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926239387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1926239387
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.2605365706
Short name T825
Test name
Test status
Simulation time 553912487 ps
CPU time 1.15 seconds
Started May 19 12:22:58 PM PDT 24
Finished May 19 12:23:00 PM PDT 24
Peak memory 198240 kb
Host smart-adbf7c94-25eb-4966-a2f6-63526dd36108
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605365706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.2605365706
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.453286950
Short name T770
Test name
Test status
Simulation time 112919723 ps
CPU time 0.96 seconds
Started May 19 12:22:23 PM PDT 24
Finished May 19 12:22:25 PM PDT 24
Peak memory 197784 kb
Host smart-e060fd93-d84f-49a5-a90c-375625a81ebc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453286950 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.453286950
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.1525910908
Short name T743
Test name
Test status
Simulation time 16362159 ps
CPU time 0.65 seconds
Started May 19 12:22:31 PM PDT 24
Finished May 19 12:22:32 PM PDT 24
Peak memory 195064 kb
Host smart-6a9c9d25-3fdf-4ff4-845e-04ccd507d403
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525910908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.1525910908
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.599907285
Short name T725
Test name
Test status
Simulation time 38386014 ps
CPU time 0.61 seconds
Started May 19 12:22:22 PM PDT 24
Finished May 19 12:22:23 PM PDT 24
Peak memory 193824 kb
Host smart-ee10aab1-c1b1-4972-900e-53f2f2a13ef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599907285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.599907285
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3732500788
Short name T93
Test name
Test status
Simulation time 27195682 ps
CPU time 0.77 seconds
Started May 19 12:24:55 PM PDT 24
Finished May 19 12:25:00 PM PDT 24
Peak memory 195976 kb
Host smart-5b36c2c0-957c-4f81-b80a-947a0bf6cd35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732500788 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3732500788
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2087472497
Short name T834
Test name
Test status
Simulation time 67720847 ps
CPU time 1.12 seconds
Started May 19 12:22:27 PM PDT 24
Finished May 19 12:22:29 PM PDT 24
Peak memory 198104 kb
Host smart-e98df379-94e0-479b-bc01-c0b0a82040b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087472497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2087472497
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.99408500
Short name T38
Test name
Test status
Simulation time 353612788 ps
CPU time 1.55 seconds
Started May 19 12:22:29 PM PDT 24
Finished May 19 12:22:32 PM PDT 24
Peak memory 197880 kb
Host smart-909b0d2f-093f-4a65-a7b7-facc2699774e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99408500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.gpio_tl_intg_err.99408500
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.904872747
Short name T791
Test name
Test status
Simulation time 89416096 ps
CPU time 0.82 seconds
Started May 19 12:22:27 PM PDT 24
Finished May 19 12:22:28 PM PDT 24
Peak memory 197616 kb
Host smart-329368d1-d011-4184-979e-c1c07263d1b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904872747 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.904872747
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3790061894
Short name T771
Test name
Test status
Simulation time 29278743 ps
CPU time 0.7 seconds
Started May 19 12:22:21 PM PDT 24
Finished May 19 12:22:22 PM PDT 24
Peak memory 194728 kb
Host smart-e8fcaa08-3ed9-4231-b5d1-e122f633942c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790061894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3790061894
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3654336418
Short name T750
Test name
Test status
Simulation time 48115157 ps
CPU time 0.64 seconds
Started May 19 12:22:28 PM PDT 24
Finished May 19 12:22:29 PM PDT 24
Peak memory 194520 kb
Host smart-1e555f26-3894-4161-b514-5ff532eb633e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654336418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3654336418
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.713463582
Short name T819
Test name
Test status
Simulation time 21658297 ps
CPU time 0.67 seconds
Started May 19 12:22:28 PM PDT 24
Finished May 19 12:22:30 PM PDT 24
Peak memory 194724 kb
Host smart-41b994a7-ba09-4932-ad34-25de40648b84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713463582 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.713463582
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1561489593
Short name T808
Test name
Test status
Simulation time 304402437 ps
CPU time 3.13 seconds
Started May 19 12:22:34 PM PDT 24
Finished May 19 12:22:38 PM PDT 24
Peak memory 197756 kb
Host smart-f105d368-0386-4512-976c-cc919509b8f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561489593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1561489593
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1477562947
Short name T41
Test name
Test status
Simulation time 301391819 ps
CPU time 1.48 seconds
Started May 19 12:22:28 PM PDT 24
Finished May 19 12:22:30 PM PDT 24
Peak memory 198076 kb
Host smart-c98542f1-8ab8-44cc-94e2-e7d443b96155
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477562947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1477562947
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1911726335
Short name T746
Test name
Test status
Simulation time 35137806 ps
CPU time 1.69 seconds
Started May 19 12:22:33 PM PDT 24
Finished May 19 12:22:37 PM PDT 24
Peak memory 197820 kb
Host smart-eae67365-863b-4f9e-84c1-b6fad0ffc401
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911726335 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1911726335
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2770860490
Short name T733
Test name
Test status
Simulation time 26459840 ps
CPU time 0.61 seconds
Started May 19 12:22:27 PM PDT 24
Finished May 19 12:22:28 PM PDT 24
Peak memory 195464 kb
Host smart-dce67560-fb23-4c4c-957b-7a3dcccae3b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770860490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2770860490
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.1503454080
Short name T788
Test name
Test status
Simulation time 15334584 ps
CPU time 0.62 seconds
Started May 19 12:22:34 PM PDT 24
Finished May 19 12:22:36 PM PDT 24
Peak memory 193480 kb
Host smart-6034d6cd-8e2c-4f1e-a08b-7ad1db4bc900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503454080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.1503454080
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.188570070
Short name T777
Test name
Test status
Simulation time 18946821 ps
CPU time 0.68 seconds
Started May 19 12:22:33 PM PDT 24
Finished May 19 12:22:36 PM PDT 24
Peak memory 194600 kb
Host smart-dbd5afa8-71c9-494c-92e9-53ea6265333e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188570070 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 18.gpio_same_csr_outstanding.188570070
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1974842361
Short name T841
Test name
Test status
Simulation time 87138353 ps
CPU time 1.7 seconds
Started May 19 12:22:33 PM PDT 24
Finished May 19 12:22:35 PM PDT 24
Peak memory 197772 kb
Host smart-f817eadf-a312-49c9-8a0a-ae56c1a3baa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974842361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1974842361
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2879050436
Short name T32
Test name
Test status
Simulation time 94981129 ps
CPU time 0.91 seconds
Started May 19 12:22:34 PM PDT 24
Finished May 19 12:22:37 PM PDT 24
Peak memory 197076 kb
Host smart-2690c8b1-cb59-47de-8b07-46157d185437
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879050436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2879050436
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2207258620
Short name T818
Test name
Test status
Simulation time 82280375 ps
CPU time 1.05 seconds
Started May 19 12:22:32 PM PDT 24
Finished May 19 12:22:34 PM PDT 24
Peak memory 197820 kb
Host smart-02db8212-89ec-4eee-89be-0ac87bb7afeb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207258620 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2207258620
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.752706336
Short name T751
Test name
Test status
Simulation time 38883089 ps
CPU time 0.6 seconds
Started May 19 12:22:58 PM PDT 24
Finished May 19 12:23:00 PM PDT 24
Peak memory 194532 kb
Host smart-a74bcfd4-8e7d-4608-9f5a-14e8fb0da506
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752706336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio
_csr_rw.752706336
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3812569567
Short name T790
Test name
Test status
Simulation time 118873430 ps
CPU time 0.65 seconds
Started May 19 12:22:41 PM PDT 24
Finished May 19 12:22:43 PM PDT 24
Peak memory 193868 kb
Host smart-1fd2021c-466c-4500-9198-d72820d71bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812569567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3812569567
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.3199262755
Short name T92
Test name
Test status
Simulation time 23259115 ps
CPU time 0.72 seconds
Started May 19 12:22:27 PM PDT 24
Finished May 19 12:22:29 PM PDT 24
Peak memory 195904 kb
Host smart-02e77318-a297-4fe2-b62e-2a5c1da2659a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199262755 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.3199262755
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3012566139
Short name T801
Test name
Test status
Simulation time 562796755 ps
CPU time 1.49 seconds
Started May 19 12:23:11 PM PDT 24
Finished May 19 12:23:15 PM PDT 24
Peak memory 197812 kb
Host smart-1a681f0d-1ba0-4afd-aa7c-63efd973731e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012566139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3012566139
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.427500681
Short name T78
Test name
Test status
Simulation time 60867171 ps
CPU time 2.04 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:49 PM PDT 24
Peak memory 197236 kb
Host smart-90062f4f-0073-4111-9604-3efe55fd6166
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427500681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.427500681
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.1343111713
Short name T98
Test name
Test status
Simulation time 46519391 ps
CPU time 0.64 seconds
Started May 19 12:19:09 PM PDT 24
Finished May 19 12:19:13 PM PDT 24
Peak memory 193612 kb
Host smart-a606183c-8d34-4b72-955c-6567b65903a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343111713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.1343111713
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2929514845
Short name T720
Test name
Test status
Simulation time 113878543 ps
CPU time 0.76 seconds
Started May 19 12:19:08 PM PDT 24
Finished May 19 12:19:11 PM PDT 24
Peak memory 197464 kb
Host smart-259bd840-5337-4b4f-9881-93e7ad7ed335
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929514845 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2929514845
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.884953593
Short name T767
Test name
Test status
Simulation time 13212591 ps
CPU time 0.59 seconds
Started May 19 12:19:10 PM PDT 24
Finished May 19 12:19:13 PM PDT 24
Peak memory 194296 kb
Host smart-af125dc2-bf05-4880-afdb-929e6ce74cf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884953593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.884953593
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3431273814
Short name T833
Test name
Test status
Simulation time 56470863 ps
CPU time 0.68 seconds
Started May 19 12:19:10 PM PDT 24
Finished May 19 12:19:13 PM PDT 24
Peak memory 193940 kb
Host smart-f162ec48-a65d-4f6c-b4b8-667ff3f48144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431273814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3431273814
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3854969492
Short name T90
Test name
Test status
Simulation time 149119438 ps
CPU time 0.66 seconds
Started May 19 12:18:11 PM PDT 24
Finished May 19 12:18:13 PM PDT 24
Peak memory 195736 kb
Host smart-e0af97af-7887-4d79-9789-2ed58e30ac4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854969492 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3854969492
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2128789695
Short name T813
Test name
Test status
Simulation time 39819878 ps
CPU time 2.02 seconds
Started May 19 12:19:07 PM PDT 24
Finished May 19 12:19:11 PM PDT 24
Peak memory 196660 kb
Host smart-8dcb07cf-63f5-4707-a7f4-b4edfaa305bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128789695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2128789695
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3877605723
Short name T43
Test name
Test status
Simulation time 77812337 ps
CPU time 1.18 seconds
Started May 19 12:17:53 PM PDT 24
Finished May 19 12:17:55 PM PDT 24
Peak memory 197648 kb
Host smart-e581c900-5734-4c62-a1be-a20ec86ce417
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877605723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3877605723
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3890992300
Short name T799
Test name
Test status
Simulation time 20748804 ps
CPU time 0.63 seconds
Started May 19 12:22:41 PM PDT 24
Finished May 19 12:22:43 PM PDT 24
Peak memory 193860 kb
Host smart-4492c767-7d6a-4aab-a2b4-3297acdcf331
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890992300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3890992300
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.3442506317
Short name T753
Test name
Test status
Simulation time 13515078 ps
CPU time 0.64 seconds
Started May 19 12:22:38 PM PDT 24
Finished May 19 12:22:39 PM PDT 24
Peak memory 193820 kb
Host smart-ba34c1ec-0185-46bf-aea2-9d4edd09bb7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442506317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.3442506317
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1776767683
Short name T757
Test name
Test status
Simulation time 60132288 ps
CPU time 0.63 seconds
Started May 19 12:23:04 PM PDT 24
Finished May 19 12:23:06 PM PDT 24
Peak memory 193516 kb
Host smart-f0d7ba0a-f01a-4ecf-a5de-fed7000499ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776767683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1776767683
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1953406580
Short name T773
Test name
Test status
Simulation time 45306979 ps
CPU time 0.63 seconds
Started May 19 12:22:40 PM PDT 24
Finished May 19 12:22:41 PM PDT 24
Peak memory 193484 kb
Host smart-f5fe7a84-1948-4b34-927f-94ba00cc406e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953406580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1953406580
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.872360069
Short name T831
Test name
Test status
Simulation time 13167057 ps
CPU time 0.59 seconds
Started May 19 12:22:38 PM PDT 24
Finished May 19 12:22:39 PM PDT 24
Peak memory 194080 kb
Host smart-02f14a32-25af-4ced-a5ba-0cbf918a1a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872360069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.872360069
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1406582401
Short name T838
Test name
Test status
Simulation time 42250086 ps
CPU time 0.66 seconds
Started May 19 12:22:38 PM PDT 24
Finished May 19 12:22:39 PM PDT 24
Peak memory 193808 kb
Host smart-e447569b-3ba7-48b4-a250-52c5c1c82d93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406582401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1406582401
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2809143848
Short name T816
Test name
Test status
Simulation time 32610432 ps
CPU time 0.65 seconds
Started May 19 12:22:41 PM PDT 24
Finished May 19 12:22:43 PM PDT 24
Peak memory 194548 kb
Host smart-7763bfb7-12e7-4c61-a6ea-b2ecb7040fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809143848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2809143848
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.3931495515
Short name T740
Test name
Test status
Simulation time 130853414 ps
CPU time 0.57 seconds
Started May 19 12:22:55 PM PDT 24
Finished May 19 12:22:57 PM PDT 24
Peak memory 193780 kb
Host smart-bc11cacb-e4c2-4bb8-989e-20850eccf160
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931495515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.3931495515
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1165345215
Short name T739
Test name
Test status
Simulation time 15121579 ps
CPU time 0.67 seconds
Started May 19 12:23:25 PM PDT 24
Finished May 19 12:23:39 PM PDT 24
Peak memory 193848 kb
Host smart-8c0d5bfe-425c-455b-bea2-f05e881990ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165345215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1165345215
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1364207621
Short name T752
Test name
Test status
Simulation time 43749321 ps
CPU time 0.61 seconds
Started May 19 12:22:51 PM PDT 24
Finished May 19 12:22:53 PM PDT 24
Peak memory 193472 kb
Host smart-7cc1556e-6fcd-4625-900e-aec2723e5793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364207621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1364207621
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.3704363189
Short name T77
Test name
Test status
Simulation time 15306174 ps
CPU time 0.83 seconds
Started May 19 12:18:20 PM PDT 24
Finished May 19 12:18:21 PM PDT 24
Peak memory 196376 kb
Host smart-b75fdc26-76be-4272-956d-a35222c2ec8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704363189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.3704363189
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.685224604
Short name T837
Test name
Test status
Simulation time 406766699 ps
CPU time 1.61 seconds
Started May 19 12:18:50 PM PDT 24
Finished May 19 12:18:53 PM PDT 24
Peak memory 197368 kb
Host smart-ddca0ce1-0ee7-4cbb-b23a-85048df05550
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685224604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.685224604
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3684865317
Short name T823
Test name
Test status
Simulation time 14860909 ps
CPU time 0.61 seconds
Started May 19 12:20:49 PM PDT 24
Finished May 19 12:20:51 PM PDT 24
Peak memory 194468 kb
Host smart-46f32bc6-891d-4060-8b66-3769ac3f4df0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684865317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3684865317
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3091183331
Short name T842
Test name
Test status
Simulation time 105359035 ps
CPU time 1.29 seconds
Started May 19 12:23:28 PM PDT 24
Finished May 19 12:23:49 PM PDT 24
Peak memory 197652 kb
Host smart-4039dc96-a8d0-4ea7-a9f7-5a7b0adffb39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091183331 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3091183331
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.843181942
Short name T87
Test name
Test status
Simulation time 15718933 ps
CPU time 0.79 seconds
Started May 19 12:18:53 PM PDT 24
Finished May 19 12:18:55 PM PDT 24
Peak memory 193572 kb
Host smart-abf7cbab-f10c-437a-a239-3dedf14de0b4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843181942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_
csr_rw.843181942
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.199537810
Short name T728
Test name
Test status
Simulation time 45227825 ps
CPU time 0.59 seconds
Started May 19 12:23:38 PM PDT 24
Finished May 19 12:23:58 PM PDT 24
Peak memory 193196 kb
Host smart-202044e3-f450-4837-96ed-e2043d864179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199537810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.199537810
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.919982125
Short name T822
Test name
Test status
Simulation time 22733245 ps
CPU time 0.67 seconds
Started May 19 12:18:21 PM PDT 24
Finished May 19 12:18:23 PM PDT 24
Peak memory 194548 kb
Host smart-5b9936f9-d42f-4409-b9ef-1bc83ccddf9f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919982125 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.919982125
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.391996195
Short name T821
Test name
Test status
Simulation time 46709941 ps
CPU time 2.24 seconds
Started May 19 12:21:14 PM PDT 24
Finished May 19 12:21:17 PM PDT 24
Peak memory 197768 kb
Host smart-ba950026-e84f-40e4-8443-6dcf24b83073
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391996195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.391996195
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2837727717
Short name T789
Test name
Test status
Simulation time 120268043 ps
CPU time 0.9 seconds
Started May 19 12:23:37 PM PDT 24
Finished May 19 12:23:58 PM PDT 24
Peak memory 195576 kb
Host smart-6f0c008e-ea55-4c61-a254-fbc7e2ced7b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837727717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2837727717
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2572425920
Short name T738
Test name
Test status
Simulation time 34078603 ps
CPU time 0.64 seconds
Started May 19 12:22:42 PM PDT 24
Finished May 19 12:22:44 PM PDT 24
Peak memory 194592 kb
Host smart-4cd9dc1e-9995-40c9-8c49-c9a520e1af5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572425920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2572425920
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4018451113
Short name T836
Test name
Test status
Simulation time 17227861 ps
CPU time 0.59 seconds
Started May 19 12:22:42 PM PDT 24
Finished May 19 12:22:44 PM PDT 24
Peak memory 193492 kb
Host smart-19eb5907-ab50-4f82-80e9-91929bd320d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018451113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4018451113
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.253627801
Short name T722
Test name
Test status
Simulation time 48662923 ps
CPU time 0.6 seconds
Started May 19 12:22:45 PM PDT 24
Finished May 19 12:22:46 PM PDT 24
Peak memory 194480 kb
Host smart-03a89b59-9246-4add-a7fc-bc0c557a24e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253627801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.253627801
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1938007523
Short name T798
Test name
Test status
Simulation time 38234240 ps
CPU time 0.57 seconds
Started May 19 12:22:45 PM PDT 24
Finished May 19 12:22:47 PM PDT 24
Peak memory 193368 kb
Host smart-3223d271-6e2d-4f12-b3dc-a2779c3b6c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938007523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1938007523
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1788276406
Short name T729
Test name
Test status
Simulation time 47298931 ps
CPU time 0.64 seconds
Started May 19 12:23:00 PM PDT 24
Finished May 19 12:23:01 PM PDT 24
Peak memory 193484 kb
Host smart-08cdf53f-624c-4f90-bbf0-1447ec1fefae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788276406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1788276406
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.2382873691
Short name T810
Test name
Test status
Simulation time 13879249 ps
CPU time 0.6 seconds
Started May 19 12:22:49 PM PDT 24
Finished May 19 12:22:50 PM PDT 24
Peak memory 193456 kb
Host smart-6c160de4-0a65-4d8b-9bdb-93685ef11d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382873691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.2382873691
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3418093464
Short name T812
Test name
Test status
Simulation time 19269071 ps
CPU time 0.62 seconds
Started May 19 12:23:25 PM PDT 24
Finished May 19 12:23:39 PM PDT 24
Peak memory 194536 kb
Host smart-67290af8-7d60-4a91-af98-d07fb2b5057e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418093464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3418093464
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2510205724
Short name T820
Test name
Test status
Simulation time 37827216 ps
CPU time 0.59 seconds
Started May 19 12:22:45 PM PDT 24
Finished May 19 12:22:47 PM PDT 24
Peak memory 193776 kb
Host smart-282ba39c-0550-42c0-a76a-c6bbdd2573b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510205724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2510205724
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.224746172
Short name T797
Test name
Test status
Simulation time 47921170 ps
CPU time 0.6 seconds
Started May 19 12:22:54 PM PDT 24
Finished May 19 12:22:55 PM PDT 24
Peak memory 194480 kb
Host smart-e49634c9-153f-4e8f-aa7f-6abcb5d30c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224746172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.224746172
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1388802879
Short name T721
Test name
Test status
Simulation time 14485022 ps
CPU time 0.62 seconds
Started May 19 12:22:43 PM PDT 24
Finished May 19 12:22:45 PM PDT 24
Peak memory 193400 kb
Host smart-81585317-69cc-427a-b249-cff2415af596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388802879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1388802879
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.177372224
Short name T83
Test name
Test status
Simulation time 130204702 ps
CPU time 0.79 seconds
Started May 19 12:19:02 PM PDT 24
Finished May 19 12:19:03 PM PDT 24
Peak memory 196600 kb
Host smart-64597c8f-9de5-4341-9d23-1b61ff9cfcef
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177372224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.177372224
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.126440551
Short name T85
Test name
Test status
Simulation time 387302509 ps
CPU time 3.35 seconds
Started May 19 12:23:14 PM PDT 24
Finished May 19 12:23:22 PM PDT 24
Peak memory 196188 kb
Host smart-f925985b-b6f2-40b6-8787-ee2f38f1f498
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126440551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.126440551
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1070260760
Short name T745
Test name
Test status
Simulation time 66205111 ps
CPU time 0.72 seconds
Started May 19 12:21:44 PM PDT 24
Finished May 19 12:21:45 PM PDT 24
Peak memory 194844 kb
Host smart-a0a5f029-8487-4267-8455-f30e7e6b67d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070260760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1070260760
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1706472357
Short name T830
Test name
Test status
Simulation time 132980560 ps
CPU time 0.84 seconds
Started May 19 12:23:25 PM PDT 24
Finished May 19 12:23:43 PM PDT 24
Peak memory 196480 kb
Host smart-ae0fbe0e-119e-460c-84d8-3a3c12e9c261
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706472357 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1706472357
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.2233171683
Short name T81
Test name
Test status
Simulation time 24833288 ps
CPU time 0.66 seconds
Started May 19 12:22:33 PM PDT 24
Finished May 19 12:22:36 PM PDT 24
Peak memory 193516 kb
Host smart-e807f951-4585-47c6-bcde-7eb7a152527d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233171683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.2233171683
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3614083371
Short name T802
Test name
Test status
Simulation time 62317432 ps
CPU time 0.65 seconds
Started May 19 12:23:18 PM PDT 24
Finished May 19 12:23:25 PM PDT 24
Peak memory 192068 kb
Host smart-36814772-26a9-420d-a016-ccb04caba5e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614083371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3614083371
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4143294533
Short name T835
Test name
Test status
Simulation time 17580706 ps
CPU time 0.68 seconds
Started May 19 12:23:15 PM PDT 24
Finished May 19 12:23:20 PM PDT 24
Peak memory 195716 kb
Host smart-ecedb3ca-4b92-4a08-a537-58a8a5910c3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143294533 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4143294533
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3884871803
Short name T769
Test name
Test status
Simulation time 129488459 ps
CPU time 1.38 seconds
Started May 19 12:23:26 PM PDT 24
Finished May 19 12:23:45 PM PDT 24
Peak memory 197516 kb
Host smart-0fae64f7-29ea-4576-91b1-ff064f49fe4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884871803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3884871803
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1466768999
Short name T807
Test name
Test status
Simulation time 86551578 ps
CPU time 0.9 seconds
Started May 19 12:18:58 PM PDT 24
Finished May 19 12:19:01 PM PDT 24
Peak memory 197424 kb
Host smart-92979a60-25d4-44da-b7bf-b0e017dff0dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466768999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1466768999
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1320168420
Short name T755
Test name
Test status
Simulation time 13389669 ps
CPU time 0.61 seconds
Started May 19 12:22:43 PM PDT 24
Finished May 19 12:22:45 PM PDT 24
Peak memory 194092 kb
Host smart-91613095-b479-4671-a0c9-3bf0bf664643
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320168420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1320168420
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.3012606466
Short name T754
Test name
Test status
Simulation time 15395320 ps
CPU time 0.61 seconds
Started May 19 12:22:43 PM PDT 24
Finished May 19 12:22:45 PM PDT 24
Peak memory 193332 kb
Host smart-06f62f15-b0a5-4b4a-8b73-5eb5fd0845a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012606466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.3012606466
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.826311919
Short name T784
Test name
Test status
Simulation time 24100180 ps
CPU time 0.76 seconds
Started May 19 12:22:52 PM PDT 24
Finished May 19 12:22:54 PM PDT 24
Peak memory 194264 kb
Host smart-a3d67893-b539-46b4-ac31-a723cb5dff6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826311919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.826311919
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.1924780848
Short name T817
Test name
Test status
Simulation time 16841821 ps
CPU time 0.64 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 191880 kb
Host smart-9c9a2b78-8a04-4fba-8de5-128bcaab7fcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924780848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.1924780848
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.2244506204
Short name T726
Test name
Test status
Simulation time 47189172 ps
CPU time 0.6 seconds
Started May 19 12:22:52 PM PDT 24
Finished May 19 12:22:53 PM PDT 24
Peak memory 193800 kb
Host smart-d8663844-9703-431c-84f4-97a7d53584ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244506204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.2244506204
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2753587958
Short name T827
Test name
Test status
Simulation time 15234072 ps
CPU time 0.58 seconds
Started May 19 12:22:49 PM PDT 24
Finished May 19 12:22:51 PM PDT 24
Peak memory 193408 kb
Host smart-dc5addd2-bd6b-47f7-9d69-26f4501f2154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753587958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2753587958
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3061703600
Short name T806
Test name
Test status
Simulation time 14662807 ps
CPU time 0.62 seconds
Started May 19 12:22:48 PM PDT 24
Finished May 19 12:22:50 PM PDT 24
Peak memory 193440 kb
Host smart-fa7ba581-842a-4e50-9648-7e8a836c28aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061703600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3061703600
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4112579085
Short name T839
Test name
Test status
Simulation time 22048996 ps
CPU time 0.57 seconds
Started May 19 12:22:57 PM PDT 24
Finished May 19 12:22:59 PM PDT 24
Peak memory 193332 kb
Host smart-d8044b42-c76c-41e2-8dbb-daed6909d77c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112579085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4112579085
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1010426518
Short name T741
Test name
Test status
Simulation time 19650204 ps
CPU time 0.66 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 191652 kb
Host smart-270cc2a3-906f-4c7f-bdf5-9259fbc57d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010426518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1010426518
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3033083665
Short name T794
Test name
Test status
Simulation time 12607288 ps
CPU time 0.63 seconds
Started May 19 12:22:57 PM PDT 24
Finished May 19 12:22:59 PM PDT 24
Peak memory 193448 kb
Host smart-469efd74-cdac-4784-b027-f718f8c351fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033083665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3033083665
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1648264809
Short name T840
Test name
Test status
Simulation time 81176051 ps
CPU time 0.78 seconds
Started May 19 12:18:58 PM PDT 24
Finished May 19 12:19:00 PM PDT 24
Peak memory 198036 kb
Host smart-dd1c5136-4741-462b-ab66-0dbd54e6c7e1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648264809 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1648264809
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3852088319
Short name T759
Test name
Test status
Simulation time 32598505 ps
CPU time 0.63 seconds
Started May 19 12:23:15 PM PDT 24
Finished May 19 12:23:19 PM PDT 24
Peak memory 193856 kb
Host smart-52ae9bf7-29db-4793-90fb-e03e157840aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852088319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3852088319
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1998588265
Short name T742
Test name
Test status
Simulation time 22124508 ps
CPU time 0.64 seconds
Started May 19 12:22:33 PM PDT 24
Finished May 19 12:22:36 PM PDT 24
Peak memory 193212 kb
Host smart-a616c0d8-5535-48bc-85f8-1cd8ebbe69f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998588265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1998588265
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.993739543
Short name T71
Test name
Test status
Simulation time 42717162 ps
CPU time 0.91 seconds
Started May 19 12:23:11 PM PDT 24
Finished May 19 12:23:16 PM PDT 24
Peak memory 197520 kb
Host smart-7d8bde3b-1c78-4e04-9510-7c2c5897924a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993739543 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.993739543
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.1711253210
Short name T832
Test name
Test status
Simulation time 110083466 ps
CPU time 3.01 seconds
Started May 19 12:23:11 PM PDT 24
Finished May 19 12:23:17 PM PDT 24
Peak memory 197564 kb
Host smart-2412a440-43cb-44f3-a51e-907447abccab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711253210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.1711253210
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1277966218
Short name T787
Test name
Test status
Simulation time 54085892 ps
CPU time 0.9 seconds
Started May 19 12:19:26 PM PDT 24
Finished May 19 12:19:27 PM PDT 24
Peak memory 197008 kb
Host smart-3090b119-f641-4c74-9624-5e87e338ce22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277966218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1277966218
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2998447570
Short name T766
Test name
Test status
Simulation time 14102458 ps
CPU time 0.71 seconds
Started May 19 12:23:31 PM PDT 24
Finished May 19 12:23:51 PM PDT 24
Peak memory 197124 kb
Host smart-6c976dc6-13e5-40d7-8fd9-9d7ec427b97e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998447570 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2998447570
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3629694900
Short name T72
Test name
Test status
Simulation time 26562136 ps
CPU time 0.59 seconds
Started May 19 12:23:31 PM PDT 24
Finished May 19 12:23:51 PM PDT 24
Peak memory 194208 kb
Host smart-c43fdb34-76e9-419b-8cb2-78a5a88b66e3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629694900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3629694900
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.237764474
Short name T727
Test name
Test status
Simulation time 64811375 ps
CPU time 0.61 seconds
Started May 19 12:20:36 PM PDT 24
Finished May 19 12:20:39 PM PDT 24
Peak memory 194512 kb
Host smart-4e72342c-d69c-4c9a-8270-3d93b5cf4f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237764474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.237764474
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2746174111
Short name T91
Test name
Test status
Simulation time 106771735 ps
CPU time 0.79 seconds
Started May 19 12:20:11 PM PDT 24
Finished May 19 12:20:12 PM PDT 24
Peak memory 196060 kb
Host smart-b1799969-9987-4e6a-bbed-4c0194987cfc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746174111 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2746174111
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2998060540
Short name T736
Test name
Test status
Simulation time 173782277 ps
CPU time 2.9 seconds
Started May 19 12:23:30 PM PDT 24
Finished May 19 12:23:54 PM PDT 24
Peak memory 197500 kb
Host smart-7bec39e3-6ad9-4f0d-b6d5-7f736eec54b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998060540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2998060540
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.558405028
Short name T31
Test name
Test status
Simulation time 121368688 ps
CPU time 1.45 seconds
Started May 19 12:20:12 PM PDT 24
Finished May 19 12:20:15 PM PDT 24
Peak memory 197864 kb
Host smart-09006f91-b117-41b9-8664-fdd3e9b9b6a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558405028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 6.gpio_tl_intg_err.558405028
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2018252593
Short name T756
Test name
Test status
Simulation time 34219441 ps
CPU time 0.9 seconds
Started May 19 12:22:48 PM PDT 24
Finished May 19 12:22:49 PM PDT 24
Peak memory 197716 kb
Host smart-e9434a67-3e72-4ca9-9c41-583cb7679ef6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018252593 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2018252593
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3268661616
Short name T772
Test name
Test status
Simulation time 14985375 ps
CPU time 0.6 seconds
Started May 19 12:20:49 PM PDT 24
Finished May 19 12:20:51 PM PDT 24
Peak memory 195292 kb
Host smart-00415f2d-0d55-4ea5-bd8b-7f933239d67f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268661616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3268661616
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.969957878
Short name T785
Test name
Test status
Simulation time 43987366 ps
CPU time 0.61 seconds
Started May 19 12:19:56 PM PDT 24
Finished May 19 12:19:57 PM PDT 24
Peak memory 192972 kb
Host smart-1cfc2828-1e6f-4c1e-89ed-5822a0d012ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969957878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.969957878
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1897542693
Short name T779
Test name
Test status
Simulation time 93731925 ps
CPU time 0.64 seconds
Started May 19 12:20:12 PM PDT 24
Finished May 19 12:20:13 PM PDT 24
Peak memory 194584 kb
Host smart-de22bbec-8cf4-4cf4-be1d-d0ab22274860
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897542693 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1897542693
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1990977966
Short name T764
Test name
Test status
Simulation time 1410831260 ps
CPU time 1.9 seconds
Started May 19 12:23:31 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 197360 kb
Host smart-fa83d7a0-50e2-40a5-bfc0-38b532430a50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990977966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1990977966
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1053579827
Short name T811
Test name
Test status
Simulation time 682140905 ps
CPU time 1.53 seconds
Started May 19 12:20:50 PM PDT 24
Finished May 19 12:20:53 PM PDT 24
Peak memory 198212 kb
Host smart-e8fc5576-707f-43cf-b787-5ba67e55f4aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053579827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1053579827
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2627483396
Short name T795
Test name
Test status
Simulation time 71895111 ps
CPU time 0.81 seconds
Started May 19 12:19:01 PM PDT 24
Finished May 19 12:19:02 PM PDT 24
Peak memory 198164 kb
Host smart-3e2772dd-992e-4283-8abd-86cb5e5e9fab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627483396 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2627483396
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.828184176
Short name T73
Test name
Test status
Simulation time 11289005 ps
CPU time 0.58 seconds
Started May 19 12:20:11 PM PDT 24
Finished May 19 12:20:12 PM PDT 24
Peak memory 194392 kb
Host smart-e3ba5d64-116c-4fb2-bb63-b1670bc57bc5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828184176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.828184176
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.464331681
Short name T776
Test name
Test status
Simulation time 14675461 ps
CPU time 0.61 seconds
Started May 19 12:19:45 PM PDT 24
Finished May 19 12:19:46 PM PDT 24
Peak memory 193424 kb
Host smart-faf0fbfd-91b3-4376-a40b-2f9097420112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464331681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.464331681
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.232075795
Short name T778
Test name
Test status
Simulation time 59091718 ps
CPU time 0.74 seconds
Started May 19 12:20:03 PM PDT 24
Finished May 19 12:20:04 PM PDT 24
Peak memory 196632 kb
Host smart-807134b3-662c-4cee-855d-770195d58964
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232075795 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.232075795
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1834702627
Short name T804
Test name
Test status
Simulation time 808807950 ps
CPU time 3.12 seconds
Started May 19 12:18:42 PM PDT 24
Finished May 19 12:18:46 PM PDT 24
Peak memory 197736 kb
Host smart-223d0656-21ce-42f4-93df-7cbc1a90d599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834702627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1834702627
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2799058408
Short name T796
Test name
Test status
Simulation time 288492709 ps
CPU time 1.36 seconds
Started May 19 12:23:31 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 197496 kb
Host smart-d3463ac5-844b-47d3-ba95-24ab32837379
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799058408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2799058408
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2529608189
Short name T781
Test name
Test status
Simulation time 72462994 ps
CPU time 1 seconds
Started May 19 12:22:33 PM PDT 24
Finished May 19 12:22:36 PM PDT 24
Peak memory 196708 kb
Host smart-20ba6488-b3df-4a68-85ab-b9ba06543c12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529608189 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2529608189
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1837472808
Short name T735
Test name
Test status
Simulation time 28808806 ps
CPU time 0.63 seconds
Started May 19 12:18:50 PM PDT 24
Finished May 19 12:18:51 PM PDT 24
Peak memory 194612 kb
Host smart-3aab4d08-0c3b-47a8-9f0c-4aa83edbc2b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837472808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1837472808
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3520859956
Short name T768
Test name
Test status
Simulation time 37830374 ps
CPU time 0.57 seconds
Started May 19 12:23:26 PM PDT 24
Finished May 19 12:23:43 PM PDT 24
Peak memory 193464 kb
Host smart-dcaefafd-324e-49c9-908c-d6c070242ab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520859956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3520859956
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3521419519
Short name T89
Test name
Test status
Simulation time 37242452 ps
CPU time 0.71 seconds
Started May 19 12:21:39 PM PDT 24
Finished May 19 12:21:41 PM PDT 24
Peak memory 194760 kb
Host smart-62d4d21a-94c2-4a0c-8df5-9b2b28a83bfb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521419519 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3521419519
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1975064761
Short name T732
Test name
Test status
Simulation time 203905919 ps
CPU time 2.48 seconds
Started May 19 12:23:26 PM PDT 24
Finished May 19 12:23:46 PM PDT 24
Peak memory 197460 kb
Host smart-fdea566a-9918-46fd-b7fd-4116c065bd92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975064761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1975064761
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.95575573
Short name T843
Test name
Test status
Simulation time 159362558 ps
CPU time 1.11 seconds
Started May 19 12:23:38 PM PDT 24
Finished May 19 12:23:58 PM PDT 24
Peak memory 197724 kb
Host smart-571d128e-2892-4e68-b69a-5259e3ebb5a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95575573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.gpio_tl_intg_err.95575573
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1205919012
Short name T567
Test name
Test status
Simulation time 16946250 ps
CPU time 0.58 seconds
Started May 19 12:23:19 PM PDT 24
Finished May 19 12:23:26 PM PDT 24
Peak memory 192376 kb
Host smart-59e72ebb-a88e-4680-b73b-cb02b7be34b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205919012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1205919012
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2731237314
Short name T327
Test name
Test status
Simulation time 26918856 ps
CPU time 0.71 seconds
Started May 19 12:21:35 PM PDT 24
Finished May 19 12:21:36 PM PDT 24
Peak memory 194080 kb
Host smart-bd0f1b9c-34d6-4f48-b091-41465b024e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731237314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2731237314
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.837498139
Short name T463
Test name
Test status
Simulation time 235366646 ps
CPU time 4.57 seconds
Started May 19 12:23:28 PM PDT 24
Finished May 19 12:23:52 PM PDT 24
Peak memory 196504 kb
Host smart-38273e71-3ad7-43e5-b919-614c018cdf76
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837498139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.837498139
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2771968553
Short name T10
Test name
Test status
Simulation time 171845879 ps
CPU time 0.99 seconds
Started May 19 12:23:33 PM PDT 24
Finished May 19 12:23:54 PM PDT 24
Peak memory 197488 kb
Host smart-60b51e38-f2d2-495c-8852-c095d32e3d32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771968553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2771968553
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.491209379
Short name T699
Test name
Test status
Simulation time 144806469 ps
CPU time 1.17 seconds
Started May 19 12:22:09 PM PDT 24
Finished May 19 12:22:11 PM PDT 24
Peak memory 195856 kb
Host smart-faa2fbaa-cdc0-4eb2-a8b6-1320bc983949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491209379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.491209379
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.759510612
Short name T596
Test name
Test status
Simulation time 789694380 ps
CPU time 2.52 seconds
Started May 19 12:23:19 PM PDT 24
Finished May 19 12:23:28 PM PDT 24
Peak memory 196568 kb
Host smart-15dc71fe-8eea-4257-bc94-21d74a7c39f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759510612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.759510612
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.557986334
Short name T583
Test name
Test status
Simulation time 86118247 ps
CPU time 2.37 seconds
Started May 19 12:23:18 PM PDT 24
Finished May 19 12:23:27 PM PDT 24
Peak memory 196412 kb
Host smart-f7250dec-b32e-49cf-9184-610b89115e15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557986334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.557986334
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4127097028
Short name T630
Test name
Test status
Simulation time 23319655 ps
CPU time 0.88 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:48 PM PDT 24
Peak memory 196264 kb
Host smart-4cdaaf65-6776-4387-9726-c79de55474cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127097028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4127097028
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1168766920
Short name T157
Test name
Test status
Simulation time 28375905 ps
CPU time 1.09 seconds
Started May 19 12:22:37 PM PDT 24
Finished May 19 12:22:38 PM PDT 24
Peak memory 195956 kb
Host smart-723ac678-2946-42e6-b687-2adc6de3d428
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168766920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1168766920
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1820689929
Short name T153
Test name
Test status
Simulation time 250369435 ps
CPU time 3.97 seconds
Started May 19 12:20:37 PM PDT 24
Finished May 19 12:20:44 PM PDT 24
Peak memory 197868 kb
Host smart-48ae13c7-f6f0-47be-ac39-6d665df9457d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820689929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1820689929
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1568861200
Short name T443
Test name
Test status
Simulation time 131520590 ps
CPU time 1.28 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:48 PM PDT 24
Peak memory 197192 kb
Host smart-e6617510-7d71-460d-95fe-66dfa7b8715c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568861200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1568861200
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3902865616
Short name T353
Test name
Test status
Simulation time 118642852 ps
CPU time 0.82 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 195448 kb
Host smart-8f2c8374-b2d8-457e-ae4f-13a71db411b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902865616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3902865616
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.928777961
Short name T602
Test name
Test status
Simulation time 32020127080 ps
CPU time 136.48 seconds
Started May 19 12:21:29 PM PDT 24
Finished May 19 12:23:46 PM PDT 24
Peak memory 198008 kb
Host smart-0d6a3958-b09d-42c4-82e8-e0909bb8edda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928777961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.928777961
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2360680005
Short name T400
Test name
Test status
Simulation time 47481672 ps
CPU time 0.57 seconds
Started May 19 12:23:30 PM PDT 24
Finished May 19 12:23:51 PM PDT 24
Peak memory 193744 kb
Host smart-8e471463-60ab-444f-accd-abe7f3be6171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360680005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2360680005
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1394359948
Short name T238
Test name
Test status
Simulation time 340135872 ps
CPU time 11.23 seconds
Started May 19 12:23:26 PM PDT 24
Finished May 19 12:23:55 PM PDT 24
Peak memory 195224 kb
Host smart-6ea312e5-a50f-40f2-a332-c833505a2724
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394359948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1394359948
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3105464251
Short name T455
Test name
Test status
Simulation time 574848813 ps
CPU time 1.04 seconds
Started May 19 12:21:19 PM PDT 24
Finished May 19 12:21:22 PM PDT 24
Peak memory 196376 kb
Host smart-6f5e4003-da15-425d-9244-15db4cdd8e63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105464251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3105464251
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2227611334
Short name T500
Test name
Test status
Simulation time 49238158 ps
CPU time 1.36 seconds
Started May 19 12:22:10 PM PDT 24
Finished May 19 12:22:12 PM PDT 24
Peak memory 196836 kb
Host smart-001ad788-24de-4415-948f-ff597c6c9dfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227611334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2227611334
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.3556341879
Short name T476
Test name
Test status
Simulation time 71198155 ps
CPU time 2.7 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:49 PM PDT 24
Peak memory 197640 kb
Host smart-9693f562-1154-4b66-b9b4-7eabaa442532
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556341879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.3556341879
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3326214798
Short name T124
Test name
Test status
Simulation time 187371559 ps
CPU time 1.94 seconds
Started May 19 12:21:58 PM PDT 24
Finished May 19 12:22:00 PM PDT 24
Peak memory 196740 kb
Host smart-29c0f36f-ef29-496b-bb21-6fa8dc4442c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326214798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3326214798
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1155852497
Short name T561
Test name
Test status
Simulation time 51998729 ps
CPU time 0.61 seconds
Started May 19 12:23:38 PM PDT 24
Finished May 19 12:23:58 PM PDT 24
Peak memory 194480 kb
Host smart-2c8798fa-916f-463a-b9e1-4c5e66f9526e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155852497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1155852497
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3826529562
Short name T105
Test name
Test status
Simulation time 60694425 ps
CPU time 1.24 seconds
Started May 19 12:20:13 PM PDT 24
Finished May 19 12:20:15 PM PDT 24
Peak memory 196772 kb
Host smart-272754dc-15e8-4580-a1f1-1d0489077365
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826529562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3826529562
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.657930581
Short name T532
Test name
Test status
Simulation time 82786419 ps
CPU time 3.03 seconds
Started May 19 12:22:09 PM PDT 24
Finished May 19 12:22:13 PM PDT 24
Peak memory 197800 kb
Host smart-d9c61398-bbb8-47f3-b277-c1b23a3da585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657930581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.657930581
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2984301943
Short name T45
Test name
Test status
Simulation time 367728040 ps
CPU time 1.02 seconds
Started May 19 12:21:50 PM PDT 24
Finished May 19 12:21:53 PM PDT 24
Peak memory 215216 kb
Host smart-cad8793a-a99f-4836-a14a-404afaedc74f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984301943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2984301943
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.11705098
Short name T160
Test name
Test status
Simulation time 86565582 ps
CPU time 1.64 seconds
Started May 19 12:19:20 PM PDT 24
Finished May 19 12:19:23 PM PDT 24
Peak memory 196760 kb
Host smart-49150cbe-37cf-44ff-b565-c03b91266b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11705098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.11705098
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.793245246
Short name T578
Test name
Test status
Simulation time 112324292 ps
CPU time 1.07 seconds
Started May 19 12:20:13 PM PDT 24
Finished May 19 12:20:15 PM PDT 24
Peak memory 195700 kb
Host smart-c89cf948-654e-4572-8dcd-e7c5b4f51bf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793245246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.793245246
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.4017810330
Short name T371
Test name
Test status
Simulation time 27484824759 ps
CPU time 146.28 seconds
Started May 19 12:18:47 PM PDT 24
Finished May 19 12:21:15 PM PDT 24
Peak memory 198360 kb
Host smart-d0c1547d-09de-419e-9d1e-21098ae6df35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017810330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.4017810330
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.4224584679
Short name T460
Test name
Test status
Simulation time 18564002 ps
CPU time 0.62 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:23:56 PM PDT 24
Peak memory 194596 kb
Host smart-b0693cb9-b202-445a-8eab-9725f546eb8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224584679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.4224584679
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2388505701
Short name T462
Test name
Test status
Simulation time 34050001 ps
CPU time 0.81 seconds
Started May 19 12:23:40 PM PDT 24
Finished May 19 12:23:59 PM PDT 24
Peak memory 195408 kb
Host smart-fb9af3bb-59b5-418f-b34e-4d88ed9a5203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388505701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2388505701
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.155587705
Short name T62
Test name
Test status
Simulation time 2848794530 ps
CPU time 10.67 seconds
Started May 19 12:25:04 PM PDT 24
Finished May 19 12:25:20 PM PDT 24
Peak memory 195860 kb
Host smart-66fa6a08-77c2-4cbb-9331-37fc23e1ef1c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155587705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.155587705
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.413435578
Short name T531
Test name
Test status
Simulation time 73036572 ps
CPU time 0.74 seconds
Started May 19 12:23:25 PM PDT 24
Finished May 19 12:23:41 PM PDT 24
Peak memory 195744 kb
Host smart-618e959b-1ac5-43ee-8741-1a5cb1a71f73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413435578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.413435578
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2228342399
Short name T156
Test name
Test status
Simulation time 114916454 ps
CPU time 1.38 seconds
Started May 19 12:23:24 PM PDT 24
Finished May 19 12:23:39 PM PDT 24
Peak memory 197708 kb
Host smart-98309938-1f54-46bd-9cce-8022eecf79cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228342399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2228342399
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3594064203
Short name T549
Test name
Test status
Simulation time 256246956 ps
CPU time 2.58 seconds
Started May 19 12:25:04 PM PDT 24
Finished May 19 12:25:13 PM PDT 24
Peak memory 195916 kb
Host smart-6cdb408e-08b7-48af-a3c6-39798fa5d6b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594064203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3594064203
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.55651870
Short name T534
Test name
Test status
Simulation time 91408893 ps
CPU time 1.8 seconds
Started May 19 12:23:24 PM PDT 24
Finished May 19 12:23:40 PM PDT 24
Peak memory 195816 kb
Host smart-ac881596-beb4-4f44-862f-d0c8fc68aa82
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55651870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.55651870
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3129466100
Short name T350
Test name
Test status
Simulation time 29886760 ps
CPU time 0.83 seconds
Started May 19 12:23:25 PM PDT 24
Finished May 19 12:23:40 PM PDT 24
Peak memory 196396 kb
Host smart-754f75eb-205b-4fdb-a678-8b7b10602b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129466100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3129466100
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.906942613
Short name T131
Test name
Test status
Simulation time 119774297 ps
CPU time 0.73 seconds
Started May 19 12:23:24 PM PDT 24
Finished May 19 12:23:39 PM PDT 24
Peak memory 195304 kb
Host smart-adeada8f-e841-422c-bb11-415439df973d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906942613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.906942613
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1452883916
Short name T206
Test name
Test status
Simulation time 856492229 ps
CPU time 3.4 seconds
Started May 19 12:23:28 PM PDT 24
Finished May 19 12:23:51 PM PDT 24
Peak memory 197828 kb
Host smart-84a31b3e-6cb5-4c98-9ce0-dc3365d67d74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452883916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1452883916
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3831020536
Short name T181
Test name
Test status
Simulation time 58129046 ps
CPU time 1.07 seconds
Started May 19 12:23:24 PM PDT 24
Finished May 19 12:23:40 PM PDT 24
Peak memory 195972 kb
Host smart-8299a06b-66d1-4c18-b19a-876afad2b46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831020536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3831020536
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3221490497
Short name T609
Test name
Test status
Simulation time 26843455 ps
CPU time 0.82 seconds
Started May 19 12:23:18 PM PDT 24
Finished May 19 12:23:26 PM PDT 24
Peak memory 195040 kb
Host smart-976db525-07d2-4a91-8344-f80006c96192
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221490497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3221490497
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.914292768
Short name T665
Test name
Test status
Simulation time 12654408929 ps
CPU time 123.04 seconds
Started May 19 12:23:24 PM PDT 24
Finished May 19 12:25:42 PM PDT 24
Peak memory 198056 kb
Host smart-6ea7bcfc-1715-4aaa-9bf7-eaff3f061cd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914292768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.g
pio_stress_all.914292768
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1888419062
Short name T600
Test name
Test status
Simulation time 66194551426 ps
CPU time 825.32 seconds
Started May 19 12:23:30 PM PDT 24
Finished May 19 12:37:36 PM PDT 24
Peak memory 198036 kb
Host smart-14306952-03aa-48b7-94a0-95730e17bfe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1888419062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1888419062
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3062046645
Short name T276
Test name
Test status
Simulation time 11944682 ps
CPU time 0.6 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:23:56 PM PDT 24
Peak memory 194840 kb
Host smart-09fb0858-22e3-41cf-a58b-88c8daf7c3e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062046645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3062046645
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2331688558
Short name T601
Test name
Test status
Simulation time 37878286 ps
CPU time 0.68 seconds
Started May 19 12:23:28 PM PDT 24
Finished May 19 12:23:48 PM PDT 24
Peak memory 195084 kb
Host smart-e6cd2a2a-f71b-414b-a2bb-dcdaa1f68858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331688558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2331688558
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.4010761701
Short name T694
Test name
Test status
Simulation time 1980696424 ps
CPU time 12.83 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:25:09 PM PDT 24
Peak memory 194228 kb
Host smart-fb27140f-5a3e-4143-ad85-435fd3ef49af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010761701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.4010761701
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3337613882
Short name T65
Test name
Test status
Simulation time 70806754 ps
CPU time 0.95 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:23:56 PM PDT 24
Peak memory 196360 kb
Host smart-05b0a1ba-321e-4b60-b697-84c62dd16726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337613882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3337613882
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.442606177
Short name T12
Test name
Test status
Simulation time 46244129 ps
CPU time 0.94 seconds
Started May 19 12:23:36 PM PDT 24
Finished May 19 12:23:57 PM PDT 24
Peak memory 196532 kb
Host smart-f1771623-6234-437e-93dd-f9868e08335d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442606177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.442606177
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.270132624
Short name T374
Test name
Test status
Simulation time 162993948 ps
CPU time 1.82 seconds
Started May 19 12:23:28 PM PDT 24
Finished May 19 12:23:49 PM PDT 24
Peak memory 197864 kb
Host smart-226a8a0c-09fc-49cd-ad46-48a8ec3e3e80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270132624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.270132624
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1095809488
Short name T161
Test name
Test status
Simulation time 66912172 ps
CPU time 1.45 seconds
Started May 19 12:23:34 PM PDT 24
Finished May 19 12:23:57 PM PDT 24
Peak memory 196468 kb
Host smart-10ae67dc-63e0-44f0-ad09-cc35555230be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095809488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1095809488
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2696243458
Short name T654
Test name
Test status
Simulation time 328211630 ps
CPU time 1.12 seconds
Started May 19 12:23:33 PM PDT 24
Finished May 19 12:23:54 PM PDT 24
Peak memory 196828 kb
Host smart-8cc08c47-b084-4db9-b8c3-40c6aeaf6b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696243458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2696243458
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1399639901
Short name T227
Test name
Test status
Simulation time 169985703 ps
CPU time 1.03 seconds
Started May 19 12:23:32 PM PDT 24
Finished May 19 12:23:53 PM PDT 24
Peak memory 196996 kb
Host smart-ffc2dedf-2cf0-4fc0-a593-aac9c98ab14f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399639901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1399639901
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.1191919010
Short name T667
Test name
Test status
Simulation time 128524656 ps
CPU time 5.37 seconds
Started May 19 12:23:36 PM PDT 24
Finished May 19 12:24:02 PM PDT 24
Peak memory 197652 kb
Host smart-6c3395f6-e53e-493a-acb9-e592fca5f3b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191919010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.1191919010
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.2269257517
Short name T452
Test name
Test status
Simulation time 181725239 ps
CPU time 1.02 seconds
Started May 19 12:23:37 PM PDT 24
Finished May 19 12:23:58 PM PDT 24
Peak memory 196568 kb
Host smart-83910fe2-a0a3-4f2c-a35e-28c1db7a1712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269257517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2269257517
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3348392555
Short name T142
Test name
Test status
Simulation time 42814896 ps
CPU time 1.15 seconds
Started May 19 12:23:31 PM PDT 24
Finished May 19 12:23:52 PM PDT 24
Peak memory 195920 kb
Host smart-59bfa0e9-c509-4ad5-89d2-2d0e9e5f6459
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348392555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3348392555
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1441982119
Short name T159
Test name
Test status
Simulation time 19904531509 ps
CPU time 125.14 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:26:00 PM PDT 24
Peak memory 198092 kb
Host smart-089dd889-934d-40c8-a11c-e1668839a5ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441982119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1441982119
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.784675859
Short name T715
Test name
Test status
Simulation time 168718648788 ps
CPU time 1640.16 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:51:15 PM PDT 24
Peak memory 198488 kb
Host smart-4decd295-252b-4b69-946f-16f0a10c3dab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=784675859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.784675859
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.21831567
Short name T168
Test name
Test status
Simulation time 41711852 ps
CPU time 0.57 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:57 PM PDT 24
Peak memory 194412 kb
Host smart-3b80e126-0ee7-42db-a8e5-56240da5e376
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21831567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.21831567
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3792865517
Short name T485
Test name
Test status
Simulation time 82554795 ps
CPU time 0.73 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:57 PM PDT 24
Peak memory 191684 kb
Host smart-9508d1f9-d3a8-4700-bef0-65124f2d94e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792865517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3792865517
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.4132763784
Short name T392
Test name
Test status
Simulation time 915762677 ps
CPU time 26.6 seconds
Started May 19 12:23:34 PM PDT 24
Finished May 19 12:24:20 PM PDT 24
Peak memory 198192 kb
Host smart-70e59cb5-096a-4863-b81d-5cb4314e03c5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132763784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.4132763784
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3310965248
Short name T373
Test name
Test status
Simulation time 114138801 ps
CPU time 0.65 seconds
Started May 19 12:23:43 PM PDT 24
Finished May 19 12:24:00 PM PDT 24
Peak memory 194288 kb
Host smart-062b40b9-f50c-4a3e-ae61-2f2650a68802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310965248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3310965248
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2738591104
Short name T249
Test name
Test status
Simulation time 256828992 ps
CPU time 1.08 seconds
Started May 19 12:23:45 PM PDT 24
Finished May 19 12:24:02 PM PDT 24
Peak memory 196032 kb
Host smart-e0424ed3-1bd4-4e53-a718-1cba54864ce4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738591104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2738591104
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1369245359
Short name T430
Test name
Test status
Simulation time 618074854 ps
CPU time 1.58 seconds
Started May 19 12:23:37 PM PDT 24
Finished May 19 12:23:59 PM PDT 24
Peak memory 196124 kb
Host smart-f1a08fcf-9246-4f3f-9b45-5006fd334b1e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369245359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1369245359
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.4228908474
Short name T180
Test name
Test status
Simulation time 401717051 ps
CPU time 1.95 seconds
Started May 19 12:23:30 PM PDT 24
Finished May 19 12:23:51 PM PDT 24
Peak memory 195892 kb
Host smart-97eccf10-9e6e-4132-b474-08d3c814afbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228908474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.4228908474
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2429803611
Short name T195
Test name
Test status
Simulation time 92809297 ps
CPU time 1.04 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:23:56 PM PDT 24
Peak memory 195828 kb
Host smart-3ee1aff3-9b30-4394-9469-c8c180737de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429803611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2429803611
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.697715961
Short name T473
Test name
Test status
Simulation time 101928739 ps
CPU time 0.75 seconds
Started May 19 12:23:31 PM PDT 24
Finished May 19 12:23:52 PM PDT 24
Peak memory 195588 kb
Host smart-6e931cb0-6a33-4fb1-9f4f-0bf934c639ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697715961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.697715961
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1317669613
Short name T7
Test name
Test status
Simulation time 674601028 ps
CPU time 2.4 seconds
Started May 19 12:23:43 PM PDT 24
Finished May 19 12:24:02 PM PDT 24
Peak memory 197764 kb
Host smart-03242cfc-bd62-4de4-8379-1f06bc07eb64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317669613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1317669613
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1752328716
Short name T324
Test name
Test status
Simulation time 37763884 ps
CPU time 1.11 seconds
Started May 19 12:23:31 PM PDT 24
Finished May 19 12:23:52 PM PDT 24
Peak memory 195788 kb
Host smart-48a59deb-5ab6-4a92-8751-0b1d57a8890e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752328716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1752328716
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.934864478
Short name T193
Test name
Test status
Simulation time 191733087 ps
CPU time 1.16 seconds
Started May 19 12:23:28 PM PDT 24
Finished May 19 12:23:49 PM PDT 24
Peak memory 195664 kb
Host smart-bb8290e5-1161-4c06-b7ea-029239af4a7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934864478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.934864478
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3089284184
Short name T617
Test name
Test status
Simulation time 2644955406 ps
CPU time 33.81 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:25:30 PM PDT 24
Peak memory 195804 kb
Host smart-e4bb756b-bc3a-4825-8739-454b283228b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089284184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3089284184
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.2735039937
Short name T135
Test name
Test status
Simulation time 12611172 ps
CPU time 0.65 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:24:53 PM PDT 24
Peak memory 191276 kb
Host smart-a04d8846-a0d7-4984-ab40-c3a8dff73b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735039937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.2735039937
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3799821486
Short name T283
Test name
Test status
Simulation time 120098722 ps
CPU time 0.88 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:57 PM PDT 24
Peak memory 193868 kb
Host smart-76d7320d-6bf4-4fee-8cd2-0faf41ef7b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799821486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3799821486
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.3918905383
Short name T690
Test name
Test status
Simulation time 544849881 ps
CPU time 28.33 seconds
Started May 19 12:23:44 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 196536 kb
Host smart-96ce98f6-c13b-4501-b877-38be715365f7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918905383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.3918905383
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.3968194348
Short name T419
Test name
Test status
Simulation time 37825342 ps
CPU time 0.78 seconds
Started May 19 12:24:46 PM PDT 24
Finished May 19 12:24:48 PM PDT 24
Peak memory 195048 kb
Host smart-61b71ee6-2171-46ef-9af8-d76c7acabe83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968194348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.3968194348
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3840536803
Short name T139
Test name
Test status
Simulation time 188314039 ps
CPU time 1.4 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 194716 kb
Host smart-87434cdd-a46c-4029-a948-040c806fd711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840536803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3840536803
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3374498005
Short name T437
Test name
Test status
Simulation time 465877912 ps
CPU time 1.96 seconds
Started May 19 12:23:34 PM PDT 24
Finished May 19 12:23:56 PM PDT 24
Peak memory 196708 kb
Host smart-971df0f1-72a2-437a-97ac-72ee5ddeee07
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374498005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3374498005
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3363960859
Short name T572
Test name
Test status
Simulation time 54421234 ps
CPU time 1.66 seconds
Started May 19 12:23:34 PM PDT 24
Finished May 19 12:23:55 PM PDT 24
Peak memory 196540 kb
Host smart-0c6e47ab-bc09-4545-b2fc-72fa7a528faa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363960859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3363960859
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3129085627
Short name T295
Test name
Test status
Simulation time 17787214 ps
CPU time 0.74 seconds
Started May 19 12:24:50 PM PDT 24
Finished May 19 12:24:55 PM PDT 24
Peak memory 195164 kb
Host smart-eafd23ae-455d-497c-a332-8f15bede05c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129085627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3129085627
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3186038331
Short name T503
Test name
Test status
Simulation time 42397596 ps
CPU time 0.67 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:57 PM PDT 24
Peak memory 192156 kb
Host smart-ef886103-7aff-4c28-859b-9c0590d493ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186038331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3186038331
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1780010184
Short name T411
Test name
Test status
Simulation time 1702788177 ps
CPU time 4.65 seconds
Started May 19 12:23:46 PM PDT 24
Finished May 19 12:24:05 PM PDT 24
Peak memory 198232 kb
Host smart-f5d26843-4f4f-41e8-99e3-32a125462f72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780010184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1780010184
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.3859594552
Short name T629
Test name
Test status
Simulation time 104995822 ps
CPU time 0.92 seconds
Started May 19 12:23:33 PM PDT 24
Finished May 19 12:23:54 PM PDT 24
Peak memory 196288 kb
Host smart-3ed8da23-1ac5-4c96-aa70-fc6a784977bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859594552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.3859594552
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3720696448
Short name T341
Test name
Test status
Simulation time 263283398 ps
CPU time 0.98 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:57 PM PDT 24
Peak memory 193636 kb
Host smart-3f1980ea-8da4-41b6-9402-b9dc851ffc33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720696448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3720696448
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1444148462
Short name T523
Test name
Test status
Simulation time 32430088484 ps
CPU time 165.1 seconds
Started May 19 12:24:59 PM PDT 24
Finished May 19 12:27:47 PM PDT 24
Peak memory 197796 kb
Host smart-397cf78c-d576-4b8e-abe8-1ab2edf18006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444148462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1444148462
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1324405596
Short name T683
Test name
Test status
Simulation time 144384235165 ps
CPU time 1898.41 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:56:31 PM PDT 24
Peak memory 195824 kb
Host smart-a1622a3a-ed38-4203-bcca-0489f8349cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1324405596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1324405596
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3961276750
Short name T542
Test name
Test status
Simulation time 12133360 ps
CPU time 0.55 seconds
Started May 19 12:24:50 PM PDT 24
Finished May 19 12:24:53 PM PDT 24
Peak memory 193464 kb
Host smart-80a8cdc0-7ec8-483e-a57f-ccab403af318
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961276750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3961276750
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1438964497
Short name T555
Test name
Test status
Simulation time 64177155 ps
CPU time 0.91 seconds
Started May 19 12:24:59 PM PDT 24
Finished May 19 12:25:03 PM PDT 24
Peak memory 195560 kb
Host smart-7b54ba71-a9d0-4663-8eed-2fffffb0dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438964497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1438964497
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2333696668
Short name T618
Test name
Test status
Simulation time 479106284 ps
CPU time 23.65 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:25:16 PM PDT 24
Peak memory 195032 kb
Host smart-d700b2f9-48ff-4d12-b3db-748c9734d113
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333696668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2333696668
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.3149414967
Short name T278
Test name
Test status
Simulation time 61090146 ps
CPU time 0.74 seconds
Started May 19 12:24:58 PM PDT 24
Finished May 19 12:25:03 PM PDT 24
Peak memory 194160 kb
Host smart-a81e7029-e684-496e-8f89-9b08fbdae81a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149414967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.3149414967
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4241822012
Short name T582
Test name
Test status
Simulation time 29515227 ps
CPU time 0.62 seconds
Started May 19 12:24:59 PM PDT 24
Finished May 19 12:25:03 PM PDT 24
Peak memory 194672 kb
Host smart-1bf55883-f2a9-42f9-95c7-3da7de49ab9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241822012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4241822012
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2601605414
Short name T356
Test name
Test status
Simulation time 345060624 ps
CPU time 3.52 seconds
Started May 19 12:24:58 PM PDT 24
Finished May 19 12:25:05 PM PDT 24
Peak memory 195620 kb
Host smart-f07bfb01-c764-40e2-907c-373d3aba0499
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601605414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2601605414
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3972648839
Short name T233
Test name
Test status
Simulation time 178229336 ps
CPU time 0.97 seconds
Started May 19 12:24:51 PM PDT 24
Finished May 19 12:24:55 PM PDT 24
Peak memory 195928 kb
Host smart-00c99cc8-a24f-41ca-956b-067e334f206b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972648839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3972648839
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.869605535
Short name T698
Test name
Test status
Simulation time 223720683 ps
CPU time 1.22 seconds
Started May 19 12:24:50 PM PDT 24
Finished May 19 12:24:54 PM PDT 24
Peak memory 195464 kb
Host smart-65da3653-3063-42d9-8405-666feb717e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869605535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.869605535
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1093180938
Short name T17
Test name
Test status
Simulation time 52656526 ps
CPU time 0.74 seconds
Started May 19 12:24:59 PM PDT 24
Finished May 19 12:25:03 PM PDT 24
Peak memory 195668 kb
Host smart-5367fecc-6170-432d-ba69-83daf7e3c7fa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093180938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1093180938
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_smoke.1447914022
Short name T277
Test name
Test status
Simulation time 88706869 ps
CPU time 0.84 seconds
Started May 19 12:24:50 PM PDT 24
Finished May 19 12:24:54 PM PDT 24
Peak memory 195980 kb
Host smart-ea562243-175d-4ad0-a7bf-e7262c454b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447914022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1447914022
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.560423702
Short name T677
Test name
Test status
Simulation time 284800108 ps
CPU time 1.18 seconds
Started May 19 12:23:40 PM PDT 24
Finished May 19 12:24:00 PM PDT 24
Peak memory 195616 kb
Host smart-68a8f0cc-019e-4cc0-9ec1-9bbff8fddd6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560423702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.560423702
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.4073888504
Short name T410
Test name
Test status
Simulation time 1734456896 ps
CPU time 38.99 seconds
Started May 19 12:24:58 PM PDT 24
Finished May 19 12:25:41 PM PDT 24
Peak memory 195668 kb
Host smart-509bb647-ca2c-41c9-b417-2626c95aa2d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073888504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.4073888504
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1680789935
Short name T638
Test name
Test status
Simulation time 50998689157 ps
CPU time 1170.36 seconds
Started May 19 12:24:59 PM PDT 24
Finished May 19 12:44:32 PM PDT 24
Peak memory 197672 kb
Host smart-a2057d4c-2747-4df3-b39a-1ca03cb0c34e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1680789935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1680789935
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1044918938
Short name T646
Test name
Test status
Simulation time 16058963 ps
CPU time 0.59 seconds
Started May 19 12:23:47 PM PDT 24
Finished May 19 12:24:02 PM PDT 24
Peak memory 193916 kb
Host smart-627a0dd7-7402-4545-a542-e2fcf81fc43b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044918938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1044918938
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2928592699
Short name T679
Test name
Test status
Simulation time 47236432 ps
CPU time 0.9 seconds
Started May 19 12:23:47 PM PDT 24
Finished May 19 12:24:03 PM PDT 24
Peak memory 196836 kb
Host smart-916936ce-81c1-424f-a105-3696c46e9a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928592699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2928592699
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.439634104
Short name T342
Test name
Test status
Simulation time 568139837 ps
CPU time 6.78 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:12 PM PDT 24
Peak memory 195064 kb
Host smart-39a57f27-a9e8-46d7-a32b-e10296b9faa2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439634104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.439634104
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.110616848
Short name T685
Test name
Test status
Simulation time 27085552 ps
CPU time 0.64 seconds
Started May 19 12:23:47 PM PDT 24
Finished May 19 12:24:02 PM PDT 24
Peak memory 194620 kb
Host smart-58fc0313-a14d-427a-902c-8ebff39d0220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110616848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.110616848
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.731192080
Short name T695
Test name
Test status
Simulation time 308360556 ps
CPU time 1.27 seconds
Started May 19 12:23:46 PM PDT 24
Finished May 19 12:24:02 PM PDT 24
Peak memory 197224 kb
Host smart-53c8864c-9af5-4c17-9fd7-303894396d2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731192080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.731192080
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2207030120
Short name T468
Test name
Test status
Simulation time 88029098 ps
CPU time 1.92 seconds
Started May 19 12:23:47 PM PDT 24
Finished May 19 12:24:03 PM PDT 24
Peak memory 198280 kb
Host smart-f12e4bd8-a752-4f91-a1ec-8b016afacc18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207030120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2207030120
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.42528575
Short name T433
Test name
Test status
Simulation time 710580171 ps
CPU time 3.12 seconds
Started May 19 12:23:51 PM PDT 24
Finished May 19 12:24:07 PM PDT 24
Peak memory 197508 kb
Host smart-b7548c96-ef52-46a4-9337-ecf0e4ab8fd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42528575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.42528575
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2804771094
Short name T306
Test name
Test status
Simulation time 21511138 ps
CPU time 0.73 seconds
Started May 19 12:23:46 PM PDT 24
Finished May 19 12:24:02 PM PDT 24
Peak memory 194884 kb
Host smart-bba491ad-1cc2-4879-9e58-03178a7d56e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804771094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2804771094
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3077436545
Short name T236
Test name
Test status
Simulation time 157092216 ps
CPU time 1.15 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:08 PM PDT 24
Peak memory 196576 kb
Host smart-d96d0a7c-d80a-47c7-9460-a1dd59a01be9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077436545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3077436545
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3426134401
Short name T537
Test name
Test status
Simulation time 2921443134 ps
CPU time 4.02 seconds
Started May 19 12:23:52 PM PDT 24
Finished May 19 12:24:08 PM PDT 24
Peak memory 197640 kb
Host smart-35e573f6-2d60-47e6-8cd1-ec8279b77a2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426134401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3426134401
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2175022034
Short name T280
Test name
Test status
Simulation time 63561083 ps
CPU time 0.89 seconds
Started May 19 12:24:58 PM PDT 24
Finished May 19 12:25:03 PM PDT 24
Peak memory 193972 kb
Host smart-d76c46f3-ccd7-4bab-bfdb-02efcd2f6e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175022034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2175022034
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.1495654822
Short name T133
Test name
Test status
Simulation time 79276033 ps
CPU time 1.38 seconds
Started May 19 12:23:45 PM PDT 24
Finished May 19 12:24:02 PM PDT 24
Peak memory 197900 kb
Host smart-44b006d4-a949-424b-85a3-aa84d9cf5e6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495654822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.1495654822
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1990077502
Short name T486
Test name
Test status
Simulation time 3995295693 ps
CPU time 50.53 seconds
Started May 19 12:24:59 PM PDT 24
Finished May 19 12:25:53 PM PDT 24
Peak memory 197900 kb
Host smart-7666cf15-1185-480d-87b2-f05200c7f5b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990077502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1990077502
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.134798482
Short name T30
Test name
Test status
Simulation time 57633227903 ps
CPU time 1639.85 seconds
Started May 19 12:23:51 PM PDT 24
Finished May 19 12:51:24 PM PDT 24
Peak memory 198024 kb
Host smart-08c8b13e-c881-4a87-872d-14874c07c4f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=134798482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.134798482
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3716480723
Short name T425
Test name
Test status
Simulation time 18990562 ps
CPU time 0.57 seconds
Started May 19 12:24:04 PM PDT 24
Finished May 19 12:24:13 PM PDT 24
Peak memory 193708 kb
Host smart-e4428b96-849e-4e08-9023-caa5b864a01d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716480723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3716480723
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3415135148
Short name T256
Test name
Test status
Simulation time 16504742 ps
CPU time 0.61 seconds
Started May 19 12:24:55 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 193936 kb
Host smart-13c8a813-80b2-40f9-a0d5-e5b388b1010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415135148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3415135148
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1358236318
Short name T669
Test name
Test status
Simulation time 1473614838 ps
CPU time 12.8 seconds
Started May 19 12:23:51 PM PDT 24
Finished May 19 12:24:16 PM PDT 24
Peak memory 196952 kb
Host smart-fdc43588-4282-43a5-9743-add53e8c01f4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358236318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1358236318
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3416306777
Short name T516
Test name
Test status
Simulation time 1082727616 ps
CPU time 0.88 seconds
Started May 19 12:23:54 PM PDT 24
Finished May 19 12:24:05 PM PDT 24
Peak memory 196088 kb
Host smart-367cea18-6ab3-4c75-aa1d-93d40910dddb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416306777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3416306777
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.841668091
Short name T13
Test name
Test status
Simulation time 32990916 ps
CPU time 0.71 seconds
Started May 19 12:23:51 PM PDT 24
Finished May 19 12:24:04 PM PDT 24
Peak memory 194236 kb
Host smart-5334c8ea-2a43-4a3e-9ebb-3496b3d0e32f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841668091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.841668091
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2808730436
Short name T243
Test name
Test status
Simulation time 92594097 ps
CPU time 3.45 seconds
Started May 19 12:24:56 PM PDT 24
Finished May 19 12:25:03 PM PDT 24
Peak memory 197868 kb
Host smart-9e7cf41f-f6f1-405c-ae96-d81ab61e2b24
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808730436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2808730436
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.982233701
Short name T382
Test name
Test status
Simulation time 134275674 ps
CPU time 3.32 seconds
Started May 19 12:24:57 PM PDT 24
Finished May 19 12:25:04 PM PDT 24
Peak memory 197848 kb
Host smart-1480ee87-53a5-4485-a372-cec2ca565850
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982233701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
982233701
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.4033520331
Short name T213
Test name
Test status
Simulation time 244635823 ps
CPU time 1.19 seconds
Started May 19 12:23:52 PM PDT 24
Finished May 19 12:24:05 PM PDT 24
Peak memory 197820 kb
Host smart-6a052364-6ab7-4c31-aa67-93ac134b21aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033520331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.4033520331
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1947454278
Short name T265
Test name
Test status
Simulation time 471772444 ps
CPU time 1.07 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:08 PM PDT 24
Peak memory 196736 kb
Host smart-66f9b198-43ef-4533-9376-56fe10d0cdbe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947454278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1947454278
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.4105438981
Short name T564
Test name
Test status
Simulation time 1557409908 ps
CPU time 2.58 seconds
Started May 19 12:23:53 PM PDT 24
Finished May 19 12:24:07 PM PDT 24
Peak memory 197904 kb
Host smart-d5b2a5bf-7ede-4916-9fc2-0c4a326901b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105438981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.4105438981
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1831453549
Short name T704
Test name
Test status
Simulation time 165016184 ps
CPU time 0.96 seconds
Started May 19 12:24:59 PM PDT 24
Finished May 19 12:25:03 PM PDT 24
Peak memory 196388 kb
Host smart-417b947e-f0c6-4667-9791-aedb58398844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831453549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1831453549
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3015243942
Short name T477
Test name
Test status
Simulation time 222467772 ps
CPU time 1.23 seconds
Started May 19 12:23:52 PM PDT 24
Finished May 19 12:24:05 PM PDT 24
Peak memory 195652 kb
Host smart-8c545698-a183-49da-8e24-1891e6a8d4ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015243942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3015243942
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1909678003
Short name T635
Test name
Test status
Simulation time 18429185993 ps
CPU time 109.19 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:27:13 PM PDT 24
Peak memory 197932 kb
Host smart-5c4db773-68c2-4c13-a5c1-16038bd14db0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909678003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1909678003
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1604751080
Short name T59
Test name
Test status
Simulation time 95092844727 ps
CPU time 1250.07 seconds
Started May 19 12:24:04 PM PDT 24
Finished May 19 12:45:03 PM PDT 24
Peak memory 198120 kb
Host smart-c874fdb2-0780-43a9-8578-189300cb0d43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1604751080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1604751080
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.4207168553
Short name T289
Test name
Test status
Simulation time 104061369 ps
CPU time 0.62 seconds
Started May 19 12:23:52 PM PDT 24
Finished May 19 12:24:04 PM PDT 24
Peak memory 193812 kb
Host smart-db64ed7a-2267-4c84-81c6-724d07fadcc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207168553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.4207168553
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.797650294
Short name T682
Test name
Test status
Simulation time 55426441 ps
CPU time 0.93 seconds
Started May 19 12:23:52 PM PDT 24
Finished May 19 12:24:05 PM PDT 24
Peak memory 195656 kb
Host smart-a0cf609e-c4ab-4c98-b066-42d307c7da90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797650294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.797650294
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.3641700742
Short name T351
Test name
Test status
Simulation time 2457191577 ps
CPU time 21.1 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:42 PM PDT 24
Peak memory 196664 kb
Host smart-781a7cda-4e28-4759-9e0a-56307150f05e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641700742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.3641700742
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1325331119
Short name T27
Test name
Test status
Simulation time 92642149 ps
CPU time 0.99 seconds
Started May 19 12:25:12 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 197772 kb
Host smart-ae3aaf23-115b-4474-84f2-60e4f4e1d453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325331119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1325331119
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1759960827
Short name T388
Test name
Test status
Simulation time 258904098 ps
CPU time 1.08 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:22 PM PDT 24
Peak memory 195944 kb
Host smart-f9e0e6e9-2bb5-4bf1-bd92-8449be2d00a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759960827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1759960827
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1036286478
Short name T577
Test name
Test status
Simulation time 74451450 ps
CPU time 2.35 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 196304 kb
Host smart-5b913549-789e-41ef-834f-4b3e56053a33
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036286478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1036286478
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3916452973
Short name T431
Test name
Test status
Simulation time 121237867 ps
CPU time 2.22 seconds
Started May 19 12:25:14 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 196800 kb
Host smart-52bdd8f6-7d53-47c2-90e7-c71425553464
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916452973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3916452973
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2746879218
Short name T201
Test name
Test status
Simulation time 44783224 ps
CPU time 1.22 seconds
Started May 19 12:25:14 PM PDT 24
Finished May 19 12:25:23 PM PDT 24
Peak memory 197864 kb
Host smart-45064768-c481-425b-8568-6a0b9ca618bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746879218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2746879218
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.723639853
Short name T66
Test name
Test status
Simulation time 109373571 ps
CPU time 1.06 seconds
Started May 19 12:24:04 PM PDT 24
Finished May 19 12:24:12 PM PDT 24
Peak memory 196632 kb
Host smart-231ed0e2-2b67-49f6-9058-4e74935efc6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723639853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup
_pulldown.723639853
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2581323361
Short name T229
Test name
Test status
Simulation time 1767658985 ps
CPU time 5.34 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:29 PM PDT 24
Peak memory 197748 kb
Host smart-be3b1b00-4434-4f80-b9bf-6c5a6559e88b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581323361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2581323361
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.4082470270
Short name T123
Test name
Test status
Simulation time 310015204 ps
CPU time 0.91 seconds
Started May 19 12:24:05 PM PDT 24
Finished May 19 12:24:14 PM PDT 24
Peak memory 195340 kb
Host smart-409a2b67-ef05-4505-a884-1891f0db4a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082470270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.4082470270
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1364567173
Short name T346
Test name
Test status
Simulation time 75321330 ps
CPU time 1.33 seconds
Started May 19 12:23:52 PM PDT 24
Finished May 19 12:24:05 PM PDT 24
Peak memory 195404 kb
Host smart-e547f79a-78a8-4e4b-864c-96294fce056e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364567173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1364567173
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2618333552
Short name T4
Test name
Test status
Simulation time 19727418123 ps
CPU time 205.6 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:28:49 PM PDT 24
Peak memory 198044 kb
Host smart-6b25f3f1-b645-4b82-9c8e-1e21d4c13207
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618333552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2618333552
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.96974399
Short name T177
Test name
Test status
Simulation time 14827771 ps
CPU time 0.6 seconds
Started May 19 12:23:57 PM PDT 24
Finished May 19 12:24:06 PM PDT 24
Peak memory 194300 kb
Host smart-86f953a1-d37c-4cef-9fa2-052885c6a24c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96974399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.96974399
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3878215431
Short name T340
Test name
Test status
Simulation time 35529306 ps
CPU time 0.71 seconds
Started May 19 12:24:04 PM PDT 24
Finished May 19 12:24:13 PM PDT 24
Peak memory 195136 kb
Host smart-08df8c4e-0432-4ba9-9d3c-c109235e63dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878215431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3878215431
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1104998675
Short name T119
Test name
Test status
Simulation time 1284209169 ps
CPU time 11.17 seconds
Started May 19 12:24:06 PM PDT 24
Finished May 19 12:24:25 PM PDT 24
Peak memory 196544 kb
Host smart-92922435-3b2d-4e34-84c7-a847b328d913
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104998675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1104998675
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3346371121
Short name T18
Test name
Test status
Simulation time 247183581 ps
CPU time 0.84 seconds
Started May 19 12:24:01 PM PDT 24
Finished May 19 12:24:10 PM PDT 24
Peak memory 195912 kb
Host smart-3d50234b-5fd0-4078-a460-80d3e9f2e55f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346371121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3346371121
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1204204697
Short name T223
Test name
Test status
Simulation time 40780822 ps
CPU time 1.12 seconds
Started May 19 12:24:00 PM PDT 24
Finished May 19 12:24:09 PM PDT 24
Peak memory 196412 kb
Host smart-21f647b3-186a-4b4f-b9ba-4e7931925250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204204697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1204204697
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.4008399100
Short name T560
Test name
Test status
Simulation time 328623133 ps
CPU time 3.47 seconds
Started May 19 12:24:01 PM PDT 24
Finished May 19 12:24:11 PM PDT 24
Peak memory 197924 kb
Host smart-03cce63a-317b-460e-9c15-faff54c39298
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008399100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.4008399100
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3044297584
Short name T349
Test name
Test status
Simulation time 71024129 ps
CPU time 1.65 seconds
Started May 19 12:23:58 PM PDT 24
Finished May 19 12:24:08 PM PDT 24
Peak memory 195980 kb
Host smart-5a61969c-769c-4f78-be81-eb23114cf939
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044297584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3044297584
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.964678610
Short name T495
Test name
Test status
Simulation time 70411706 ps
CPU time 0.99 seconds
Started May 19 12:24:04 PM PDT 24
Finished May 19 12:24:14 PM PDT 24
Peak memory 195608 kb
Host smart-5d087878-4998-423d-a12c-6fd09fc6eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964678610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.964678610
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2021887121
Short name T569
Test name
Test status
Simulation time 39034648 ps
CPU time 0.64 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 194192 kb
Host smart-10785122-fe91-421f-b1ac-1c635e116d85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021887121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2021887121
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3428135787
Short name T290
Test name
Test status
Simulation time 146619347 ps
CPU time 3.52 seconds
Started May 19 12:24:03 PM PDT 24
Finished May 19 12:24:14 PM PDT 24
Peak memory 198176 kb
Host smart-1b035d6a-ccbc-47b8-b70f-64c79d877a39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428135787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3428135787
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2131159292
Short name T239
Test name
Test status
Simulation time 367742534 ps
CPU time 1.16 seconds
Started May 19 12:23:54 PM PDT 24
Finished May 19 12:24:05 PM PDT 24
Peak memory 195420 kb
Host smart-5198a9d1-a9df-4b5b-a715-ef84c511feca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131159292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2131159292
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1126934159
Short name T639
Test name
Test status
Simulation time 144936807 ps
CPU time 1.17 seconds
Started May 19 12:23:52 PM PDT 24
Finished May 19 12:24:05 PM PDT 24
Peak memory 195532 kb
Host smart-59d19ac4-7f85-4edd-9d8f-6a2e41331717
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126934159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1126934159
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1215408422
Short name T285
Test name
Test status
Simulation time 155190076480 ps
CPU time 132.27 seconds
Started May 19 12:23:59 PM PDT 24
Finished May 19 12:26:20 PM PDT 24
Peak memory 197964 kb
Host smart-750abe6e-c09c-479c-adcc-4c22b9a353c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215408422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1215408422
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3230214899
Short name T220
Test name
Test status
Simulation time 18579807 ps
CPU time 0.57 seconds
Started May 19 12:24:00 PM PDT 24
Finished May 19 12:24:08 PM PDT 24
Peak memory 193764 kb
Host smart-f101fc02-88e7-420e-a574-c7cec0434ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230214899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3230214899
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3271149939
Short name T707
Test name
Test status
Simulation time 112135103 ps
CPU time 0.92 seconds
Started May 19 12:23:59 PM PDT 24
Finished May 19 12:24:08 PM PDT 24
Peak memory 196192 kb
Host smart-20949e13-4c6d-418c-a013-ec4d1e34fbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271149939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3271149939
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1983976892
Short name T453
Test name
Test status
Simulation time 719551320 ps
CPU time 17.93 seconds
Started May 19 12:23:59 PM PDT 24
Finished May 19 12:24:25 PM PDT 24
Peak memory 196276 kb
Host smart-d81dcb51-7a56-49b5-bfaf-fe932a24a812
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983976892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1983976892
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3725173807
Short name T210
Test name
Test status
Simulation time 159859949 ps
CPU time 0.81 seconds
Started May 19 12:24:08 PM PDT 24
Finished May 19 12:24:17 PM PDT 24
Peak memory 195672 kb
Host smart-abe18db7-0785-4ebc-b112-cb958fa1bfe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725173807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3725173807
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1278143951
Short name T691
Test name
Test status
Simulation time 115887193 ps
CPU time 1.3 seconds
Started May 19 12:24:00 PM PDT 24
Finished May 19 12:24:09 PM PDT 24
Peak memory 196408 kb
Host smart-aa127911-f638-414f-adc5-8ff318769e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278143951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1278143951
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1364702854
Short name T199
Test name
Test status
Simulation time 38861046 ps
CPU time 1.5 seconds
Started May 19 12:24:09 PM PDT 24
Finished May 19 12:24:18 PM PDT 24
Peak memory 197856 kb
Host smart-83115f54-7f20-4554-9414-9671ec95e08a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364702854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1364702854
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1536593742
Short name T25
Test name
Test status
Simulation time 119097536 ps
CPU time 2.29 seconds
Started May 19 12:24:03 PM PDT 24
Finished May 19 12:24:13 PM PDT 24
Peak memory 198204 kb
Host smart-9699190a-aa64-4f5a-a35a-f2eda8b3baf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536593742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1536593742
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2041479310
Short name T404
Test name
Test status
Simulation time 167534647 ps
CPU time 1 seconds
Started May 19 12:24:07 PM PDT 24
Finished May 19 12:24:16 PM PDT 24
Peak memory 195792 kb
Host smart-ca00a19b-239d-4b4c-ae5d-b23f21dc1d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041479310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2041479310
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1132791559
Short name T395
Test name
Test status
Simulation time 100187934 ps
CPU time 0.96 seconds
Started May 19 12:24:03 PM PDT 24
Finished May 19 12:24:11 PM PDT 24
Peak memory 196424 kb
Host smart-faf35172-5e88-4371-bceb-876c53bb63a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132791559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1132791559
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2126462546
Short name T563
Test name
Test status
Simulation time 64428400 ps
CPU time 1.12 seconds
Started May 19 12:24:05 PM PDT 24
Finished May 19 12:24:14 PM PDT 24
Peak memory 196768 kb
Host smart-f38de706-b3d7-4468-99d9-86faa86f246f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126462546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2126462546
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.145853000
Short name T421
Test name
Test status
Simulation time 467665430 ps
CPU time 1.21 seconds
Started May 19 12:24:03 PM PDT 24
Finished May 19 12:24:11 PM PDT 24
Peak memory 195640 kb
Host smart-dbaff7c9-b057-45b6-8d9c-9280945d45b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145853000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.145853000
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3243137822
Short name T325
Test name
Test status
Simulation time 39643740 ps
CPU time 0.85 seconds
Started May 19 12:24:08 PM PDT 24
Finished May 19 12:24:17 PM PDT 24
Peak memory 195244 kb
Host smart-314ca186-bee5-451b-b862-75966ec4981d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243137822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3243137822
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.4164301171
Short name T585
Test name
Test status
Simulation time 11236843041 ps
CPU time 57.55 seconds
Started May 19 12:24:07 PM PDT 24
Finished May 19 12:25:12 PM PDT 24
Peak memory 198068 kb
Host smart-5bcc6f26-372f-4ee2-9fc7-7cea515f3de0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164301171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.4164301171
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2070914599
Short name T55
Test name
Test status
Simulation time 62916225699 ps
CPU time 974.12 seconds
Started May 19 12:23:59 PM PDT 24
Finished May 19 12:40:21 PM PDT 24
Peak memory 198052 kb
Host smart-1eebf9d9-79ab-4787-8f87-b6b4ab4fcb1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2070914599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2070914599
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2718760443
Short name T432
Test name
Test status
Simulation time 87473933 ps
CPU time 0.65 seconds
Started May 19 12:18:06 PM PDT 24
Finished May 19 12:18:08 PM PDT 24
Peak memory 192988 kb
Host smart-5f1319c4-a0be-4054-821c-36121a18f94f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718760443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2718760443
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.2428623760
Short name T407
Test name
Test status
Simulation time 285413530 ps
CPU time 0.95 seconds
Started May 19 12:19:55 PM PDT 24
Finished May 19 12:19:57 PM PDT 24
Peak memory 195360 kb
Host smart-3ef1711c-bf36-4ec2-8200-4dab9ea1617d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428623760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.2428623760
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3248089480
Short name T620
Test name
Test status
Simulation time 1515156359 ps
CPU time 21.81 seconds
Started May 19 12:23:51 PM PDT 24
Finished May 19 12:24:26 PM PDT 24
Peak memory 197172 kb
Host smart-941e4411-fa90-4015-8dec-32715adb6598
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248089480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3248089480
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2340833652
Short name T396
Test name
Test status
Simulation time 122897852 ps
CPU time 0.91 seconds
Started May 19 12:21:46 PM PDT 24
Finished May 19 12:21:47 PM PDT 24
Peak memory 197388 kb
Host smart-8d41831d-ff54-4f4c-92ba-a1ed096887a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340833652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2340833652
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.380503403
Short name T303
Test name
Test status
Simulation time 62710434 ps
CPU time 0.85 seconds
Started May 19 12:20:56 PM PDT 24
Finished May 19 12:20:58 PM PDT 24
Peak memory 195816 kb
Host smart-0db88f28-3ff5-4165-b9eb-35bddfcb48f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380503403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.380503403
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.165077938
Short name T394
Test name
Test status
Simulation time 71232704 ps
CPU time 1.01 seconds
Started May 19 12:21:17 PM PDT 24
Finished May 19 12:21:19 PM PDT 24
Peak memory 196540 kb
Host smart-2c15ae83-6201-4b18-aada-e1c8c595c4ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165077938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.165077938
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3340769749
Short name T398
Test name
Test status
Simulation time 224278802 ps
CPU time 0.93 seconds
Started May 19 12:20:03 PM PDT 24
Finished May 19 12:20:04 PM PDT 24
Peak memory 195436 kb
Host smart-b07ffb8f-b33a-41d2-8c17-7705b663ba0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340769749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3340769749
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1232448905
Short name T262
Test name
Test status
Simulation time 14995896 ps
CPU time 0.66 seconds
Started May 19 12:19:32 PM PDT 24
Finished May 19 12:19:33 PM PDT 24
Peak memory 194544 kb
Host smart-aa5710e2-9b8d-4e12-861a-d0882b407b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232448905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1232448905
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3258411000
Short name T68
Test name
Test status
Simulation time 46413620 ps
CPU time 0.78 seconds
Started May 19 12:20:54 PM PDT 24
Finished May 19 12:20:55 PM PDT 24
Peak memory 196028 kb
Host smart-11a80ace-d516-46ea-9575-7fd68ae099b7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258411000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3258411000
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3406102513
Short name T300
Test name
Test status
Simulation time 375749340 ps
CPU time 4.41 seconds
Started May 19 12:19:19 PM PDT 24
Finished May 19 12:19:24 PM PDT 24
Peak memory 197796 kb
Host smart-c157ebc2-7f23-4629-baa1-4e5d3459b023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406102513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3406102513
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3650022426
Short name T34
Test name
Test status
Simulation time 61273044 ps
CPU time 0.92 seconds
Started May 19 12:21:16 PM PDT 24
Finished May 19 12:21:17 PM PDT 24
Peak memory 213536 kb
Host smart-a19404c5-0487-42bd-a6c7-2c782941d3e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650022426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3650022426
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2813392704
Short name T545
Test name
Test status
Simulation time 108794836 ps
CPU time 0.92 seconds
Started May 19 12:20:35 PM PDT 24
Finished May 19 12:20:39 PM PDT 24
Peak memory 196424 kb
Host smart-3fb52c33-9923-4e87-ae77-529083ad1e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813392704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2813392704
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2928756081
Short name T441
Test name
Test status
Simulation time 56440259 ps
CPU time 1.24 seconds
Started May 19 12:21:39 PM PDT 24
Finished May 19 12:21:41 PM PDT 24
Peak memory 195640 kb
Host smart-577874c9-a00d-4cc5-900b-e52d92eeb016
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928756081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2928756081
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3389648614
Short name T623
Test name
Test status
Simulation time 8209700236 ps
CPU time 81.08 seconds
Started May 19 12:21:50 PM PDT 24
Finished May 19 12:23:13 PM PDT 24
Peak memory 197908 kb
Host smart-31ea4777-be7b-4e47-bb1c-dd2ee313be75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389648614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3389648614
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.866406985
Short name T464
Test name
Test status
Simulation time 23255533 ps
CPU time 0.54 seconds
Started May 19 12:24:08 PM PDT 24
Finished May 19 12:24:17 PM PDT 24
Peak memory 194216 kb
Host smart-93345280-9a5f-44ef-b32b-42b33ffb6ed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866406985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.866406985
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4012105774
Short name T163
Test name
Test status
Simulation time 245043079 ps
CPU time 0.84 seconds
Started May 19 12:24:07 PM PDT 24
Finished May 19 12:24:16 PM PDT 24
Peak memory 195936 kb
Host smart-e42fba78-a01a-4305-b279-da0f1f3e892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012105774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4012105774
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.1654060078
Short name T361
Test name
Test status
Simulation time 3261944738 ps
CPU time 16.54 seconds
Started May 19 12:24:00 PM PDT 24
Finished May 19 12:24:24 PM PDT 24
Peak memory 195572 kb
Host smart-dbf79014-9109-40ab-9fb8-bc0a4bb772f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654060078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.1654060078
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3673542421
Short name T417
Test name
Test status
Simulation time 379375489 ps
CPU time 1.09 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:19 PM PDT 24
Peak memory 197524 kb
Host smart-c13363a2-555f-4c08-884c-aa5b6024a694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673542421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3673542421
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.1874639410
Short name T522
Test name
Test status
Simulation time 73015830 ps
CPU time 1.12 seconds
Started May 19 12:24:03 PM PDT 24
Finished May 19 12:24:11 PM PDT 24
Peak memory 196144 kb
Host smart-e292d0b7-f499-4056-aa93-fa5db70669c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874639410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.1874639410
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.587573725
Short name T237
Test name
Test status
Simulation time 486291528 ps
CPU time 2.75 seconds
Started May 19 12:24:01 PM PDT 24
Finished May 19 12:24:11 PM PDT 24
Peak memory 196424 kb
Host smart-582b9475-b6d9-402a-ab61-933d93dfb0fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587573725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
587573725
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3042825249
Short name T235
Test name
Test status
Simulation time 46276324 ps
CPU time 1.02 seconds
Started May 19 12:24:07 PM PDT 24
Finished May 19 12:24:16 PM PDT 24
Peak memory 195808 kb
Host smart-ebd75575-1b9d-4a6c-8853-d5d916aa3ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042825249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3042825249
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1616770161
Short name T202
Test name
Test status
Simulation time 74375221 ps
CPU time 1.21 seconds
Started May 19 12:23:59 PM PDT 24
Finished May 19 12:24:09 PM PDT 24
Peak memory 196864 kb
Host smart-90aa18c6-b3a5-4524-891e-4072c803ba9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616770161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1616770161
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.759104644
Short name T264
Test name
Test status
Simulation time 1372552428 ps
CPU time 6.34 seconds
Started May 19 12:24:03 PM PDT 24
Finished May 19 12:24:17 PM PDT 24
Peak memory 197180 kb
Host smart-70702ac1-f36e-4973-8212-92b4f81dfd94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759104644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.759104644
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3483656112
Short name T250
Test name
Test status
Simulation time 64616756 ps
CPU time 1.08 seconds
Started May 19 12:24:08 PM PDT 24
Finished May 19 12:24:17 PM PDT 24
Peak memory 195680 kb
Host smart-4f5110f4-d639-4a48-9b32-f4c4e36ca4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483656112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3483656112
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3659255832
Short name T524
Test name
Test status
Simulation time 161331397 ps
CPU time 1.03 seconds
Started May 19 12:24:03 PM PDT 24
Finished May 19 12:24:11 PM PDT 24
Peak memory 196008 kb
Host smart-b3127912-0c24-437a-ab2e-304b155109b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659255832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3659255832
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1328983362
Short name T598
Test name
Test status
Simulation time 3527908951 ps
CPU time 46.79 seconds
Started May 19 12:24:07 PM PDT 24
Finished May 19 12:25:01 PM PDT 24
Peak memory 198012 kb
Host smart-0f49936c-f8b8-4210-9e54-829c552e2cbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328983362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1328983362
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2622929557
Short name T594
Test name
Test status
Simulation time 399441897137 ps
CPU time 2315 seconds
Started May 19 12:24:08 PM PDT 24
Finished May 19 01:02:51 PM PDT 24
Peak memory 198056 kb
Host smart-32bd4a76-62ee-4028-8bda-db1688484544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2622929557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2622929557
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.840697918
Short name T363
Test name
Test status
Simulation time 35366506 ps
CPU time 0.62 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 192824 kb
Host smart-c5eb0ff1-d7c4-4947-9ca2-e56aea3f8887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840697918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.840697918
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.4143813882
Short name T109
Test name
Test status
Simulation time 18878426 ps
CPU time 0.65 seconds
Started May 19 12:24:07 PM PDT 24
Finished May 19 12:24:15 PM PDT 24
Peak memory 193808 kb
Host smart-79db2493-cb0d-476f-92aa-df73006ef05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143813882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.4143813882
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2984675610
Short name T427
Test name
Test status
Simulation time 2188939805 ps
CPU time 21.86 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 196796 kb
Host smart-f8770667-82aa-4d5b-9671-1708c0ff81b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984675610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2984675610
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1758916588
Short name T190
Test name
Test status
Simulation time 276018043 ps
CPU time 0.61 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:19 PM PDT 24
Peak memory 194172 kb
Host smart-8e520c5a-b909-4303-a626-a94f63a7a106
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758916588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1758916588
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2647420926
Short name T152
Test name
Test status
Simulation time 175737873 ps
CPU time 0.96 seconds
Started May 19 12:25:44 PM PDT 24
Finished May 19 12:25:46 PM PDT 24
Peak memory 195832 kb
Host smart-07f68ea3-22d4-4f9a-9e3d-5ec8ac933890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647420926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2647420926
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3723249615
Short name T607
Test name
Test status
Simulation time 84118358 ps
CPU time 3.06 seconds
Started May 19 12:24:04 PM PDT 24
Finished May 19 12:24:14 PM PDT 24
Peak memory 197904 kb
Host smart-a7ea1288-2111-47a6-99c6-f34a5ac32c46
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723249615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3723249615
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.299543660
Short name T348
Test name
Test status
Simulation time 56010258 ps
CPU time 1.09 seconds
Started May 19 12:24:08 PM PDT 24
Finished May 19 12:24:18 PM PDT 24
Peak memory 195628 kb
Host smart-90542e21-963c-42fe-b03a-7bfc0e882691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299543660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
299543660
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2265067
Short name T595
Test name
Test status
Simulation time 18755836 ps
CPU time 0.78 seconds
Started May 19 12:24:08 PM PDT 24
Finished May 19 12:24:17 PM PDT 24
Peak memory 196484 kb
Host smart-7ea60dbc-ac5a-41eb-90a5-0036ea97ea86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2265067
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3873206561
Short name T271
Test name
Test status
Simulation time 38944385 ps
CPU time 0.79 seconds
Started May 19 12:24:14 PM PDT 24
Finished May 19 12:24:23 PM PDT 24
Peak memory 196456 kb
Host smart-13289501-6e07-4bd4-b5a7-738f1c8f96de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873206561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3873206561
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.395091968
Short name T279
Test name
Test status
Simulation time 576506293 ps
CPU time 6.41 seconds
Started May 19 12:24:15 PM PDT 24
Finished May 19 12:24:30 PM PDT 24
Peak memory 197840 kb
Host smart-85471a51-588d-4e5d-be28-ed1eb42806fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395091968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.395091968
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.4199736760
Short name T496
Test name
Test status
Simulation time 1052510554 ps
CPU time 1.27 seconds
Started May 19 12:25:30 PM PDT 24
Finished May 19 12:25:33 PM PDT 24
Peak memory 196928 kb
Host smart-b9eea6c0-8401-4e45-b520-bf79e5dfc902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199736760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.4199736760
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1448076692
Short name T383
Test name
Test status
Simulation time 34639806 ps
CPU time 0.79 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:19 PM PDT 24
Peak memory 195116 kb
Host smart-6b114fed-e2ce-4ced-9222-384a6d28dfbf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448076692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1448076692
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1174188383
Short name T687
Test name
Test status
Simulation time 35757693136 ps
CPU time 82.67 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:25:41 PM PDT 24
Peak memory 197984 kb
Host smart-813d90e8-90d7-4f0b-8b76-5c36754a38d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174188383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1174188383
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4196870224
Short name T173
Test name
Test status
Simulation time 12590884 ps
CPU time 0.63 seconds
Started May 19 12:24:08 PM PDT 24
Finished May 19 12:24:16 PM PDT 24
Peak memory 193704 kb
Host smart-5b174799-7d9d-46d2-a16a-956c53396fff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196870224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4196870224
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.924756785
Short name T310
Test name
Test status
Simulation time 79543311 ps
CPU time 0.67 seconds
Started May 19 12:24:07 PM PDT 24
Finished May 19 12:24:16 PM PDT 24
Peak memory 193984 kb
Host smart-69ee8fed-8a55-424a-bf85-f986353ae42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924756785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.924756785
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3543776341
Short name T214
Test name
Test status
Simulation time 1196692221 ps
CPU time 10.53 seconds
Started May 19 12:24:03 PM PDT 24
Finished May 19 12:24:21 PM PDT 24
Peak memory 196284 kb
Host smart-e47d54a2-93db-4617-ba7c-638ebc9832f6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543776341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3543776341
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3542508913
Short name T517
Test name
Test status
Simulation time 73466822 ps
CPU time 0.76 seconds
Started May 19 12:24:14 PM PDT 24
Finished May 19 12:24:23 PM PDT 24
Peak memory 195636 kb
Host smart-dfb14f9f-2730-49af-acf9-dfe33fbcf25d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542508913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3542508913
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1480257691
Short name T557
Test name
Test status
Simulation time 386058493 ps
CPU time 1.54 seconds
Started May 19 12:24:06 PM PDT 24
Finished May 19 12:24:15 PM PDT 24
Peak memory 196512 kb
Host smart-d66a7aa9-14b0-48ce-b54c-bd8f109a67a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480257691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1480257691
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.2820222687
Short name T519
Test name
Test status
Simulation time 54998372 ps
CPU time 2.22 seconds
Started May 19 12:24:04 PM PDT 24
Finished May 19 12:24:15 PM PDT 24
Peak memory 198236 kb
Host smart-7c314b8f-8119-4c26-8dc3-8620cec0f145
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820222687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.2820222687
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2241484208
Short name T191
Test name
Test status
Simulation time 217722291 ps
CPU time 2.11 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:15 PM PDT 24
Peak memory 196108 kb
Host smart-7703acea-77d0-4696-a44d-04c6dfb38b9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241484208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2241484208
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1973225674
Short name T717
Test name
Test status
Simulation time 297835534 ps
CPU time 0.91 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:19 PM PDT 24
Peak memory 195728 kb
Host smart-fda72ee7-b239-418d-87cd-a50e7ae9af17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973225674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1973225674
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3480020574
Short name T565
Test name
Test status
Simulation time 95467236 ps
CPU time 0.83 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:19 PM PDT 24
Peak memory 195976 kb
Host smart-e3300704-a77d-44c4-adfb-63b5b4e050a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480020574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3480020574
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.150305976
Short name T69
Test name
Test status
Simulation time 1671477419 ps
CPU time 5.19 seconds
Started May 19 12:25:30 PM PDT 24
Finished May 19 12:25:37 PM PDT 24
Peak memory 197740 kb
Host smart-af126979-df23-474f-b408-91b9f6863dae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150305976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.150305976
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.74648854
Short name T360
Test name
Test status
Simulation time 340521875 ps
CPU time 0.98 seconds
Started May 19 12:24:05 PM PDT 24
Finished May 19 12:24:14 PM PDT 24
Peak memory 196272 kb
Host smart-ea948124-3b83-458d-952d-b45ae7e3c742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74648854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.74648854
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3847805336
Short name T217
Test name
Test status
Simulation time 132108960 ps
CPU time 1.05 seconds
Started May 19 12:24:06 PM PDT 24
Finished May 19 12:24:15 PM PDT 24
Peak memory 195548 kb
Host smart-a15fac0d-958e-442b-af6c-8030b755ed55
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847805336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3847805336
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2650038999
Short name T222
Test name
Test status
Simulation time 7610668302 ps
CPU time 138.85 seconds
Started May 19 12:24:14 PM PDT 24
Finished May 19 12:26:42 PM PDT 24
Peak memory 197960 kb
Host smart-24f497f8-83cc-4130-b60a-43fc5b99f21f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650038999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2650038999
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1150789541
Short name T16
Test name
Test status
Simulation time 13828330 ps
CPU time 0.56 seconds
Started May 19 12:24:14 PM PDT 24
Finished May 19 12:24:24 PM PDT 24
Peak memory 194436 kb
Host smart-679ad885-c6cf-41da-a997-378de13e2511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150789541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1150789541
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.105089376
Short name T662
Test name
Test status
Simulation time 114747275 ps
CPU time 0.8 seconds
Started May 19 12:24:15 PM PDT 24
Finished May 19 12:24:24 PM PDT 24
Peak memory 196184 kb
Host smart-64cf2d8f-e012-45e9-b0a6-8fdc0c647da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105089376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.105089376
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.463766902
Short name T162
Test name
Test status
Simulation time 2172225195 ps
CPU time 10.46 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:29 PM PDT 24
Peak memory 196732 kb
Host smart-bc417be5-d4ed-4866-bfd5-c3ef32131235
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463766902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.463766902
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3217248345
Short name T198
Test name
Test status
Simulation time 174528906 ps
CPU time 0.75 seconds
Started May 19 12:24:15 PM PDT 24
Finished May 19 12:24:24 PM PDT 24
Peak memory 195868 kb
Host smart-71717372-1bc0-4923-803a-4fc4bdd4cdff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217248345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3217248345
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2868505613
Short name T491
Test name
Test status
Simulation time 390315197 ps
CPU time 1.28 seconds
Started May 19 12:24:14 PM PDT 24
Finished May 19 12:24:24 PM PDT 24
Peak memory 197004 kb
Host smart-a032498d-f342-498c-a7d0-73b3e54e6682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868505613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2868505613
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3941198526
Short name T307
Test name
Test status
Simulation time 324818326 ps
CPU time 3.37 seconds
Started May 19 12:24:15 PM PDT 24
Finished May 19 12:24:27 PM PDT 24
Peak memory 197936 kb
Host smart-810dbe51-b17c-45fe-be1e-baad47764166
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941198526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3941198526
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.409999547
Short name T143
Test name
Test status
Simulation time 298103393 ps
CPU time 2.55 seconds
Started May 19 12:24:13 PM PDT 24
Finished May 19 12:24:23 PM PDT 24
Peak memory 196864 kb
Host smart-0386ac6b-56cc-475d-9bbd-d2f3e35f5c55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409999547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
409999547
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3779263468
Short name T466
Test name
Test status
Simulation time 28227461 ps
CPU time 0.78 seconds
Started May 19 12:24:12 PM PDT 24
Finished May 19 12:24:21 PM PDT 24
Peak memory 195308 kb
Host smart-a9a46429-2869-4e67-b0f1-c65d11a9a2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779263468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3779263468
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2003457432
Short name T113
Test name
Test status
Simulation time 23165424 ps
CPU time 0.89 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:19 PM PDT 24
Peak memory 195876 kb
Host smart-f814b8db-bf38-4826-8eef-0441829993b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003457432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2003457432
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3415841660
Short name T240
Test name
Test status
Simulation time 765094892 ps
CPU time 4.48 seconds
Started May 19 12:24:15 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 197772 kb
Host smart-f4a05c5b-5021-4a15-b249-bc363a078773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415841660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3415841660
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3972610322
Short name T154
Test name
Test status
Simulation time 187428644 ps
CPU time 1.02 seconds
Started May 19 12:24:05 PM PDT 24
Finished May 19 12:24:14 PM PDT 24
Peak memory 195580 kb
Host smart-e2b92ec5-3ac2-4bd1-9e7c-6c5b52f5b324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972610322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3972610322
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.1929146047
Short name T232
Test name
Test status
Simulation time 60914118 ps
CPU time 1.17 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:19 PM PDT 24
Peak memory 195504 kb
Host smart-5d058af5-db91-4b6a-b90e-dbe8dbbd7e94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929146047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.1929146047
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1960019663
Short name T5
Test name
Test status
Simulation time 3396519782 ps
CPU time 36.13 seconds
Started May 19 12:24:13 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 198436 kb
Host smart-c9a3d856-9471-44d8-8480-d7bbda07be67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960019663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1960019663
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2338992221
Short name T207
Test name
Test status
Simulation time 35082092 ps
CPU time 0.55 seconds
Started May 19 12:24:14 PM PDT 24
Finished May 19 12:24:23 PM PDT 24
Peak memory 193688 kb
Host smart-6068392f-ded4-42cb-91e3-b6aef807a9dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338992221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2338992221
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1124008643
Short name T129
Test name
Test status
Simulation time 144507783 ps
CPU time 0.82 seconds
Started May 19 12:24:14 PM PDT 24
Finished May 19 12:24:24 PM PDT 24
Peak memory 197088 kb
Host smart-660489b8-5013-46dd-92eb-e3c536cf5a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124008643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1124008643
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3767108199
Short name T586
Test name
Test status
Simulation time 124231391 ps
CPU time 5.96 seconds
Started May 19 12:24:15 PM PDT 24
Finished May 19 12:24:29 PM PDT 24
Peak memory 196096 kb
Host smart-cf5436d4-7dd2-4cc3-8c45-0fedee9a344a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767108199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3767108199
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1980813275
Short name T650
Test name
Test status
Simulation time 234816535 ps
CPU time 0.8 seconds
Started May 19 12:24:13 PM PDT 24
Finished May 19 12:24:21 PM PDT 24
Peak memory 195728 kb
Host smart-96c371d3-3084-4b4b-ab3c-d85141a991aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980813275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1980813275
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3447026143
Short name T219
Test name
Test status
Simulation time 71982515 ps
CPU time 1.15 seconds
Started May 19 12:24:12 PM PDT 24
Finished May 19 12:24:21 PM PDT 24
Peak memory 196312 kb
Host smart-c5f1fa2f-62d2-4c61-b9b1-2ad83a62a6be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447026143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3447026143
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2953398580
Short name T444
Test name
Test status
Simulation time 42175938 ps
CPU time 1.1 seconds
Started May 19 12:24:13 PM PDT 24
Finished May 19 12:24:22 PM PDT 24
Peak memory 196632 kb
Host smart-4366f29f-1e50-4a6e-a8f2-04387f7eb67b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953398580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2953398580
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3996951237
Short name T589
Test name
Test status
Simulation time 1602691033 ps
CPU time 2.48 seconds
Started May 19 12:24:14 PM PDT 24
Finished May 19 12:24:25 PM PDT 24
Peak memory 197880 kb
Host smart-4f9aa0d3-9997-4bc7-a162-3fd137e20afd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996951237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3996951237
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.986743454
Short name T593
Test name
Test status
Simulation time 332178451 ps
CPU time 1 seconds
Started May 19 12:24:14 PM PDT 24
Finished May 19 12:24:24 PM PDT 24
Peak memory 195836 kb
Host smart-964e1009-f50e-4192-bf76-ba0f3335d90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986743454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.986743454
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.948222589
Short name T514
Test name
Test status
Simulation time 113400374 ps
CPU time 1.22 seconds
Started May 19 12:24:11 PM PDT 24
Finished May 19 12:24:21 PM PDT 24
Peak memory 196516 kb
Host smart-550f4687-54e1-422d-bd78-7bbee3d3e9c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948222589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.948222589
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.405233052
Short name T144
Test name
Test status
Simulation time 446698186 ps
CPU time 4.72 seconds
Started May 19 12:24:11 PM PDT 24
Finished May 19 12:24:24 PM PDT 24
Peak memory 197768 kb
Host smart-013e8827-155f-4c5c-a848-1179cef3cee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405233052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.405233052
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3221003067
Short name T478
Test name
Test status
Simulation time 356234093 ps
CPU time 1.39 seconds
Started May 19 12:24:12 PM PDT 24
Finished May 19 12:24:22 PM PDT 24
Peak memory 196724 kb
Host smart-b33810c8-b335-4f3c-a1fa-24b9613038ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221003067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3221003067
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1783089747
Short name T118
Test name
Test status
Simulation time 198280253 ps
CPU time 1.09 seconds
Started May 19 12:24:10 PM PDT 24
Finished May 19 12:24:19 PM PDT 24
Peak memory 195648 kb
Host smart-46a568cc-9fb0-4d2a-9b1e-edfbb62e9e8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783089747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1783089747
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1647325425
Short name T551
Test name
Test status
Simulation time 26362108014 ps
CPU time 68.84 seconds
Started May 19 12:24:15 PM PDT 24
Finished May 19 12:25:32 PM PDT 24
Peak memory 198008 kb
Host smart-86f7a5de-1f7b-4b5c-b69e-6078200d490e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647325425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1647325425
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.4101864634
Short name T56
Test name
Test status
Simulation time 174074244689 ps
CPU time 1059.11 seconds
Started May 19 12:24:16 PM PDT 24
Finished May 19 12:42:03 PM PDT 24
Peak memory 197980 kb
Host smart-a90ecdd2-9969-47f9-bc7f-6bc6e57c020f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4101864634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.4101864634
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3754332992
Short name T231
Test name
Test status
Simulation time 54002589 ps
CPU time 0.56 seconds
Started May 19 12:24:22 PM PDT 24
Finished May 19 12:24:31 PM PDT 24
Peak memory 193704 kb
Host smart-2575495f-7368-45ae-922b-e5940823b7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754332992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3754332992
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2054548390
Short name T208
Test name
Test status
Simulation time 23830595 ps
CPU time 0.79 seconds
Started May 19 12:24:17 PM PDT 24
Finished May 19 12:24:26 PM PDT 24
Peak memory 195168 kb
Host smart-c873c030-5b6e-4c2a-b881-c97278af830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054548390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2054548390
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3403423391
Short name T179
Test name
Test status
Simulation time 787920918 ps
CPU time 5.57 seconds
Started May 19 12:24:23 PM PDT 24
Finished May 19 12:24:36 PM PDT 24
Peak memory 196388 kb
Host smart-dc065bcb-32ac-4f23-a75e-069074e893f3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403423391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3403423391
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4034948939
Short name T189
Test name
Test status
Simulation time 94403340 ps
CPU time 0.93 seconds
Started May 19 12:24:19 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 197028 kb
Host smart-298df1ff-61b5-4cdc-823d-036d1e002336
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034948939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4034948939
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1035375031
Short name T716
Test name
Test status
Simulation time 72154670 ps
CPU time 1.24 seconds
Started May 19 12:24:18 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 196464 kb
Host smart-74b6cbd6-d98d-4cd0-a7d4-6ed0cb45c88e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035375031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1035375031
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1359334152
Short name T458
Test name
Test status
Simulation time 62446176 ps
CPU time 1.38 seconds
Started May 19 12:24:21 PM PDT 24
Finished May 19 12:24:31 PM PDT 24
Peak memory 195920 kb
Host smart-385c3430-5925-4e59-90c5-ddac45b994ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359334152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1359334152
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1053317541
Short name T64
Test name
Test status
Simulation time 31098429 ps
CPU time 0.92 seconds
Started May 19 12:25:18 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 195288 kb
Host smart-7e226b37-756a-48db-bf6b-d1e3cfaf9531
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053317541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1053317541
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.517177365
Short name T653
Test name
Test status
Simulation time 154025324 ps
CPU time 0.73 seconds
Started May 19 12:24:18 PM PDT 24
Finished May 19 12:24:27 PM PDT 24
Peak memory 195376 kb
Host smart-55eb2e23-6661-4426-990d-28c80b828450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517177365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.517177365
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1201675104
Short name T196
Test name
Test status
Simulation time 40842747 ps
CPU time 0.84 seconds
Started May 19 12:24:19 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 195700 kb
Host smart-00b32fdc-6055-4d2e-82a0-580d94751abe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201675104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1201675104
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2125335731
Short name T376
Test name
Test status
Simulation time 244049975 ps
CPU time 2.8 seconds
Started May 19 12:24:25 PM PDT 24
Finished May 19 12:24:35 PM PDT 24
Peak memory 197792 kb
Host smart-52a1fc72-6232-47f1-9e6d-812ebe3d7e0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125335731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2125335731
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.210719193
Short name T149
Test name
Test status
Simulation time 172980902 ps
CPU time 0.9 seconds
Started May 19 12:24:12 PM PDT 24
Finished May 19 12:24:21 PM PDT 24
Peak memory 196784 kb
Host smart-d58562e3-fd0a-44a6-b35b-7446f6bdb518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210719193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.210719193
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.969685354
Short name T636
Test name
Test status
Simulation time 311767481 ps
CPU time 1.11 seconds
Started May 19 12:24:17 PM PDT 24
Finished May 19 12:24:27 PM PDT 24
Peak memory 195388 kb
Host smart-cedd5a00-f5a1-4790-ab1a-37e16c0c6a93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969685354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.969685354
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.684129459
Short name T23
Test name
Test status
Simulation time 18353167450 ps
CPU time 103.41 seconds
Started May 19 12:24:15 PM PDT 24
Finished May 19 12:26:07 PM PDT 24
Peak memory 197956 kb
Host smart-08f15a3b-4d09-4eff-9751-e75a9197c117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684129459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.684129459
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2616119239
Short name T686
Test name
Test status
Simulation time 14438879 ps
CPU time 0.55 seconds
Started May 19 12:25:21 PM PDT 24
Finished May 19 12:25:27 PM PDT 24
Peak memory 193944 kb
Host smart-7c04da7e-ca41-4015-9ab0-4e16ea9731a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616119239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2616119239
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1122242024
Short name T347
Test name
Test status
Simulation time 199420017 ps
CPU time 0.92 seconds
Started May 19 12:25:21 PM PDT 24
Finished May 19 12:25:27 PM PDT 24
Peak memory 195544 kb
Host smart-626b2ed5-32e7-4321-b90a-e62599c225c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122242024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1122242024
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1635361604
Short name T488
Test name
Test status
Simulation time 3093137605 ps
CPU time 17.66 seconds
Started May 19 12:24:16 PM PDT 24
Finished May 19 12:24:42 PM PDT 24
Peak memory 196596 kb
Host smart-c654f3fa-80fa-4d2f-8fb8-ce154960531b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635361604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1635361604
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1682916710
Short name T218
Test name
Test status
Simulation time 63776991 ps
CPU time 0.66 seconds
Started May 19 12:24:17 PM PDT 24
Finished May 19 12:24:26 PM PDT 24
Peak memory 194068 kb
Host smart-ffd3704a-bb35-44fe-8e20-6ae98d04f0c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682916710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1682916710
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3177457372
Short name T703
Test name
Test status
Simulation time 1849856102 ps
CPU time 1.37 seconds
Started May 19 12:24:19 PM PDT 24
Finished May 19 12:24:29 PM PDT 24
Peak memory 195672 kb
Host smart-e813407d-ce10-41b9-b528-dbbb6d1bf56e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177457372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3177457372
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.2037838459
Short name T540
Test name
Test status
Simulation time 83549258 ps
CPU time 0.95 seconds
Started May 19 12:24:23 PM PDT 24
Finished May 19 12:24:32 PM PDT 24
Peak memory 196324 kb
Host smart-c1b2e6c3-a037-41d2-806f-94d6bfd705fa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037838459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.2037838459
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.1649365039
Short name T138
Test name
Test status
Simulation time 397629645 ps
CPU time 1.55 seconds
Started May 19 12:24:26 PM PDT 24
Finished May 19 12:24:35 PM PDT 24
Peak memory 195592 kb
Host smart-7d369da4-a15a-454b-81e3-7d185ea7c26c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649365039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.1649365039
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2641675776
Short name T592
Test name
Test status
Simulation time 29014495 ps
CPU time 1.12 seconds
Started May 19 12:24:20 PM PDT 24
Finished May 19 12:24:30 PM PDT 24
Peak memory 195800 kb
Host smart-8cfb2737-9b42-41ba-b1e8-3da9ae8eb7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641675776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2641675776
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1083523059
Short name T158
Test name
Test status
Simulation time 58234843 ps
CPU time 1.5 seconds
Started May 19 12:24:22 PM PDT 24
Finished May 19 12:24:32 PM PDT 24
Peak memory 198344 kb
Host smart-7fe51a7c-d26d-405d-9d6e-ab3730159a86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083523059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1083523059
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1209336364
Short name T579
Test name
Test status
Simulation time 336019070 ps
CPU time 4.28 seconds
Started May 19 12:25:26 PM PDT 24
Finished May 19 12:25:33 PM PDT 24
Peak memory 197816 kb
Host smart-d8e08258-d08d-4c47-92dc-9381dfe7762a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209336364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1209336364
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3968463243
Short name T292
Test name
Test status
Simulation time 69323938 ps
CPU time 0.97 seconds
Started May 19 12:24:20 PM PDT 24
Finished May 19 12:24:30 PM PDT 24
Peak memory 195340 kb
Host smart-4471d233-5d68-48ba-b6d7-ea371dd409a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968463243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3968463243
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.600289420
Short name T558
Test name
Test status
Simulation time 191316729 ps
CPU time 0.91 seconds
Started May 19 12:24:19 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 196136 kb
Host smart-f96dadb9-42d4-4f08-bfa2-49d723739463
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600289420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.600289420
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3648817840
Short name T390
Test name
Test status
Simulation time 1642567269 ps
CPU time 17.47 seconds
Started May 19 12:24:17 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 197816 kb
Host smart-15cb36e3-facf-4e1d-b0bc-3cbbaf381f2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648817840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3648817840
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3129413890
Short name T22
Test name
Test status
Simulation time 122811127 ps
CPU time 0.57 seconds
Started May 19 12:24:18 PM PDT 24
Finished May 19 12:24:27 PM PDT 24
Peak memory 193672 kb
Host smart-4f04b6c5-e798-48c3-92c0-00581bc43085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129413890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3129413890
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3791905916
Short name T48
Test name
Test status
Simulation time 82152393 ps
CPU time 0.85 seconds
Started May 19 12:24:19 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 196132 kb
Host smart-4396f3c4-605a-446f-a38f-92707ee7865b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791905916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3791905916
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3530731379
Short name T331
Test name
Test status
Simulation time 736610985 ps
CPU time 10.75 seconds
Started May 19 12:24:20 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 195268 kb
Host smart-a8232d77-0b96-47e4-b118-37b5292386c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530731379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3530731379
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1712018295
Short name T8
Test name
Test status
Simulation time 234243813 ps
CPU time 0.79 seconds
Started May 19 12:24:21 PM PDT 24
Finished May 19 12:24:30 PM PDT 24
Peak memory 195648 kb
Host smart-18ead53b-a626-44fb-9a7e-6950dbf3841a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712018295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1712018295
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1262424623
Short name T505
Test name
Test status
Simulation time 60719864 ps
CPU time 0.68 seconds
Started May 19 12:24:19 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 194220 kb
Host smart-fd195e21-54e4-4acc-a116-e3063be6952b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262424623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1262424623
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2814921794
Short name T389
Test name
Test status
Simulation time 63889332 ps
CPU time 2.37 seconds
Started May 19 12:24:18 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 197836 kb
Host smart-3125212f-e74a-47ee-aa71-c8deef6b8080
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814921794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2814921794
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2731515601
Short name T644
Test name
Test status
Simulation time 62544962 ps
CPU time 1.91 seconds
Started May 19 12:24:22 PM PDT 24
Finished May 19 12:24:32 PM PDT 24
Peak memory 196732 kb
Host smart-51f1a347-1d99-4efd-925c-e9d09d941c12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731515601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2731515601
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.3615110825
Short name T709
Test name
Test status
Simulation time 173549987 ps
CPU time 1.22 seconds
Started May 19 12:24:21 PM PDT 24
Finished May 19 12:24:31 PM PDT 24
Peak memory 197264 kb
Host smart-70ec409b-da27-49dc-9e57-8127d974fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615110825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.3615110825
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3091861518
Short name T613
Test name
Test status
Simulation time 121713131 ps
CPU time 1.13 seconds
Started May 19 12:24:23 PM PDT 24
Finished May 19 12:24:32 PM PDT 24
Peak memory 196720 kb
Host smart-37c1eb9e-8641-4d41-8115-71ee3d9b0b42
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091861518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3091861518
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1446513031
Short name T274
Test name
Test status
Simulation time 1478810074 ps
CPU time 4.61 seconds
Started May 19 12:24:19 PM PDT 24
Finished May 19 12:24:32 PM PDT 24
Peak memory 198172 kb
Host smart-d69b2f25-7f5b-4693-afa1-3cb071abbe63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446513031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1446513031
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2556737596
Short name T399
Test name
Test status
Simulation time 31201661 ps
CPU time 0.8 seconds
Started May 19 12:24:19 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 195888 kb
Host smart-c827735d-5c07-4e66-8761-9f6414d6fb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556737596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2556737596
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1131858033
Short name T228
Test name
Test status
Simulation time 255636074 ps
CPU time 1.11 seconds
Started May 19 12:24:20 PM PDT 24
Finished May 19 12:24:30 PM PDT 24
Peak memory 195556 kb
Host smart-7a9d1cf4-814e-43e5-a1a7-5b886ff0f186
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131858033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1131858033
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1579629108
Short name T185
Test name
Test status
Simulation time 26848362122 ps
CPU time 161.02 seconds
Started May 19 12:25:30 PM PDT 24
Finished May 19 12:28:13 PM PDT 24
Peak memory 198032 kb
Host smart-43d62f28-92c0-46f9-ad49-4b0610bedd09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579629108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1579629108
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1047658459
Short name T372
Test name
Test status
Simulation time 15287211 ps
CPU time 0.58 seconds
Started May 19 12:24:29 PM PDT 24
Finished May 19 12:24:38 PM PDT 24
Peak memory 193652 kb
Host smart-9d32d412-411f-471b-a297-fa5cb8237a38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047658459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1047658459
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.723114219
Short name T63
Test name
Test status
Simulation time 56051034 ps
CPU time 0.71 seconds
Started May 19 12:24:22 PM PDT 24
Finished May 19 12:24:31 PM PDT 24
Peak memory 195100 kb
Host smart-f42ce4e5-b3d5-4a64-9edf-be9dc577261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723114219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.723114219
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3137560981
Short name T375
Test name
Test status
Simulation time 175530404 ps
CPU time 9.39 seconds
Started May 19 12:24:22 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 197100 kb
Host smart-59226c03-2752-44b6-9cac-f0c19b555449
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137560981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3137560981
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3884580631
Short name T429
Test name
Test status
Simulation time 328347063 ps
CPU time 0.99 seconds
Started May 19 12:24:23 PM PDT 24
Finished May 19 12:24:31 PM PDT 24
Peak memory 196616 kb
Host smart-643bfa0f-6004-4388-81c6-7d08928ac382
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884580631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3884580631
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.4009249378
Short name T402
Test name
Test status
Simulation time 78070872 ps
CPU time 1.35 seconds
Started May 19 12:24:25 PM PDT 24
Finished May 19 12:24:34 PM PDT 24
Peak memory 197860 kb
Host smart-5f02ca4d-b935-4dd1-89f2-1e5d1fc04abd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009249378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.4009249378
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.543960182
Short name T203
Test name
Test status
Simulation time 336820463 ps
CPU time 3.47 seconds
Started May 19 12:24:23 PM PDT 24
Finished May 19 12:24:34 PM PDT 24
Peak memory 198224 kb
Host smart-efccbb55-f596-4fb7-becd-8f10bbe7e419
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543960182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.543960182
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.4209119974
Short name T448
Test name
Test status
Simulation time 362983863 ps
CPU time 1.53 seconds
Started May 19 12:24:17 PM PDT 24
Finished May 19 12:24:27 PM PDT 24
Peak memory 195844 kb
Host smart-d1a85099-0bb4-4186-8874-caa0a1dd548b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209119974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.4209119974
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.978385373
Short name T287
Test name
Test status
Simulation time 36649017 ps
CPU time 0.74 seconds
Started May 19 12:24:18 PM PDT 24
Finished May 19 12:24:28 PM PDT 24
Peak memory 195320 kb
Host smart-7a4d76f7-9ac9-4c89-80be-9ab4f9b2478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978385373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.978385373
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.606550901
Short name T320
Test name
Test status
Simulation time 54883381 ps
CPU time 1.01 seconds
Started May 19 12:24:23 PM PDT 24
Finished May 19 12:24:32 PM PDT 24
Peak memory 195552 kb
Host smart-fae4d7d7-22e2-4632-833b-e8d5295ed535
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606550901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.606550901
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_smoke.2141384468
Short name T174
Test name
Test status
Simulation time 292925062 ps
CPU time 1.34 seconds
Started May 19 12:24:17 PM PDT 24
Finished May 19 12:24:27 PM PDT 24
Peak memory 196500 kb
Host smart-1d55ee43-3a98-44d9-8d17-a482dd7fc608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141384468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2141384468
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1805266343
Short name T619
Test name
Test status
Simulation time 59626107 ps
CPU time 0.76 seconds
Started May 19 12:24:19 PM PDT 24
Finished May 19 12:24:29 PM PDT 24
Peak memory 194828 kb
Host smart-73428d82-52bc-4033-9cb2-f7684bf824b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805266343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1805266343
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.4172679379
Short name T385
Test name
Test status
Simulation time 8050040242 ps
CPU time 196.59 seconds
Started May 19 12:24:25 PM PDT 24
Finished May 19 12:27:50 PM PDT 24
Peak memory 197980 kb
Host smart-0aa94926-bb4a-46d7-b11c-451cab16586c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172679379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.4172679379
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.1221768945
Short name T57
Test name
Test status
Simulation time 201338915273 ps
CPU time 957.42 seconds
Started May 19 12:24:24 PM PDT 24
Finished May 19 12:40:29 PM PDT 24
Peak memory 198096 kb
Host smart-886c832d-49fd-4752-88a0-1496ce4fb984
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1221768945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.1221768945
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2974961068
Short name T313
Test name
Test status
Simulation time 75575311 ps
CPU time 0.56 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:39 PM PDT 24
Peak memory 194396 kb
Host smart-e77450fb-0fe0-4da6-8543-0280b7681c74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974961068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2974961068
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1453236785
Short name T319
Test name
Test status
Simulation time 24264275 ps
CPU time 0.71 seconds
Started May 19 12:24:27 PM PDT 24
Finished May 19 12:24:36 PM PDT 24
Peak memory 194096 kb
Host smart-f45a153e-dafd-4448-84d6-ad2efaa1f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453236785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1453236785
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.297370096
Short name T556
Test name
Test status
Simulation time 314008931 ps
CPU time 8.15 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:47 PM PDT 24
Peak memory 196648 kb
Host smart-99f87b8b-efa9-499d-a8fe-eea16051007f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297370096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.297370096
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1565428869
Short name T625
Test name
Test status
Simulation time 47913301 ps
CPU time 0.77 seconds
Started May 19 12:24:27 PM PDT 24
Finished May 19 12:24:36 PM PDT 24
Peak memory 196356 kb
Host smart-d3624375-9ac8-442f-9c56-6b68c10a0d48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565428869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1565428869
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1825922200
Short name T668
Test name
Test status
Simulation time 54398003 ps
CPU time 1.01 seconds
Started May 19 12:24:26 PM PDT 24
Finished May 19 12:24:34 PM PDT 24
Peak memory 195864 kb
Host smart-5fa39eda-5b16-4465-a724-379a42b8a31f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825922200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1825922200
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.4163489823
Short name T315
Test name
Test status
Simulation time 44064888 ps
CPU time 1.71 seconds
Started May 19 12:24:29 PM PDT 24
Finished May 19 12:24:38 PM PDT 24
Peak memory 197912 kb
Host smart-db0029fc-b88f-479a-9f45-4298657ae109
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163489823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.4163489823
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.402201408
Short name T546
Test name
Test status
Simulation time 703296995 ps
CPU time 1.79 seconds
Started May 19 12:24:35 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 195864 kb
Host smart-bf033dc6-7422-44ee-b14c-4d8703dfef15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402201408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
402201408
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1336245278
Short name T465
Test name
Test status
Simulation time 22619809 ps
CPU time 0.64 seconds
Started May 19 12:24:29 PM PDT 24
Finished May 19 12:24:38 PM PDT 24
Peak memory 194176 kb
Host smart-283bbe28-c63e-42f4-bd5d-9d57a15c7865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336245278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1336245278
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3289362678
Short name T576
Test name
Test status
Simulation time 65720133 ps
CPU time 1.17 seconds
Started May 19 12:24:28 PM PDT 24
Finished May 19 12:24:37 PM PDT 24
Peak memory 197780 kb
Host smart-10916001-7d62-4f61-85d9-59b69ea14a6a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289362678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3289362678
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2010414032
Short name T393
Test name
Test status
Simulation time 459588425 ps
CPU time 3.77 seconds
Started May 19 12:24:28 PM PDT 24
Finished May 19 12:24:39 PM PDT 24
Peak memory 197872 kb
Host smart-47e52765-9a55-49b0-baa8-a4cfb2e1adb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010414032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2010414032
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.4222450673
Short name T258
Test name
Test status
Simulation time 340552770 ps
CPU time 1.12 seconds
Started May 19 12:24:26 PM PDT 24
Finished May 19 12:24:34 PM PDT 24
Peak memory 195548 kb
Host smart-b5d0d6bc-46eb-4c7d-8b00-e3ad5f2466bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222450673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.4222450673
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.762351520
Short name T580
Test name
Test status
Simulation time 136122675 ps
CPU time 0.94 seconds
Started May 19 12:24:25 PM PDT 24
Finished May 19 12:24:33 PM PDT 24
Peak memory 195532 kb
Host smart-921749b4-b7eb-41d7-92c2-8e4c685dacff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762351520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.762351520
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1439612925
Short name T435
Test name
Test status
Simulation time 2899056496 ps
CPU time 31.22 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:25:11 PM PDT 24
Peak memory 197980 kb
Host smart-bc26dcff-ca43-4dd4-9cb1-cd0f0cc8ed8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439612925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1439612925
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2999827055
Short name T461
Test name
Test status
Simulation time 13464506 ps
CPU time 0.57 seconds
Started May 19 12:23:19 PM PDT 24
Finished May 19 12:23:27 PM PDT 24
Peak memory 193188 kb
Host smart-12c463db-303b-4237-80c1-02ccf9118331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999827055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2999827055
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1553910858
Short name T622
Test name
Test status
Simulation time 24511246 ps
CPU time 0.96 seconds
Started May 19 12:20:22 PM PDT 24
Finished May 19 12:20:25 PM PDT 24
Peak memory 196412 kb
Host smart-bfff9637-7de6-4076-889d-6037e35e05a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553910858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1553910858
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.186405744
Short name T269
Test name
Test status
Simulation time 346155609 ps
CPU time 11.02 seconds
Started May 19 12:21:01 PM PDT 24
Finished May 19 12:21:12 PM PDT 24
Peak memory 197752 kb
Host smart-476de5d9-18bf-447a-b7b6-a4f8bb71fd28
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186405744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.186405744
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.83160741
Short name T188
Test name
Test status
Simulation time 72117171 ps
CPU time 0.9 seconds
Started May 19 12:21:47 PM PDT 24
Finished May 19 12:21:50 PM PDT 24
Peak memory 196364 kb
Host smart-a007e088-5199-4274-9554-9f7f4324d966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83160741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.83160741
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1745888604
Short name T501
Test name
Test status
Simulation time 46463730 ps
CPU time 0.93 seconds
Started May 19 12:19:03 PM PDT 24
Finished May 19 12:19:05 PM PDT 24
Peak memory 197072 kb
Host smart-f4820870-116f-412a-a0c8-c4058e474e50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745888604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1745888604
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1454300752
Short name T504
Test name
Test status
Simulation time 80032547 ps
CPU time 2.83 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:49 PM PDT 24
Peak memory 196012 kb
Host smart-9b4b71e6-e6a7-49ff-a0ed-8986f6c487cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454300752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1454300752
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1221639936
Short name T148
Test name
Test status
Simulation time 2442747631 ps
CPU time 2.7 seconds
Started May 19 12:22:36 PM PDT 24
Finished May 19 12:22:39 PM PDT 24
Peak memory 197032 kb
Host smart-3c05f17d-a948-4394-86c4-2e05513152e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221639936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1221639936
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.989006477
Short name T406
Test name
Test status
Simulation time 106617650 ps
CPU time 0.86 seconds
Started May 19 12:20:48 PM PDT 24
Finished May 19 12:20:50 PM PDT 24
Peak memory 196312 kb
Host smart-2a1c0763-e501-41e5-a8f8-a3fb5af1bc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989006477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.989006477
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3320842029
Short name T498
Test name
Test status
Simulation time 504011535 ps
CPU time 1.04 seconds
Started May 19 12:23:19 PM PDT 24
Finished May 19 12:23:27 PM PDT 24
Peak memory 195576 kb
Host smart-58729bbd-4b0c-41c0-985c-549b12666540
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320842029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3320842029
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.761437562
Short name T566
Test name
Test status
Simulation time 888501707 ps
CPU time 3.71 seconds
Started May 19 12:23:18 PM PDT 24
Finished May 19 12:23:28 PM PDT 24
Peak memory 196452 kb
Host smart-dc1ae0af-dcdc-46a2-ade0-cb165a62feca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761437562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.761437562
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1616729160
Short name T44
Test name
Test status
Simulation time 38566196 ps
CPU time 0.85 seconds
Started May 19 12:18:48 PM PDT 24
Finished May 19 12:18:50 PM PDT 24
Peak memory 214044 kb
Host smart-e177b652-2edf-4990-a53e-244f8050a8e9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616729160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1616729160
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1739767337
Short name T282
Test name
Test status
Simulation time 171048215 ps
CPU time 1.26 seconds
Started May 19 12:18:07 PM PDT 24
Finished May 19 12:18:09 PM PDT 24
Peak memory 197548 kb
Host smart-9c1ce25d-cbd7-4cef-abf6-5e664162dd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739767337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1739767337
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1178619749
Short name T311
Test name
Test status
Simulation time 34721521 ps
CPU time 0.91 seconds
Started May 19 12:22:02 PM PDT 24
Finished May 19 12:22:03 PM PDT 24
Peak memory 195288 kb
Host smart-7ab2f593-6d74-47ff-acb6-594d1b515ffc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178619749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1178619749
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1139490393
Short name T480
Test name
Test status
Simulation time 3961627536 ps
CPU time 44.38 seconds
Started May 19 12:20:50 PM PDT 24
Finished May 19 12:21:36 PM PDT 24
Peak memory 197908 kb
Host smart-ea3ad30f-c4a4-42d3-883a-8360eafbd0f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139490393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1139490393
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3040454324
Short name T147
Test name
Test status
Simulation time 15063826 ps
CPU time 0.57 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 193976 kb
Host smart-2d5199c5-9d82-4d00-a96c-25b5f5103892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040454324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3040454324
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.2644854266
Short name T187
Test name
Test status
Simulation time 422559363 ps
CPU time 0.72 seconds
Started May 19 12:24:26 PM PDT 24
Finished May 19 12:24:34 PM PDT 24
Peak memory 195044 kb
Host smart-b65909d9-48f7-4726-b049-c1c634311d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644854266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.2644854266
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.1329762346
Short name T543
Test name
Test status
Simulation time 1285216989 ps
CPU time 16.49 seconds
Started May 19 12:24:35 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 196672 kb
Host smart-efe11dc3-7b7a-449a-9743-4e7b4bedb576
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329762346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.1329762346
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.401668714
Short name T367
Test name
Test status
Simulation time 103157623 ps
CPU time 0.98 seconds
Started May 19 12:24:27 PM PDT 24
Finished May 19 12:24:36 PM PDT 24
Peak memory 196456 kb
Host smart-cd6859af-8261-4677-9005-d93ab7a7f4d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401668714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.401668714
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.194062531
Short name T337
Test name
Test status
Simulation time 124547434 ps
CPU time 0.79 seconds
Started May 19 12:24:24 PM PDT 24
Finished May 19 12:24:33 PM PDT 24
Peak memory 196616 kb
Host smart-c7851a9a-d338-451d-a85a-1898a029db6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194062531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.194062531
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1289980237
Short name T547
Test name
Test status
Simulation time 41293804 ps
CPU time 1.05 seconds
Started May 19 12:24:35 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 196820 kb
Host smart-85105ef2-75f8-4529-b815-43c5bb52d789
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289980237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1289980237
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2596746020
Short name T114
Test name
Test status
Simulation time 60658652 ps
CPU time 1.31 seconds
Started May 19 12:24:25 PM PDT 24
Finished May 19 12:24:34 PM PDT 24
Peak memory 196516 kb
Host smart-c5932953-9b27-450f-b086-361c29b95db2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596746020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2596746020
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1935200702
Short name T305
Test name
Test status
Simulation time 128116606 ps
CPU time 0.8 seconds
Started May 19 12:24:34 PM PDT 24
Finished May 19 12:24:42 PM PDT 24
Peak memory 196384 kb
Host smart-c56e6789-de52-4f7e-b54d-8a80c57373c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935200702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1935200702
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.4239861884
Short name T451
Test name
Test status
Simulation time 93167180 ps
CPU time 0.65 seconds
Started May 19 12:24:35 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 194204 kb
Host smart-218b524d-4438-4ba3-a858-c26b9c3fd4c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239861884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.4239861884
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2371986546
Short name T204
Test name
Test status
Simulation time 49126849 ps
CPU time 2.42 seconds
Started May 19 12:24:26 PM PDT 24
Finished May 19 12:24:36 PM PDT 24
Peak memory 197840 kb
Host smart-534db70d-4d77-40a0-9b99-01213cbd19a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371986546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2371986546
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1339532513
Short name T714
Test name
Test status
Simulation time 91298327 ps
CPU time 1.41 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 196580 kb
Host smart-d09b31e7-361e-482b-94fe-daa58cc641ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339532513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1339532513
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1925483974
Short name T273
Test name
Test status
Simulation time 151475977 ps
CPU time 0.83 seconds
Started May 19 12:24:34 PM PDT 24
Finished May 19 12:24:42 PM PDT 24
Peak memory 195020 kb
Host smart-d0ca0699-c39c-4e70-8a1a-03a74e889a0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925483974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1925483974
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3586403578
Short name T182
Test name
Test status
Simulation time 21437207011 ps
CPU time 129.35 seconds
Started May 19 12:24:26 PM PDT 24
Finished May 19 12:26:43 PM PDT 24
Peak memory 197972 kb
Host smart-972b687c-bd57-45e1-a548-65c5b78a2fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586403578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3586403578
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1424165238
Short name T29
Test name
Test status
Simulation time 242899259115 ps
CPU time 1871.39 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:55:49 PM PDT 24
Peak memory 198012 kb
Host smart-a6e8d4fe-14e8-4321-91a7-052a3ff9b3c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1424165238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1424165238
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2297668450
Short name T172
Test name
Test status
Simulation time 22130983 ps
CPU time 0.6 seconds
Started May 19 12:24:35 PM PDT 24
Finished May 19 12:24:42 PM PDT 24
Peak memory 194640 kb
Host smart-72fb535d-976e-4794-8f90-7460db5041ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297668450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2297668450
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1503518719
Short name T296
Test name
Test status
Simulation time 99595636 ps
CPU time 0.81 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:39 PM PDT 24
Peak memory 196952 kb
Host smart-b403c089-5f98-4d35-94fb-0412baae7c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503518719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1503518719
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1013858491
Short name T627
Test name
Test status
Simulation time 309448979 ps
CPU time 9.97 seconds
Started May 19 12:24:29 PM PDT 24
Finished May 19 12:24:46 PM PDT 24
Peak memory 196624 kb
Host smart-a009fe8a-bce4-45d3-a374-11817d5618bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013858491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1013858491
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3220653933
Short name T333
Test name
Test status
Simulation time 62096702 ps
CPU time 0.73 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 194564 kb
Host smart-9eb830c4-9f89-491a-81e0-e764fd2f43b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220653933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3220653933
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2165427290
Short name T426
Test name
Test status
Simulation time 33815267 ps
CPU time 1.03 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:39 PM PDT 24
Peak memory 195852 kb
Host smart-84f97281-c3dd-4f63-a5b1-f42f2b9334ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165427290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2165427290
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1447828179
Short name T475
Test name
Test status
Simulation time 246988462 ps
CPU time 2.95 seconds
Started May 19 12:24:33 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 196688 kb
Host smart-bfe23807-3c0c-4e08-b844-68a7e85e223c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447828179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1447828179
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.4243242668
Short name T412
Test name
Test status
Simulation time 130005636 ps
CPU time 3.58 seconds
Started May 19 12:24:26 PM PDT 24
Finished May 19 12:24:37 PM PDT 24
Peak memory 196304 kb
Host smart-62782903-978d-42b9-8d76-2bf2864b8403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243242668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.4243242668
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.304454121
Short name T632
Test name
Test status
Simulation time 44369837 ps
CPU time 0.88 seconds
Started May 19 12:24:29 PM PDT 24
Finished May 19 12:24:38 PM PDT 24
Peak memory 195864 kb
Host smart-7466ece6-bf0f-4087-a64f-e7f9c0fd871e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304454121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.304454121
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.4284349206
Short name T672
Test name
Test status
Simulation time 75480167 ps
CPU time 0.91 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 196432 kb
Host smart-d3af38cc-d084-4ffc-8e08-4e1ba941cd15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284349206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.4284349206
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3931686140
Short name T1
Test name
Test status
Simulation time 1763807959 ps
CPU time 5.74 seconds
Started May 19 12:24:27 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 197804 kb
Host smart-4727ead1-d752-4dc0-b0e7-d07456b46174
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931686140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3931686140
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.1949818649
Short name T661
Test name
Test status
Simulation time 167550864 ps
CPU time 0.99 seconds
Started May 19 12:24:34 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 195324 kb
Host smart-4dd30995-3cd6-47de-bf27-4baf9a6024e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949818649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.1949818649
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2173319541
Short name T621
Test name
Test status
Simulation time 158533630 ps
CPU time 0.95 seconds
Started May 19 12:24:25 PM PDT 24
Finished May 19 12:24:34 PM PDT 24
Peak memory 195540 kb
Host smart-648f3c76-e53f-4da5-85f2-507917a75cb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173319541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2173319541
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2976868795
Short name T52
Test name
Test status
Simulation time 1669803421 ps
CPU time 45.14 seconds
Started May 19 12:24:26 PM PDT 24
Finished May 19 12:25:18 PM PDT 24
Peak memory 197872 kb
Host smart-cfab87f2-68fa-4dfc-8a74-308a8d7f14ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976868795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2976868795
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2386907051
Short name T502
Test name
Test status
Simulation time 13965520 ps
CPU time 0.56 seconds
Started May 19 12:26:12 PM PDT 24
Finished May 19 12:26:13 PM PDT 24
Peak memory 194424 kb
Host smart-beec41ba-0871-41c2-a2bc-81882005d7f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386907051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2386907051
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.3548600670
Short name T454
Test name
Test status
Simulation time 27215977 ps
CPU time 0.72 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:39 PM PDT 24
Peak memory 194080 kb
Host smart-87c7f493-75fe-4434-a61d-6038f220acf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548600670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.3548600670
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1797261806
Short name T293
Test name
Test status
Simulation time 1002046139 ps
CPU time 13.88 seconds
Started May 19 12:24:42 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 195284 kb
Host smart-f8437b04-0137-4f08-80fc-59252bfdec2b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797261806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1797261806
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1829122468
Short name T553
Test name
Test status
Simulation time 109755834 ps
CPU time 1.05 seconds
Started May 19 12:25:43 PM PDT 24
Finished May 19 12:25:45 PM PDT 24
Peak memory 195108 kb
Host smart-0bd584be-8c88-4359-b5a3-2afca7000651
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829122468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1829122468
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2485800915
Short name T697
Test name
Test status
Simulation time 269099905 ps
CPU time 1.08 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 196616 kb
Host smart-b4464218-a44c-4867-af1c-065c56ead5da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485800915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2485800915
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3973902174
Short name T708
Test name
Test status
Simulation time 98762574 ps
CPU time 1.63 seconds
Started May 19 12:24:36 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 196236 kb
Host smart-66277e8e-2970-4a24-8c12-c4553724de15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973902174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3973902174
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3273766238
Short name T175
Test name
Test status
Simulation time 50020455 ps
CPU time 0.95 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 195516 kb
Host smart-f5859a1c-7305-405c-81e0-950056c55cfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273766238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3273766238
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2283313846
Short name T51
Test name
Test status
Simulation time 148033391 ps
CPU time 1.27 seconds
Started May 19 12:24:38 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 195628 kb
Host smart-c3063c48-396e-4f5e-807b-051a29930a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283313846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2283313846
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1294174188
Short name T509
Test name
Test status
Simulation time 457052964 ps
CPU time 0.95 seconds
Started May 19 12:24:39 PM PDT 24
Finished May 19 12:24:46 PM PDT 24
Peak memory 195940 kb
Host smart-012e3f0c-e8ce-439a-aab2-97d2b776e641
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294174188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1294174188
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2575269378
Short name T21
Test name
Test status
Simulation time 185709555 ps
CPU time 4.24 seconds
Started May 19 12:24:34 PM PDT 24
Finished May 19 12:24:46 PM PDT 24
Peak memory 198180 kb
Host smart-18db269a-3a0e-4f27-90de-b4b34794722e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575269378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2575269378
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2566466577
Short name T409
Test name
Test status
Simulation time 75275212 ps
CPU time 1.38 seconds
Started May 19 12:26:01 PM PDT 24
Finished May 19 12:26:03 PM PDT 24
Peak memory 197844 kb
Host smart-20c421e8-7200-4c03-8541-e04ebd4f700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566466577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2566466577
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2175958147
Short name T511
Test name
Test status
Simulation time 85249317 ps
CPU time 1.34 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:24:42 PM PDT 24
Peak memory 196536 kb
Host smart-aefc6399-8b13-4f00-8e6e-257b6531a674
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175958147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2175958147
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.724879293
Short name T263
Test name
Test status
Simulation time 16778952326 ps
CPU time 167.91 seconds
Started May 19 12:24:42 PM PDT 24
Finished May 19 12:27:32 PM PDT 24
Peak memory 198020 kb
Host smart-f98c60cb-0ba9-4a4f-a8bd-c2b9bbbede1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724879293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.724879293
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1384241624
Short name T603
Test name
Test status
Simulation time 1029100081313 ps
CPU time 1729.61 seconds
Started May 19 12:24:34 PM PDT 24
Finished May 19 12:53:31 PM PDT 24
Peak memory 198448 kb
Host smart-100d2680-0782-430c-9cee-bffc7ae57c64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1384241624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1384241624
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.656232138
Short name T605
Test name
Test status
Simulation time 40559398 ps
CPU time 0.56 seconds
Started May 19 12:24:38 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 193740 kb
Host smart-017ce19b-9435-4e92-a95e-cd9fa5a07209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656232138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.656232138
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2551906731
Short name T127
Test name
Test status
Simulation time 356276435 ps
CPU time 0.76 seconds
Started May 19 12:24:28 PM PDT 24
Finished May 19 12:24:37 PM PDT 24
Peak memory 195056 kb
Host smart-332a2971-3579-4c34-8070-42de5a2478ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551906731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2551906731
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2799875436
Short name T291
Test name
Test status
Simulation time 411244109 ps
CPU time 12.41 seconds
Started May 19 12:24:35 PM PDT 24
Finished May 19 12:24:54 PM PDT 24
Peak memory 197792 kb
Host smart-4879c92f-1354-4cbf-91ad-023f53bba942
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799875436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2799875436
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3631090311
Short name T141
Test name
Test status
Simulation time 45371724 ps
CPU time 0.84 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 196868 kb
Host smart-d06d51d6-8437-41f1-8060-f964edd0a2f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631090311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3631090311
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1606735629
Short name T554
Test name
Test status
Simulation time 15274131 ps
CPU time 0.71 seconds
Started May 19 12:24:34 PM PDT 24
Finished May 19 12:24:42 PM PDT 24
Peak memory 194572 kb
Host smart-39847e0e-3392-4376-a53c-2c404ab83e47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606735629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1606735629
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2537876656
Short name T248
Test name
Test status
Simulation time 37175903 ps
CPU time 1.58 seconds
Started May 19 12:24:34 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 198104 kb
Host smart-d6ad1177-8f56-47e4-943d-bd23ff531266
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537876656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2537876656
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1076997684
Short name T535
Test name
Test status
Simulation time 262885944 ps
CPU time 1.68 seconds
Started May 19 12:24:35 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 195792 kb
Host smart-1141dae2-43bc-4bcc-8547-f6479157b383
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076997684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1076997684
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1570652785
Short name T423
Test name
Test status
Simulation time 27490191 ps
CPU time 0.76 seconds
Started May 19 12:24:33 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 195288 kb
Host smart-c96d9903-cf52-4985-a550-ad9854afe562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570652785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1570652785
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3359884894
Short name T442
Test name
Test status
Simulation time 163655749 ps
CPU time 0.98 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:39 PM PDT 24
Peak memory 195680 kb
Host smart-4200ddde-18f8-4c4c-966a-53dfe7425f08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359884894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3359884894
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.3313684847
Short name T664
Test name
Test status
Simulation time 1327191006 ps
CPU time 5.7 seconds
Started May 19 12:24:35 PM PDT 24
Finished May 19 12:24:48 PM PDT 24
Peak memory 197780 kb
Host smart-4914be8d-a85a-4e99-bff0-dee7e31824f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313684847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.3313684847
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2378660155
Short name T712
Test name
Test status
Simulation time 109223995 ps
CPU time 0.98 seconds
Started May 19 12:25:43 PM PDT 24
Finished May 19 12:25:45 PM PDT 24
Peak memory 194992 kb
Host smart-45475461-ba71-41dd-817e-ebcdd7806174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378660155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2378660155
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1709650570
Short name T345
Test name
Test status
Simulation time 155572838 ps
CPU time 0.84 seconds
Started May 19 12:24:33 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 195200 kb
Host smart-af0f54e8-d740-45fb-aa47-85c41941626c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709650570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1709650570
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3741799510
Short name T252
Test name
Test status
Simulation time 16729774015 ps
CPU time 188.88 seconds
Started May 19 12:24:33 PM PDT 24
Finished May 19 12:27:49 PM PDT 24
Peak memory 198064 kb
Host smart-ee13fbdf-d9db-483b-a135-ae99ce77fbe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741799510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3741799510
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3427116416
Short name T533
Test name
Test status
Simulation time 48997817 ps
CPU time 0.54 seconds
Started May 19 12:24:46 PM PDT 24
Finished May 19 12:24:48 PM PDT 24
Peak memory 193764 kb
Host smart-aee60756-d849-496c-8d69-976c586023d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427116416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3427116416
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3962845254
Short name T304
Test name
Test status
Simulation time 171239153 ps
CPU time 0.89 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:40 PM PDT 24
Peak memory 195596 kb
Host smart-c09fc05c-3eb8-4053-b4c5-6ee4a6e549a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962845254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3962845254
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3076245831
Short name T651
Test name
Test status
Simulation time 2259901299 ps
CPU time 20.77 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 195472 kb
Host smart-2c9578ec-a8ac-4dcb-bac9-dad15631e1fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076245831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3076245831
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.1788945201
Short name T570
Test name
Test status
Simulation time 106594303 ps
CPU time 1.03 seconds
Started May 19 12:24:36 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 196472 kb
Host smart-2a78904c-0e52-463b-ab79-378429a8ea08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788945201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.1788945201
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3626323141
Short name T701
Test name
Test status
Simulation time 209026183 ps
CPU time 1.11 seconds
Started May 19 12:26:02 PM PDT 24
Finished May 19 12:26:04 PM PDT 24
Peak memory 195564 kb
Host smart-20ac3fd2-2084-47ac-ae8b-2bbae3047b31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626323141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3626323141
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.4152159463
Short name T328
Test name
Test status
Simulation time 86818010 ps
CPU time 3.17 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 197864 kb
Host smart-843c69eb-109b-45a9-bd9e-b557a205395a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152159463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.4152159463
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.890901408
Short name T588
Test name
Test status
Simulation time 102285414 ps
CPU time 2.98 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 196840 kb
Host smart-4ca0fe3d-3bfb-4834-939a-db85b604ea26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890901408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
890901408
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4031065393
Short name T381
Test name
Test status
Simulation time 37272965 ps
CPU time 0.95 seconds
Started May 19 12:24:28 PM PDT 24
Finished May 19 12:24:37 PM PDT 24
Peak memory 197060 kb
Host smart-10aa1c8e-1578-430e-b9ce-24bb025f2435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031065393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4031065393
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.2127243920
Short name T164
Test name
Test status
Simulation time 126273350 ps
CPU time 1.01 seconds
Started May 19 12:26:06 PM PDT 24
Finished May 19 12:26:08 PM PDT 24
Peak memory 195828 kb
Host smart-d3c0ed23-b61c-42e5-937d-687c482c0c8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127243920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.2127243920
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3357941299
Short name T536
Test name
Test status
Simulation time 475474858 ps
CPU time 1.66 seconds
Started May 19 12:26:15 PM PDT 24
Finished May 19 12:26:17 PM PDT 24
Peak memory 197808 kb
Host smart-a8571448-a674-4713-aed6-dd508ff6f4d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357941299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3357941299
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2359619323
Short name T297
Test name
Test status
Simulation time 42671568 ps
CPU time 0.87 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:39 PM PDT 24
Peak memory 195120 kb
Host smart-bb6aa5a9-5366-4bd8-8368-29229e3ff92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359619323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2359619323
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.126558901
Short name T674
Test name
Test status
Simulation time 46412603 ps
CPU time 1.26 seconds
Started May 19 12:24:29 PM PDT 24
Finished May 19 12:24:38 PM PDT 24
Peak memory 197848 kb
Host smart-bb63a97d-c83a-4f62-b97f-c4a9fcd04f40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126558901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.126558901
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3885853368
Short name T136
Test name
Test status
Simulation time 3832540197 ps
CPU time 96.25 seconds
Started May 19 12:24:42 PM PDT 24
Finished May 19 12:26:21 PM PDT 24
Peak memory 198036 kb
Host smart-ea15d641-c322-4b40-aa3b-fad9788ab3b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885853368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3885853368
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1345823885
Short name T362
Test name
Test status
Simulation time 27672432 ps
CPU time 0.57 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 193636 kb
Host smart-f0f412af-2009-41ee-ad8d-dd4a1ad73bec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345823885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1345823885
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3552094164
Short name T492
Test name
Test status
Simulation time 219441364 ps
CPU time 0.78 seconds
Started May 19 12:24:40 PM PDT 24
Finished May 19 12:24:45 PM PDT 24
Peak memory 195128 kb
Host smart-0284640b-c08f-4d09-bd41-0c2ea19e5e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552094164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3552094164
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.175371169
Short name T267
Test name
Test status
Simulation time 1015271703 ps
CPU time 12.66 seconds
Started May 19 12:24:33 PM PDT 24
Finished May 19 12:24:53 PM PDT 24
Peak memory 197168 kb
Host smart-00680f55-d81e-44fc-b2e0-0e0b33555c67
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175371169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.175371169
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.500616061
Short name T526
Test name
Test status
Simulation time 328517727 ps
CPU time 1.05 seconds
Started May 19 12:26:02 PM PDT 24
Finished May 19 12:26:04 PM PDT 24
Peak memory 196168 kb
Host smart-92e9a967-4261-4a50-af7d-6f7b22a3176c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500616061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.500616061
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.954074131
Short name T251
Test name
Test status
Simulation time 149391464 ps
CPU time 1.37 seconds
Started May 19 12:24:34 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 197452 kb
Host smart-9a2913ea-79df-4520-a504-24a04bc1ee7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954074131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.954074131
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.561357717
Short name T645
Test name
Test status
Simulation time 104820092 ps
CPU time 3.08 seconds
Started May 19 12:24:34 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 198188 kb
Host smart-02e325fc-8124-4c16-89ae-123328b93ef0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561357717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.561357717
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.351061563
Short name T266
Test name
Test status
Simulation time 751554367 ps
CPU time 3.18 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 196848 kb
Host smart-40872175-fe3f-413a-9e41-54ea41d7f764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351061563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.
351061563
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3066380874
Short name T166
Test name
Test status
Simulation time 16833339 ps
CPU time 0.74 seconds
Started May 19 12:24:38 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 195896 kb
Host smart-3cdb5e65-7504-46a7-93c6-6659cff0ad46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066380874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3066380874
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2896342874
Short name T710
Test name
Test status
Simulation time 347840397 ps
CPU time 0.87 seconds
Started May 19 12:24:48 PM PDT 24
Finished May 19 12:24:50 PM PDT 24
Peak memory 196528 kb
Host smart-f623d50f-70bf-4c1c-acea-fdcfe41be7a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896342874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2896342874
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2731263883
Short name T544
Test name
Test status
Simulation time 111735664 ps
CPU time 4.81 seconds
Started May 19 12:24:47 PM PDT 24
Finished May 19 12:24:53 PM PDT 24
Peak memory 197904 kb
Host smart-1be1976c-6fe5-44c5-b5b4-3bdbed2450a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731263883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2731263883
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2494007955
Short name T170
Test name
Test status
Simulation time 190821090 ps
CPU time 1.03 seconds
Started May 19 12:24:30 PM PDT 24
Finished May 19 12:24:39 PM PDT 24
Peak memory 195668 kb
Host smart-923498f1-7c4b-4ffc-839f-cf0f482a03ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494007955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2494007955
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.952095786
Short name T693
Test name
Test status
Simulation time 206346372 ps
CPU time 1 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 196188 kb
Host smart-0d045c74-7640-4576-95cd-8d92af17ea89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952095786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.952095786
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1248578684
Short name T405
Test name
Test status
Simulation time 363837297426 ps
CPU time 201.72 seconds
Started May 19 12:24:42 PM PDT 24
Finished May 19 12:28:06 PM PDT 24
Peak memory 198060 kb
Host smart-305000d3-829d-4f06-8454-2aa3a9c14430
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248578684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1248578684
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.649006544
Short name T54
Test name
Test status
Simulation time 157035801798 ps
CPU time 608.38 seconds
Started May 19 12:26:02 PM PDT 24
Finished May 19 12:36:11 PM PDT 24
Peak memory 198092 kb
Host smart-079328d2-bbd3-4d97-99d9-b7707d78ab60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=649006544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.649006544
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4208198173
Short name T599
Test name
Test status
Simulation time 34719006 ps
CPU time 0.6 seconds
Started May 19 12:24:48 PM PDT 24
Finished May 19 12:24:50 PM PDT 24
Peak memory 193880 kb
Host smart-344d5c46-aefb-466f-aee2-2adcceb33eaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208198173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4208198173
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2497646992
Short name T112
Test name
Test status
Simulation time 82381335 ps
CPU time 0.64 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 193976 kb
Host smart-f4a3eac0-4509-49fa-932a-500092c3d300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497646992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2497646992
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.351975879
Short name T415
Test name
Test status
Simulation time 1466980886 ps
CPU time 23.1 seconds
Started May 19 12:24:51 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 197892 kb
Host smart-88ff311f-15b6-4b98-b20b-694e8c120f75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351975879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.351975879
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2814873974
Short name T626
Test name
Test status
Simulation time 68147272 ps
CPU time 0.9 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:12 PM PDT 24
Peak memory 196664 kb
Host smart-2b56dbbf-10ef-4c06-8f40-21ac0e073bf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814873974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2814873974
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3984614699
Short name T272
Test name
Test status
Simulation time 97053594 ps
CPU time 1.36 seconds
Started May 19 12:24:36 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 197904 kb
Host smart-a53948b8-3876-490a-b58e-361d069d959a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984614699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3984614699
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2706915759
Short name T656
Test name
Test status
Simulation time 424193719 ps
CPU time 2.26 seconds
Started May 19 12:24:33 PM PDT 24
Finished May 19 12:24:43 PM PDT 24
Peak memory 197916 kb
Host smart-33029076-87a1-46b2-88b9-8763fdf925b1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706915759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2706915759
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3294222872
Short name T718
Test name
Test status
Simulation time 150954043 ps
CPU time 2.41 seconds
Started May 19 12:24:35 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 196940 kb
Host smart-b5e09f21-95b2-47f5-82f5-8e0dd760c4e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294222872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3294222872
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.722661436
Short name T184
Test name
Test status
Simulation time 22684750 ps
CPU time 0.84 seconds
Started May 19 12:24:38 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 197180 kb
Host smart-4ebd6865-b9ab-4f2f-ab08-2efc782b01b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722661436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.722661436
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.4021447248
Short name T681
Test name
Test status
Simulation time 34501961 ps
CPU time 0.76 seconds
Started May 19 12:26:01 PM PDT 24
Finished May 19 12:26:03 PM PDT 24
Peak memory 195380 kb
Host smart-0f111524-745d-48c5-a401-9cb53d9e053c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021447248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.4021447248
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2428637765
Short name T332
Test name
Test status
Simulation time 392467834 ps
CPU time 4.42 seconds
Started May 19 12:24:44 PM PDT 24
Finished May 19 12:24:50 PM PDT 24
Peak memory 197720 kb
Host smart-f4c59fa1-f5b5-4556-8b8e-36c7d779ef0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428637765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2428637765
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.839374201
Short name T472
Test name
Test status
Simulation time 1023590018 ps
CPU time 1.26 seconds
Started May 19 12:24:33 PM PDT 24
Finished May 19 12:24:42 PM PDT 24
Peak memory 196960 kb
Host smart-0350a635-0b6b-4f71-aa11-869c8571051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839374201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.839374201
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.529598844
Short name T562
Test name
Test status
Simulation time 118578262 ps
CPU time 0.76 seconds
Started May 19 12:26:01 PM PDT 24
Finished May 19 12:26:03 PM PDT 24
Peak memory 195788 kb
Host smart-196f3999-7da7-4ee3-bc1c-3f266b1dffba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529598844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.529598844
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1059540764
Short name T493
Test name
Test status
Simulation time 83267499669 ps
CPU time 143.82 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:27:16 PM PDT 24
Peak memory 198056 kb
Host smart-cde10ae8-7378-4038-8126-501622811516
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059540764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1059540764
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.1623092481
Short name T358
Test name
Test status
Simulation time 80333518567 ps
CPU time 1786.35 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:54:43 PM PDT 24
Peak memory 198060 kb
Host smart-10d1ba86-885e-400d-866e-dab09c935a0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1623092481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.1623092481
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2081548101
Short name T676
Test name
Test status
Simulation time 18894736 ps
CPU time 0.56 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 193680 kb
Host smart-35e54565-c20d-4ab7-9543-8677080e625e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081548101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2081548101
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.4237546940
Short name T386
Test name
Test status
Simulation time 125229568 ps
CPU time 0.78 seconds
Started May 19 12:25:00 PM PDT 24
Finished May 19 12:25:04 PM PDT 24
Peak memory 195232 kb
Host smart-0d274e9f-5e5b-429a-a25c-0fb6bb7e0a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237546940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.4237546940
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2570802899
Short name T713
Test name
Test status
Simulation time 280513729 ps
CPU time 9.11 seconds
Started May 19 12:24:56 PM PDT 24
Finished May 19 12:25:09 PM PDT 24
Peak memory 196668 kb
Host smart-5cb46a99-48c6-40b4-9943-a3fc43e17012
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570802899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2570802899
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.582218200
Short name T364
Test name
Test status
Simulation time 654250081 ps
CPU time 0.77 seconds
Started May 19 12:24:48 PM PDT 24
Finished May 19 12:24:51 PM PDT 24
Peak memory 196508 kb
Host smart-00a23305-f6a6-4ac7-865b-6d5ad5158d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582218200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.582218200
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1318498309
Short name T591
Test name
Test status
Simulation time 111935403 ps
CPU time 0.67 seconds
Started May 19 12:24:48 PM PDT 24
Finished May 19 12:24:50 PM PDT 24
Peak memory 194796 kb
Host smart-339be0e6-70ee-41fd-982c-620599492d56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318498309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1318498309
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3560936595
Short name T226
Test name
Test status
Simulation time 92859832 ps
CPU time 3.47 seconds
Started May 19 12:24:48 PM PDT 24
Finished May 19 12:24:53 PM PDT 24
Peak memory 197832 kb
Host smart-97334b20-e605-4872-a59a-3ba31e748f7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560936595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3560936595
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1230026716
Short name T134
Test name
Test status
Simulation time 398060323 ps
CPU time 2.91 seconds
Started May 19 12:24:46 PM PDT 24
Finished May 19 12:24:51 PM PDT 24
Peak memory 195652 kb
Host smart-d80ad481-c76d-40b3-b752-bfdcc9ea7ebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230026716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1230026716
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.93522224
Short name T186
Test name
Test status
Simulation time 21783804 ps
CPU time 0.65 seconds
Started May 19 12:24:46 PM PDT 24
Finished May 19 12:24:47 PM PDT 24
Peak memory 194140 kb
Host smart-2c04acdc-f4d0-40ef-a6df-744df1830697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93522224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.93522224
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3398205500
Short name T329
Test name
Test status
Simulation time 115528474 ps
CPU time 1.21 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 195628 kb
Host smart-e2cf6e6a-2ea0-432f-8ecf-b5d42676c0cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398205500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3398205500
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3579364564
Short name T489
Test name
Test status
Simulation time 1041355785 ps
CPU time 4.52 seconds
Started May 19 12:24:46 PM PDT 24
Finished May 19 12:24:52 PM PDT 24
Peak memory 197880 kb
Host smart-9fe1dcdd-df4e-4202-b26b-fb9345cd9329
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579364564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3579364564
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.717796165
Short name T604
Test name
Test status
Simulation time 413556008 ps
CPU time 0.8 seconds
Started May 19 12:24:45 PM PDT 24
Finished May 19 12:24:47 PM PDT 24
Peak memory 194996 kb
Host smart-c653ce23-5df8-414d-b583-f15df2382ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717796165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.717796165
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1523842970
Short name T150
Test name
Test status
Simulation time 172493361 ps
CPU time 1.19 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 195708 kb
Host smart-cc91978a-4c47-4981-8dfc-ffec3b6c5a5e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523842970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1523842970
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2959497317
Short name T692
Test name
Test status
Simulation time 15487819289 ps
CPU time 157.38 seconds
Started May 19 12:24:56 PM PDT 24
Finished May 19 12:27:37 PM PDT 24
Peak memory 198040 kb
Host smart-7bca2bd9-e089-4a8f-b821-94842caaa7d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959497317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2959497317
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2571920193
Short name T719
Test name
Test status
Simulation time 165096099828 ps
CPU time 1418.66 seconds
Started May 19 12:24:47 PM PDT 24
Finished May 19 12:48:27 PM PDT 24
Peak memory 198056 kb
Host smart-c1517c31-c33f-44d4-b983-0bbee15e49d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2571920193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2571920193
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1422813962
Short name T471
Test name
Test status
Simulation time 32163194 ps
CPU time 0.57 seconds
Started May 19 12:24:40 PM PDT 24
Finished May 19 12:24:44 PM PDT 24
Peak memory 194612 kb
Host smart-64c1a7f9-bef6-49ca-8227-888a7dd9b0f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422813962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1422813962
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.24186116
Short name T518
Test name
Test status
Simulation time 36593628 ps
CPU time 0.85 seconds
Started May 19 12:24:51 PM PDT 24
Finished May 19 12:24:55 PM PDT 24
Peak memory 195896 kb
Host smart-cb163d83-e87a-4f1f-8273-06c66260304c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24186116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.24186116
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3504433563
Short name T507
Test name
Test status
Simulation time 2013771725 ps
CPU time 16.21 seconds
Started May 19 12:24:47 PM PDT 24
Finished May 19 12:25:05 PM PDT 24
Peak memory 195432 kb
Host smart-02a93e98-6970-444f-93a1-d828771fa3a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504433563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3504433563
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3432236288
Short name T171
Test name
Test status
Simulation time 131565971 ps
CPU time 0.7 seconds
Started May 19 12:24:55 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 194592 kb
Host smart-c333a9ed-f927-4325-bd8e-ac3bf32089b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432236288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3432236288
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.3434370019
Short name T628
Test name
Test status
Simulation time 28316535 ps
CPU time 0.78 seconds
Started May 19 12:24:56 PM PDT 24
Finished May 19 12:25:05 PM PDT 24
Peak memory 195292 kb
Host smart-c28c7e07-a18b-40ea-b256-d73342389e48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434370019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.3434370019
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.2287621116
Short name T103
Test name
Test status
Simulation time 88623828 ps
CPU time 1.77 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 197868 kb
Host smart-8103294f-3687-4603-a9fc-778510b427ce
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287621116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.2287621116
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.346975196
Short name T270
Test name
Test status
Simulation time 91330103 ps
CPU time 1.05 seconds
Started May 19 12:24:53 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 195556 kb
Host smart-f4930b4f-0308-45de-bfd2-a4f33f51a576
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346975196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
346975196
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1168411445
Short name T379
Test name
Test status
Simulation time 98471247 ps
CPU time 0.97 seconds
Started May 19 12:24:50 PM PDT 24
Finished May 19 12:24:53 PM PDT 24
Peak memory 195668 kb
Host smart-48a1c90d-be78-423c-8cd0-36f26be8530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168411445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1168411445
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1205231519
Short name T413
Test name
Test status
Simulation time 128314196 ps
CPU time 1.35 seconds
Started May 19 12:24:57 PM PDT 24
Finished May 19 12:25:02 PM PDT 24
Peak memory 196844 kb
Host smart-ec9b06ba-89dd-4bc2-a571-6bbd53a5c7c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205231519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1205231519
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2640332538
Short name T608
Test name
Test status
Simulation time 386905961 ps
CPU time 3.3 seconds
Started May 19 12:24:44 PM PDT 24
Finished May 19 12:24:49 PM PDT 24
Peak memory 197828 kb
Host smart-6033b01b-ff5d-4361-a5ba-29a164bcba26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640332538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2640332538
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2781819169
Short name T499
Test name
Test status
Simulation time 57727047 ps
CPU time 1.08 seconds
Started May 19 12:24:57 PM PDT 24
Finished May 19 12:25:02 PM PDT 24
Peak memory 195492 kb
Host smart-ec1d0ccb-5a08-44f5-9186-27943419c37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781819169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2781819169
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.714765604
Short name T335
Test name
Test status
Simulation time 66384477 ps
CPU time 1.13 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:56 PM PDT 24
Peak memory 196332 kb
Host smart-f7687821-fa56-4c8e-892b-5bdd88f8a962
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714765604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.714765604
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.587559645
Short name T637
Test name
Test status
Simulation time 29241534522 ps
CPU time 90.32 seconds
Started May 19 12:24:45 PM PDT 24
Finished May 19 12:26:16 PM PDT 24
Peak memory 197960 kb
Host smart-b8290eb6-4e4d-462c-8c94-f7ec6302ee54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587559645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.587559645
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2442696170
Short name T151
Test name
Test status
Simulation time 14065647 ps
CPU time 0.59 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:24:52 PM PDT 24
Peak memory 194712 kb
Host smart-22d09694-45d2-4e4b-b936-e46668d2dd9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442696170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2442696170
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3524283477
Short name T647
Test name
Test status
Simulation time 74432508 ps
CPU time 0.74 seconds
Started May 19 12:24:42 PM PDT 24
Finished May 19 12:24:45 PM PDT 24
Peak memory 195708 kb
Host smart-a3e90854-ef26-4a77-ad7a-e7599ea40f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524283477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3524283477
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1983630012
Short name T343
Test name
Test status
Simulation time 435248564 ps
CPU time 13.54 seconds
Started May 19 12:24:51 PM PDT 24
Finished May 19 12:25:08 PM PDT 24
Peak memory 196652 kb
Host smart-4e404800-1571-4910-8af3-e708fd596ad2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983630012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1983630012
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2401921574
Short name T539
Test name
Test status
Simulation time 53705891 ps
CPU time 0.93 seconds
Started May 19 12:24:50 PM PDT 24
Finished May 19 12:24:54 PM PDT 24
Peak memory 197652 kb
Host smart-1d8b6fc7-52ee-4a96-8843-4715ff4bff61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401921574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2401921574
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2919630009
Short name T663
Test name
Test status
Simulation time 83834176 ps
CPU time 0.8 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 196024 kb
Host smart-2cabe361-f4fb-4104-a577-032887accda6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919630009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2919630009
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2636453339
Short name T666
Test name
Test status
Simulation time 80857247 ps
CPU time 2.2 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:25:01 PM PDT 24
Peak memory 197940 kb
Host smart-472c04b0-14bc-4067-ac16-7dfe3446ad21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636453339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2636453339
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.4241570986
Short name T339
Test name
Test status
Simulation time 517253539 ps
CPU time 2.64 seconds
Started May 19 12:24:42 PM PDT 24
Finished May 19 12:24:47 PM PDT 24
Peak memory 197892 kb
Host smart-8ffd4a13-4488-47e2-8417-b718d34d477d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241570986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.4241570986
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.29000898
Short name T584
Test name
Test status
Simulation time 62098841 ps
CPU time 1.14 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 197096 kb
Host smart-f281a66a-01a3-4495-9a02-1a31798eb0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29000898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.29000898
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.79274930
Short name T145
Test name
Test status
Simulation time 20405779 ps
CPU time 0.77 seconds
Started May 19 12:24:51 PM PDT 24
Finished May 19 12:24:56 PM PDT 24
Peak memory 195396 kb
Host smart-c227bd73-18db-4a9b-8ec4-61861a12d195
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79274930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup_
pulldown.79274930
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1855790366
Short name T338
Test name
Test status
Simulation time 233738193 ps
CPU time 3.05 seconds
Started May 19 12:24:59 PM PDT 24
Finished May 19 12:25:05 PM PDT 24
Peak memory 197732 kb
Host smart-108fedd7-074f-44b0-a3ff-cc28cbc39fd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855790366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1855790366
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1280540792
Short name T352
Test name
Test status
Simulation time 208657914 ps
CPU time 1.23 seconds
Started May 19 12:24:48 PM PDT 24
Finished May 19 12:24:50 PM PDT 24
Peak memory 197792 kb
Host smart-86daa0b1-f361-4f66-a175-26d68c63766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280540792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1280540792
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1830717262
Short name T294
Test name
Test status
Simulation time 395125556 ps
CPU time 1.17 seconds
Started May 19 12:24:57 PM PDT 24
Finished May 19 12:25:02 PM PDT 24
Peak memory 195560 kb
Host smart-a28a5554-d0cc-4573-a687-4bdd98adebeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830717262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1830717262
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1747028562
Short name T541
Test name
Test status
Simulation time 50110844263 ps
CPU time 101 seconds
Started May 19 12:24:43 PM PDT 24
Finished May 19 12:26:26 PM PDT 24
Peak memory 198004 kb
Host smart-fc5a5b0d-0a41-4268-8289-94e40b78d445
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747028562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1747028562
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.356721172
Short name T298
Test name
Test status
Simulation time 19315770 ps
CPU time 0.6 seconds
Started May 19 12:23:01 PM PDT 24
Finished May 19 12:23:03 PM PDT 24
Peak memory 193892 kb
Host smart-aac5e47d-e3ff-4e9e-80d9-2e997e054deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356721172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.356721172
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2796905338
Short name T615
Test name
Test status
Simulation time 21524990 ps
CPU time 0.74 seconds
Started May 19 12:23:25 PM PDT 24
Finished May 19 12:23:41 PM PDT 24
Peak memory 195148 kb
Host smart-3a19a920-f9cb-4904-bd45-12233b47f73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796905338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2796905338
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1868930390
Short name T655
Test name
Test status
Simulation time 610654156 ps
CPU time 17.42 seconds
Started May 19 12:23:15 PM PDT 24
Finished May 19 12:23:37 PM PDT 24
Peak memory 197788 kb
Host smart-d44a6f6e-b8c6-4013-abd6-c724ebdcfba7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868930390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1868930390
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1541560766
Short name T301
Test name
Test status
Simulation time 103044507 ps
CPU time 1.12 seconds
Started May 19 12:22:59 PM PDT 24
Finished May 19 12:23:02 PM PDT 24
Peak memory 196136 kb
Host smart-0ff4317d-0222-47af-b352-4f00d3ebad89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541560766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1541560766
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2240468739
Short name T357
Test name
Test status
Simulation time 116455446 ps
CPU time 1.32 seconds
Started May 19 12:22:57 PM PDT 24
Finished May 19 12:22:59 PM PDT 24
Peak memory 197032 kb
Host smart-7e458224-4b05-4ddb-8445-0aa44f1a5931
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240468739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2240468739
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1178058841
Short name T192
Test name
Test status
Simulation time 94184835 ps
CPU time 3.54 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:50 PM PDT 24
Peak memory 197832 kb
Host smart-262d0856-a95a-4370-a5ba-39839e3922e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178058841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1178058841
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.332709120
Short name T416
Test name
Test status
Simulation time 164699342 ps
CPU time 3.33 seconds
Started May 19 12:23:17 PM PDT 24
Finished May 19 12:23:26 PM PDT 24
Peak memory 196680 kb
Host smart-d38cd987-afe5-48c6-a449-9c3916cc48df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332709120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.332709120
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1184276541
Short name T111
Test name
Test status
Simulation time 113073342 ps
CPU time 1.15 seconds
Started May 19 12:22:57 PM PDT 24
Finished May 19 12:22:59 PM PDT 24
Peak memory 195740 kb
Host smart-6eb75e2d-d4ec-4aa2-bb54-fa99351166a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184276541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1184276541
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3056469558
Short name T678
Test name
Test status
Simulation time 192556669 ps
CPU time 1.19 seconds
Started May 19 12:22:56 PM PDT 24
Finished May 19 12:22:58 PM PDT 24
Peak memory 196840 kb
Host smart-8db67fc1-4219-4b5c-8be7-3bda397e9d28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056469558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3056469558
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3475449631
Short name T445
Test name
Test status
Simulation time 501313688 ps
CPU time 1.89 seconds
Started May 19 12:23:01 PM PDT 24
Finished May 19 12:23:03 PM PDT 24
Peak memory 197828 kb
Host smart-4409627f-7bbc-44ec-85ba-b5455586440d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475449631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3475449631
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.1669784887
Short name T36
Test name
Test status
Simulation time 33101313 ps
CPU time 0.79 seconds
Started May 19 12:22:59 PM PDT 24
Finished May 19 12:23:01 PM PDT 24
Peak memory 213544 kb
Host smart-7b78646d-f0c9-4e15-9f85-0d798051df2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669784887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.1669784887
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.4083898364
Short name T660
Test name
Test status
Simulation time 80632238 ps
CPU time 0.89 seconds
Started May 19 12:22:48 PM PDT 24
Finished May 19 12:22:50 PM PDT 24
Peak memory 196316 kb
Host smart-b96062c0-ca5d-46e3-8d7d-6ff839d5c40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083898364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4083898364
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1906065665
Short name T642
Test name
Test status
Simulation time 51490453 ps
CPU time 0.99 seconds
Started May 19 12:20:46 PM PDT 24
Finished May 19 12:20:49 PM PDT 24
Peak memory 196828 kb
Host smart-35d28e7e-5ae7-4d3f-a815-c4c2f371b5a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906065665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1906065665
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3983840563
Short name T634
Test name
Test status
Simulation time 29910331296 ps
CPU time 25.11 seconds
Started May 19 12:23:45 PM PDT 24
Finished May 19 12:24:26 PM PDT 24
Peak memory 197980 kb
Host smart-167eeb82-1642-4af6-b663-1e0b36b3f91f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983840563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3983840563
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.48268799
Short name T552
Test name
Test status
Simulation time 51424603834 ps
CPU time 608.88 seconds
Started May 19 12:23:02 PM PDT 24
Finished May 19 12:33:12 PM PDT 24
Peak memory 198136 kb
Host smart-86be6be2-ca58-46f6-ab0c-0ca5b5784c6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=48268799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.48268799
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1054534857
Short name T702
Test name
Test status
Simulation time 88545964 ps
CPU time 0.56 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:20 PM PDT 24
Peak memory 194548 kb
Host smart-2e222695-8f6e-41aa-bef5-809b28f83b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054534857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1054534857
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1482244290
Short name T247
Test name
Test status
Simulation time 104685345 ps
CPU time 0.9 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:24:52 PM PDT 24
Peak memory 195508 kb
Host smart-13ddaf53-87b1-49bb-918d-e6aed693ddd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482244290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1482244290
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.760445756
Short name T378
Test name
Test status
Simulation time 182778972 ps
CPU time 9.3 seconds
Started May 19 12:24:45 PM PDT 24
Finished May 19 12:24:55 PM PDT 24
Peak memory 196768 kb
Host smart-28a2ca95-da95-480b-a109-9a01ed92bc99
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760445756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.760445756
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.821121473
Short name T234
Test name
Test status
Simulation time 68431129 ps
CPU time 0.94 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:24:52 PM PDT 24
Peak memory 196380 kb
Host smart-0a8544d6-a274-47a5-9040-c3e16031ea6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821121473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.821121473
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2391822246
Short name T244
Test name
Test status
Simulation time 531363370 ps
CPU time 1.28 seconds
Started May 19 12:24:46 PM PDT 24
Finished May 19 12:24:49 PM PDT 24
Peak memory 197024 kb
Host smart-39f032d2-87b1-4bbc-ab02-c6ad38eb416f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391822246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2391822246
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3340736535
Short name T550
Test name
Test status
Simulation time 56608708 ps
CPU time 2.44 seconds
Started May 19 12:25:00 PM PDT 24
Finished May 19 12:25:06 PM PDT 24
Peak memory 197860 kb
Host smart-93cec684-d7d1-469c-9ba4-7676bc9bee9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340736535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3340736535
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1858925575
Short name T633
Test name
Test status
Simulation time 201300030 ps
CPU time 2.15 seconds
Started May 19 12:24:57 PM PDT 24
Finished May 19 12:25:03 PM PDT 24
Peak memory 195932 kb
Host smart-15647b3f-dcb8-4249-bee6-d6f1e03f1f3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858925575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1858925575
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.4274497784
Short name T525
Test name
Test status
Simulation time 50032303 ps
CPU time 1.04 seconds
Started May 19 12:24:47 PM PDT 24
Finished May 19 12:24:49 PM PDT 24
Peak memory 195668 kb
Host smart-208dcdbd-aaeb-4480-b1aa-fe77153224f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274497784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.4274497784
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3643853077
Short name T575
Test name
Test status
Simulation time 50669649 ps
CPU time 1.15 seconds
Started May 19 12:24:43 PM PDT 24
Finished May 19 12:24:46 PM PDT 24
Peak memory 195688 kb
Host smart-73780433-8a54-497a-be5e-72b05054a518
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643853077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3643853077
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3411103822
Short name T9
Test name
Test status
Simulation time 467104085 ps
CPU time 6.08 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 197804 kb
Host smart-31f95438-7cd9-4322-b243-46e0ba3ffa78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411103822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3411103822
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.419706268
Short name T711
Test name
Test status
Simulation time 32111224 ps
CPU time 0.83 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 195016 kb
Host smart-628c1de9-2d38-429f-a37e-25f6af2e1880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419706268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.419706268
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3351466610
Short name T696
Test name
Test status
Simulation time 80944313 ps
CPU time 1.18 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:24:53 PM PDT 24
Peak memory 196544 kb
Host smart-6504ee3a-dd93-47cf-a0bd-1dfb3e4b59e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351466610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3351466610
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3597501210
Short name T318
Test name
Test status
Simulation time 22761144646 ps
CPU time 69.47 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:26:31 PM PDT 24
Peak memory 198060 kb
Host smart-5ac958d9-9d32-403c-bf19-4d4e9bc1851f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597501210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3597501210
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.886324733
Short name T53
Test name
Test status
Simulation time 879512623874 ps
CPU time 1963.1 seconds
Started May 19 12:25:11 PM PDT 24
Finished May 19 12:58:03 PM PDT 24
Peak memory 198112 kb
Host smart-a86d3fc4-b22d-416b-b299-423110c87ec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=886324733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.886324733
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.768032245
Short name T299
Test name
Test status
Simulation time 32215159 ps
CPU time 0.54 seconds
Started May 19 12:25:08 PM PDT 24
Finished May 19 12:25:16 PM PDT 24
Peak memory 194408 kb
Host smart-e6bc109c-fa5d-4a03-8743-85041c3fcd34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768032245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.768032245
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3956473377
Short name T24
Test name
Test status
Simulation time 183339058 ps
CPU time 0.91 seconds
Started May 19 12:25:12 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 196332 kb
Host smart-c87cbc83-ff81-473a-a401-640ef1e665d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956473377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3956473377
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3862066229
Short name T530
Test name
Test status
Simulation time 3837650648 ps
CPU time 25.57 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:32 PM PDT 24
Peak memory 196508 kb
Host smart-3f17f1cf-9b03-429b-a741-8d8f544d9fbc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862066229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3862066229
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3316732468
Short name T6
Test name
Test status
Simulation time 179061986 ps
CPU time 0.92 seconds
Started May 19 12:24:55 PM PDT 24
Finished May 19 12:25:00 PM PDT 24
Peak memory 196212 kb
Host smart-d01a6e06-009c-4e6b-a909-3b565eb2e722
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316732468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3316732468
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2345913754
Short name T510
Test name
Test status
Simulation time 602898711 ps
CPU time 1.24 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:09 PM PDT 24
Peak memory 196044 kb
Host smart-74a2b90f-e4c3-45f2-b70b-3a2549916974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345913754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2345913754
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.4220474342
Short name T365
Test name
Test status
Simulation time 73276222 ps
CPU time 1.6 seconds
Started May 19 12:25:01 PM PDT 24
Finished May 19 12:25:07 PM PDT 24
Peak memory 196692 kb
Host smart-7387c21c-8226-481a-ab0a-035530bc3a68
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220474342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.4220474342
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1272659315
Short name T397
Test name
Test status
Simulation time 173929007 ps
CPU time 1.37 seconds
Started May 19 12:24:55 PM PDT 24
Finished May 19 12:25:00 PM PDT 24
Peak memory 195968 kb
Host smart-43b24daa-f76f-4cfa-a296-28acf9b621bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272659315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1272659315
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.516887969
Short name T15
Test name
Test status
Simulation time 56837670 ps
CPU time 0.81 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 196360 kb
Host smart-420a7ebf-81f8-447d-9d3b-aba3f758649a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516887969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.516887969
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2078753927
Short name T121
Test name
Test status
Simulation time 58410520 ps
CPU time 1.25 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:57 PM PDT 24
Peak memory 197208 kb
Host smart-68e2bb9b-ad75-404a-bc8c-904bb2ad31d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078753927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2078753927
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2707789758
Short name T408
Test name
Test status
Simulation time 247084611 ps
CPU time 3.75 seconds
Started May 19 12:24:51 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 197740 kb
Host smart-4217867d-cf66-4640-a026-454faf03212f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707789758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2707789758
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.207909711
Short name T49
Test name
Test status
Simulation time 39873089 ps
CPU time 1.14 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:16 PM PDT 24
Peak memory 195916 kb
Host smart-25c0d73a-367e-4546-898d-652e3feafd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207909711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.207909711
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3906880967
Short name T657
Test name
Test status
Simulation time 221040928 ps
CPU time 1.13 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:16 PM PDT 24
Peak memory 195284 kb
Host smart-bccfd788-95dd-4124-bba3-a482046fde68
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906880967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3906880967
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3078657325
Short name T450
Test name
Test status
Simulation time 8908087195 ps
CPU time 116.99 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:27:09 PM PDT 24
Peak memory 198024 kb
Host smart-c8c841b0-47d1-4fc3-b500-7dbe72442b90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078657325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3078657325
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.167348098
Short name T334
Test name
Test status
Simulation time 62776005 ps
CPU time 0.52 seconds
Started May 19 12:25:18 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 193732 kb
Host smart-566ea1c7-6227-45cf-9cf6-d5eff92493f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167348098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.167348098
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.640003566
Short name T106
Test name
Test status
Simulation time 40709940 ps
CPU time 0.65 seconds
Started May 19 12:24:56 PM PDT 24
Finished May 19 12:25:05 PM PDT 24
Peak memory 193820 kb
Host smart-e7f7f22f-6955-4a54-a763-223d129a3ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640003566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.640003566
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4225468770
Short name T215
Test name
Test status
Simulation time 3368300625 ps
CPU time 24.18 seconds
Started May 19 12:24:58 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 196776 kb
Host smart-106cc5eb-d6fd-463e-a561-5fd58adfc257
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225468770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4225468770
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2347760216
Short name T286
Test name
Test status
Simulation time 188276510 ps
CPU time 0.79 seconds
Started May 19 12:25:01 PM PDT 24
Finished May 19 12:25:04 PM PDT 24
Peak memory 195688 kb
Host smart-9a2dc884-fa5d-4a11-bf31-13385d05e10b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347760216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2347760216
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3173368417
Short name T260
Test name
Test status
Simulation time 173661873 ps
CPU time 1.16 seconds
Started May 19 12:25:12 PM PDT 24
Finished May 19 12:25:22 PM PDT 24
Peak memory 195764 kb
Host smart-b487c901-edda-4d16-9dcc-a0768e8cc34a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173368417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3173368417
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.951796064
Short name T369
Test name
Test status
Simulation time 43229370 ps
CPU time 1.77 seconds
Started May 19 12:25:04 PM PDT 24
Finished May 19 12:25:12 PM PDT 24
Peak memory 198300 kb
Host smart-366e5fea-4079-4796-a6e1-cda2cb2d7375
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951796064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.951796064
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3257893858
Short name T706
Test name
Test status
Simulation time 1359347915 ps
CPU time 2.91 seconds
Started May 19 12:25:14 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 197760 kb
Host smart-cbbd3808-3905-468a-9d12-f23c55ccd7a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257893858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3257893858
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3977373254
Short name T245
Test name
Test status
Simulation time 170873109 ps
CPU time 0.95 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 195848 kb
Host smart-fa158122-b701-43b0-9375-1d18d1b5125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977373254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3977373254
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2951934235
Short name T167
Test name
Test status
Simulation time 45638610 ps
CPU time 0.66 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 194124 kb
Host smart-b5b1bcb7-45d4-4220-a93e-f924a76f5351
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951934235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2951934235
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3295283731
Short name T643
Test name
Test status
Simulation time 934076165 ps
CPU time 2.87 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 197832 kb
Host smart-1667e5f2-8c27-46f3-84ee-362f9a9afd39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295283731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3295283731
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3389002911
Short name T314
Test name
Test status
Simulation time 125584675 ps
CPU time 1.22 seconds
Started May 19 12:25:03 PM PDT 24
Finished May 19 12:25:10 PM PDT 24
Peak memory 196556 kb
Host smart-398def33-bcdc-43bd-8441-887552841a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389002911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3389002911
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.242098729
Short name T281
Test name
Test status
Simulation time 35658624 ps
CPU time 0.93 seconds
Started May 19 12:24:47 PM PDT 24
Finished May 19 12:24:50 PM PDT 24
Peak memory 196440 kb
Host smart-928e4dba-8de7-41ce-9d92-3cfe786ec206
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242098729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.242098729
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3109002532
Short name T612
Test name
Test status
Simulation time 9845833101 ps
CPU time 117.37 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:27:11 PM PDT 24
Peak memory 197972 kb
Host smart-3b2db7fd-569b-4e7a-86db-a70765a74176
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109002532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3109002532
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1154690661
Short name T359
Test name
Test status
Simulation time 47436858 ps
CPU time 0.58 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:13 PM PDT 24
Peak memory 193912 kb
Host smart-0277aef2-c91f-4abd-890a-756f5cd6ee5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154690661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1154690661
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3349946663
Short name T624
Test name
Test status
Simulation time 25022033 ps
CPU time 0.75 seconds
Started May 19 12:24:49 PM PDT 24
Finished May 19 12:24:51 PM PDT 24
Peak memory 195296 kb
Host smart-12319353-c2ce-4d21-83d0-8269fc501a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349946663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3349946663
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2480715147
Short name T446
Test name
Test status
Simulation time 870415406 ps
CPU time 19.05 seconds
Started May 19 12:24:56 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 196648 kb
Host smart-08828354-9f27-4a4e-a68b-6eff9d6af1db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480715147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2480715147
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.944316769
Short name T224
Test name
Test status
Simulation time 61263110 ps
CPU time 0.94 seconds
Started May 19 12:24:53 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 197500 kb
Host smart-2215e4f4-9d2b-47b3-8d91-00bfe47f5df7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944316769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.944316769
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.255511854
Short name T648
Test name
Test status
Simulation time 242146234 ps
CPU time 1.09 seconds
Started May 19 12:24:48 PM PDT 24
Finished May 19 12:24:57 PM PDT 24
Peak memory 195884 kb
Host smart-11123be0-80c4-41c8-9c51-4db90c54223e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255511854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.255511854
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.676723280
Short name T447
Test name
Test status
Simulation time 555081032 ps
CPU time 3.31 seconds
Started May 19 12:24:53 PM PDT 24
Finished May 19 12:25:01 PM PDT 24
Peak memory 197932 kb
Host smart-de08e369-8ac3-4e20-beb8-a20fd8edd015
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676723280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.676723280
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2638329925
Short name T671
Test name
Test status
Simulation time 38451973 ps
CPU time 1.06 seconds
Started May 19 12:24:53 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 196132 kb
Host smart-136f8c51-1ebc-4e11-b827-1564767c86d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638329925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2638329925
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2013126693
Short name T47
Test name
Test status
Simulation time 41336747 ps
CPU time 1.01 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 195744 kb
Host smart-1ae55fa9-498b-4bcd-8d00-0816b0ec269f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013126693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2013126693
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3922214092
Short name T689
Test name
Test status
Simulation time 84294399 ps
CPU time 0.98 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:18 PM PDT 24
Peak memory 195712 kb
Host smart-85053927-99d8-4ce1-a451-cc6e4f92635b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922214092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3922214092
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1734127364
Short name T700
Test name
Test status
Simulation time 1856103079 ps
CPU time 5.71 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:25:04 PM PDT 24
Peak memory 197728 kb
Host smart-0b67d529-9662-4a3f-9a63-fb6785142d74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734127364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1734127364
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.348483223
Short name T467
Test name
Test status
Simulation time 211435577 ps
CPU time 1.18 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:15 PM PDT 24
Peak memory 196000 kb
Host smart-17b6eea5-da33-496f-92ff-129162f9a30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348483223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.348483223
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1190300047
Short name T574
Test name
Test status
Simulation time 32674964 ps
CPU time 0.99 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 196268 kb
Host smart-f1ecd889-66ef-4a42-ada5-977c37c3987e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190300047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1190300047
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.824730876
Short name T606
Test name
Test status
Simulation time 60106034082 ps
CPU time 101.64 seconds
Started May 19 12:25:03 PM PDT 24
Finished May 19 12:26:51 PM PDT 24
Peak memory 198040 kb
Host smart-c455a49e-8e38-421d-9fd4-a5625d2e60d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824730876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.824730876
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1322702980
Short name T242
Test name
Test status
Simulation time 18280736 ps
CPU time 0.55 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:18 PM PDT 24
Peak memory 193720 kb
Host smart-f1648fa8-228e-4752-85ad-c0ac6fa9530b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322702980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1322702980
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.108077676
Short name T538
Test name
Test status
Simulation time 67345923 ps
CPU time 0.78 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 195340 kb
Host smart-dbc37680-2d4c-43e3-a9c7-e718946f50d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108077676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.108077676
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.280306369
Short name T658
Test name
Test status
Simulation time 438459014 ps
CPU time 22.72 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:36 PM PDT 24
Peak memory 197856 kb
Host smart-46ebaf17-d24a-43da-ab13-4279fb55e2e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280306369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stres
s.280306369
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.418780253
Short name T484
Test name
Test status
Simulation time 72364543 ps
CPU time 0.93 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:13 PM PDT 24
Peak memory 196160 kb
Host smart-bbfadc2c-4082-4498-a0b2-f5a041856c64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418780253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.418780253
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.391945811
Short name T70
Test name
Test status
Simulation time 114447928 ps
CPU time 1.02 seconds
Started May 19 12:25:04 PM PDT 24
Finished May 19 12:25:11 PM PDT 24
Peak memory 195660 kb
Host smart-13bb538d-9c33-4f77-a2af-166fe496c93c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391945811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.391945811
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.1572727502
Short name T102
Test name
Test status
Simulation time 66486484 ps
CPU time 0.96 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:22 PM PDT 24
Peak memory 196484 kb
Host smart-d49b784d-ec2d-4844-9671-6369628408a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572727502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.1572727502
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1171990964
Short name T521
Test name
Test status
Simulation time 266569855 ps
CPU time 2.92 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:25:01 PM PDT 24
Peak memory 197900 kb
Host smart-124c2e6a-3bbb-48b4-9e39-c88a1835a52a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171990964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1171990964
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.290779370
Short name T194
Test name
Test status
Simulation time 19514216 ps
CPU time 0.81 seconds
Started May 19 12:25:00 PM PDT 24
Finished May 19 12:25:04 PM PDT 24
Peak memory 196496 kb
Host smart-23a9499f-256c-4355-80df-8f09c263645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290779370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.290779370
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.654634337
Short name T479
Test name
Test status
Simulation time 43696215 ps
CPU time 0.68 seconds
Started May 19 12:24:53 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 194112 kb
Host smart-d9e3dd18-4f72-4c2d-a718-b87eff1dd875
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654634337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.654634337
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1146821310
Short name T456
Test name
Test status
Simulation time 100560482 ps
CPU time 1.55 seconds
Started May 19 12:25:08 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 197732 kb
Host smart-c1d63f13-0b80-4a13-81fb-3ecedd9821c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146821310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1146821310
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.30857282
Short name T50
Test name
Test status
Simulation time 84229207 ps
CPU time 0.85 seconds
Started May 19 12:25:01 PM PDT 24
Finished May 19 12:25:06 PM PDT 24
Peak memory 195504 kb
Host smart-c103bc9c-be72-46e1-9ce0-e582d73bf465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30857282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.30857282
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2549707357
Short name T120
Test name
Test status
Simulation time 27110535 ps
CPU time 0.88 seconds
Started May 19 12:25:15 PM PDT 24
Finished May 19 12:25:23 PM PDT 24
Peak memory 197068 kb
Host smart-19d84e22-10ac-48ee-a5f1-c731a460fe7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549707357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2549707357
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.709682193
Short name T183
Test name
Test status
Simulation time 59457200486 ps
CPU time 174.95 seconds
Started May 19 12:25:00 PM PDT 24
Finished May 19 12:27:58 PM PDT 24
Peak memory 197976 kb
Host smart-3c6fb313-7fc7-40a0-a7c6-f07bfc381866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709682193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.709682193
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.978134462
Short name T58
Test name
Test status
Simulation time 780391662259 ps
CPU time 1633.24 seconds
Started May 19 12:25:03 PM PDT 24
Finished May 19 12:52:22 PM PDT 24
Peak memory 198480 kb
Host smart-034d744c-7d48-4762-b244-862c3da11931
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=978134462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.978134462
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.118222299
Short name T631
Test name
Test status
Simulation time 14843869 ps
CPU time 0.57 seconds
Started May 19 12:24:56 PM PDT 24
Finished May 19 12:25:01 PM PDT 24
Peak memory 193908 kb
Host smart-21f1c1a1-54ee-4708-b8fb-44cbcbb2a312
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118222299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.118222299
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3098587048
Short name T205
Test name
Test status
Simulation time 74585907 ps
CPU time 0.67 seconds
Started May 19 12:24:55 PM PDT 24
Finished May 19 12:25:00 PM PDT 24
Peak memory 194832 kb
Host smart-fc8ba9f1-7def-4d88-ba8b-170bb4de2613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098587048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3098587048
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3058362240
Short name T370
Test name
Test status
Simulation time 2673571254 ps
CPU time 17.95 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 196632 kb
Host smart-73bc41f0-8914-4e51-8779-9fa5650908f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058362240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3058362240
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2586787517
Short name T241
Test name
Test status
Simulation time 152172730 ps
CPU time 0.74 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:22 PM PDT 24
Peak memory 195728 kb
Host smart-b6ca84bb-14a0-4352-b8ab-ff01ec7bbc80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586787517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2586787517
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1338363812
Short name T380
Test name
Test status
Simulation time 210847870 ps
CPU time 1.26 seconds
Started May 19 12:25:03 PM PDT 24
Finished May 19 12:25:10 PM PDT 24
Peak memory 197444 kb
Host smart-44b62cc4-5644-499f-8e47-5463421927ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338363812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1338363812
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.1378545856
Short name T221
Test name
Test status
Simulation time 64278074 ps
CPU time 1.34 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 196536 kb
Host smart-18467013-b991-42f0-96a8-94ec24b4c6ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378545856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.1378545856
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1759255274
Short name T610
Test name
Test status
Simulation time 29567803 ps
CPU time 0.86 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:22 PM PDT 24
Peak memory 194204 kb
Host smart-bf0e145f-d7e6-4c64-a6b1-ded361a65391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759255274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1759255274
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4294134656
Short name T209
Test name
Test status
Simulation time 53049929 ps
CPU time 1.2 seconds
Started May 19 12:24:53 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 196944 kb
Host smart-b26e6c82-d50b-476e-8730-a53a4730e2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294134656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4294134656
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1093595528
Short name T474
Test name
Test status
Simulation time 137402030 ps
CPU time 1.16 seconds
Started May 19 12:24:56 PM PDT 24
Finished May 19 12:25:01 PM PDT 24
Peak memory 196372 kb
Host smart-ec35c9cb-7736-4af3-b1fd-69210e60e349
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093595528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1093595528
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.588803981
Short name T322
Test name
Test status
Simulation time 293070060 ps
CPU time 4.42 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 197712 kb
Host smart-3a11ecce-2417-4b8d-aaf8-6f5bda969f23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588803981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.588803981
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.468769699
Short name T614
Test name
Test status
Simulation time 42798385 ps
CPU time 1.11 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:15 PM PDT 24
Peak memory 196128 kb
Host smart-059722ef-1639-4512-b1db-489c4ac189bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468769699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.468769699
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1768643087
Short name T428
Test name
Test status
Simulation time 80323028 ps
CPU time 0.89 seconds
Started May 19 12:25:00 PM PDT 24
Finished May 19 12:25:12 PM PDT 24
Peak memory 196144 kb
Host smart-c16dab8a-2f97-4289-8192-dac89e66854b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768643087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1768643087
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3702715149
Short name T122
Test name
Test status
Simulation time 8898867095 ps
CPU time 114.77 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:27:18 PM PDT 24
Peak memory 197920 kb
Host smart-abb70b89-77b5-412b-9675-460530937ee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702715149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3702715149
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2280956984
Short name T401
Test name
Test status
Simulation time 42929655 ps
CPU time 0.59 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 194592 kb
Host smart-c1acc489-47d2-4731-bd8a-6b1d3e7efb11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280956984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2280956984
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.4092862146
Short name T684
Test name
Test status
Simulation time 61124754 ps
CPU time 0.7 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 193956 kb
Host smart-7aa68434-2d5b-41e9-ade0-81533f5cccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092862146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.4092862146
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.846207687
Short name T652
Test name
Test status
Simulation time 6013321565 ps
CPU time 20.31 seconds
Started May 19 12:25:03 PM PDT 24
Finished May 19 12:25:29 PM PDT 24
Peak memory 196428 kb
Host smart-d58182ef-b700-4f12-8375-0586ba59d6b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846207687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.846207687
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.4264382404
Short name T559
Test name
Test status
Simulation time 60012953 ps
CPU time 0.76 seconds
Started May 19 12:25:07 PM PDT 24
Finished May 19 12:25:15 PM PDT 24
Peak memory 195700 kb
Host smart-1c434154-420f-4281-8c77-47b99d54e88e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264382404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.4264382404
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.4263568801
Short name T673
Test name
Test status
Simulation time 49252509 ps
CPU time 1.31 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 197920 kb
Host smart-50be3692-4a17-4a03-9113-c6a5c2e4611e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263568801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.4263568801
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1442701216
Short name T257
Test name
Test status
Simulation time 73279751 ps
CPU time 2.62 seconds
Started May 19 12:25:08 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 197872 kb
Host smart-755b4645-48d2-4152-9dda-c13106777fac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442701216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1442701216
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2878844650
Short name T384
Test name
Test status
Simulation time 566330483 ps
CPU time 3 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 196916 kb
Host smart-d6578ce5-f70c-4b00-9ce8-b56e67dfaf8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878844650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2878844650
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2442419531
Short name T688
Test name
Test status
Simulation time 127039198 ps
CPU time 0.75 seconds
Started May 19 12:25:16 PM PDT 24
Finished May 19 12:25:24 PM PDT 24
Peak memory 195292 kb
Host smart-ac0e9c2d-8abe-4816-afbe-1ea811b89503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442419531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2442419531
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.166613937
Short name T261
Test name
Test status
Simulation time 23754646 ps
CPU time 0.86 seconds
Started May 19 12:25:19 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 195812 kb
Host smart-c0725aa4-32df-4dad-820e-a1b052a67f57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166613937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.166613937
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1017205822
Short name T439
Test name
Test status
Simulation time 212651423 ps
CPU time 3.46 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:15 PM PDT 24
Peak memory 197728 kb
Host smart-f073fbde-96a9-41fe-832d-3846845b9326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017205822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1017205822
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.2828691619
Short name T330
Test name
Test status
Simulation time 83426508 ps
CPU time 1.11 seconds
Started May 19 12:25:11 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 195692 kb
Host smart-f15095da-e733-422b-86fb-fe2d62bf29a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828691619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.2828691619
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3898676113
Short name T317
Test name
Test status
Simulation time 70415483 ps
CPU time 1.01 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:13 PM PDT 24
Peak memory 195560 kb
Host smart-816411df-4f36-409a-8069-544256aab4dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898676113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3898676113
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1383388987
Short name T424
Test name
Test status
Simulation time 108550358293 ps
CPU time 211.49 seconds
Started May 19 12:25:04 PM PDT 24
Finished May 19 12:28:41 PM PDT 24
Peak memory 198020 kb
Host smart-9ec9d1ae-0ed6-45a9-b156-52d18da75811
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383388987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1383388987
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1845726975
Short name T513
Test name
Test status
Simulation time 16582577 ps
CPU time 0.58 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:13 PM PDT 24
Peak memory 193680 kb
Host smart-a1ddb83a-7302-45c4-96dd-7d2a170b40e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845726975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1845726975
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.4035569748
Short name T587
Test name
Test status
Simulation time 163251580 ps
CPU time 0.81 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 194976 kb
Host smart-c71204b9-2210-4fa6-bd98-b8c99d014925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035569748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.4035569748
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.506233096
Short name T67
Test name
Test status
Simulation time 307413337 ps
CPU time 8.51 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 196480 kb
Host smart-814d7c80-6aa8-477a-a04d-c9e3842dbdbb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506233096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.506233096
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.3624932849
Short name T469
Test name
Test status
Simulation time 269710135 ps
CPU time 0.78 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:13 PM PDT 24
Peak memory 195976 kb
Host smart-a253be7e-cf5e-4fea-ac4a-9fd6b49af7dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624932849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.3624932849
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.463464709
Short name T680
Test name
Test status
Simulation time 84617258 ps
CPU time 0.85 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 197708 kb
Host smart-ba4ae940-3257-4b02-a9a1-cd0494159b16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463464709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.463464709
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3789852455
Short name T640
Test name
Test status
Simulation time 31610300 ps
CPU time 1.27 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 197936 kb
Host smart-8a1e1eea-38ed-4eac-a284-fb8f3e0fc0b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789852455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3789852455
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2738068293
Short name T649
Test name
Test status
Simulation time 199044952 ps
CPU time 2.9 seconds
Started May 19 12:25:30 PM PDT 24
Finished May 19 12:25:35 PM PDT 24
Peak memory 196960 kb
Host smart-043b36a6-c208-4093-91b8-664fc270c031
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738068293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2738068293
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.2455859142
Short name T641
Test name
Test status
Simulation time 19770271 ps
CPU time 0.71 seconds
Started May 19 12:24:54 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 195980 kb
Host smart-d16918f5-247f-481e-8d07-51148aee6dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455859142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.2455859142
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1691188234
Short name T275
Test name
Test status
Simulation time 99601456 ps
CPU time 1 seconds
Started May 19 12:25:08 PM PDT 24
Finished May 19 12:25:17 PM PDT 24
Peak memory 196456 kb
Host smart-cdadb546-6784-47d3-b96b-3d2a11b2c3e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691188234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1691188234
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.281174865
Short name T128
Test name
Test status
Simulation time 146153752 ps
CPU time 1.56 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:23 PM PDT 24
Peak memory 197788 kb
Host smart-8289b47e-eb9a-491d-bbc7-217ba9ffd6f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281174865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.281174865
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4049491456
Short name T508
Test name
Test status
Simulation time 171650487 ps
CPU time 0.95 seconds
Started May 19 12:25:04 PM PDT 24
Finished May 19 12:25:10 PM PDT 24
Peak memory 195484 kb
Host smart-69b54d36-8b8e-4268-9fb3-fd02dab5c03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049491456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4049491456
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.3619753107
Short name T321
Test name
Test status
Simulation time 52250435 ps
CPU time 1.07 seconds
Started May 19 12:24:55 PM PDT 24
Finished May 19 12:25:00 PM PDT 24
Peak memory 195492 kb
Host smart-df0dee2d-5f7c-452b-b69b-f0c761819898
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619753107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.3619753107
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2394148450
Short name T368
Test name
Test status
Simulation time 18294492564 ps
CPU time 126.34 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:27:27 PM PDT 24
Peak memory 198004 kb
Host smart-7317f8c0-ace5-46b6-a188-37a8df299c47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394148450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2394148450
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1243292955
Short name T37
Test name
Test status
Simulation time 128607996 ps
CPU time 0.54 seconds
Started May 19 12:25:01 PM PDT 24
Finished May 19 12:25:04 PM PDT 24
Peak memory 193728 kb
Host smart-d0438972-d34e-4505-9ce1-cb15c93edff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243292955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1243292955
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.4168445964
Short name T529
Test name
Test status
Simulation time 73217950 ps
CPU time 0.7 seconds
Started May 19 12:25:12 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 195444 kb
Host smart-c36bddc0-6dc0-4f4f-bb49-daaaa6702e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168445964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.4168445964
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.991338476
Short name T590
Test name
Test status
Simulation time 987904652 ps
CPU time 26.59 seconds
Started May 19 12:25:04 PM PDT 24
Finished May 19 12:25:36 PM PDT 24
Peak memory 195376 kb
Host smart-5fb1dab1-c1f8-434c-8134-15bf5b322ac6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991338476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.991338476
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2245109622
Short name T571
Test name
Test status
Simulation time 141489591 ps
CPU time 0.92 seconds
Started May 19 12:25:32 PM PDT 24
Finished May 19 12:25:34 PM PDT 24
Peak memory 197764 kb
Host smart-ec3b3826-e989-43d8-847a-e56097e93d97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245109622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2245109622
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.526862439
Short name T459
Test name
Test status
Simulation time 51660414 ps
CPU time 0.83 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:20 PM PDT 24
Peak memory 195292 kb
Host smart-916611a5-c9cb-426f-91b6-06539fab151e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526862439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.526862439
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1644774217
Short name T573
Test name
Test status
Simulation time 90740554 ps
CPU time 3.23 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:20 PM PDT 24
Peak memory 197924 kb
Host smart-004ffc83-d421-4492-9ab0-ef659ca5ef3d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644774217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1644774217
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.772291091
Short name T597
Test name
Test status
Simulation time 96491568 ps
CPU time 1.22 seconds
Started May 19 12:25:06 PM PDT 24
Finished May 19 12:25:14 PM PDT 24
Peak memory 196512 kb
Host smart-d259b422-ebc1-4e8c-86fc-8934324362ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772291091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
772291091
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1081747392
Short name T403
Test name
Test status
Simulation time 82681124 ps
CPU time 1 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:13 PM PDT 24
Peak memory 195852 kb
Host smart-b972039f-8d67-4d2e-8866-c380a1909dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081747392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1081747392
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3066614553
Short name T46
Test name
Test status
Simulation time 19392874 ps
CPU time 0.66 seconds
Started May 19 12:25:13 PM PDT 24
Finished May 19 12:25:22 PM PDT 24
Peak memory 194236 kb
Host smart-afc0fa90-f7c7-45d6-9254-d498f8636a80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066614553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3066614553
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1658092270
Short name T165
Test name
Test status
Simulation time 44583589 ps
CPU time 1.1 seconds
Started May 19 12:25:19 PM PDT 24
Finished May 19 12:25:26 PM PDT 24
Peak memory 197864 kb
Host smart-2ed33afd-1ea5-41ac-a673-31c6a063b649
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658092270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1658092270
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1842726258
Short name T309
Test name
Test status
Simulation time 392613296 ps
CPU time 0.84 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:25:13 PM PDT 24
Peak memory 195268 kb
Host smart-bd40c80e-cd44-48ad-b863-7c14473bc3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842726258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1842726258
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.122167874
Short name T611
Test name
Test status
Simulation time 58731439 ps
CPU time 1.04 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:18 PM PDT 24
Peak memory 196316 kb
Host smart-02d00885-5b3c-42c9-9519-cba7c71e8b9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122167874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.122167874
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2340792307
Short name T312
Test name
Test status
Simulation time 11067733136 ps
CPU time 147.33 seconds
Started May 19 12:25:05 PM PDT 24
Finished May 19 12:27:39 PM PDT 24
Peak memory 198004 kb
Host smart-26e855c5-fd5c-4359-8487-4051e58bc9ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340792307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2340792307
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1445729024
Short name T438
Test name
Test status
Simulation time 40284719391 ps
CPU time 820.91 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:38:58 PM PDT 24
Peak memory 198044 kb
Host smart-cd5d5ac4-31d9-4985-b907-33b6fd92cfca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1445729024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1445729024
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.196832909
Short name T470
Test name
Test status
Simulation time 12330050 ps
CPU time 0.54 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:18 PM PDT 24
Peak memory 194432 kb
Host smart-a63c627e-611c-42bd-8bac-372e144ae575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196832909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.196832909
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3174648439
Short name T108
Test name
Test status
Simulation time 173791599 ps
CPU time 0.88 seconds
Started May 19 12:25:10 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 196240 kb
Host smart-6e631fe1-412f-49c5-a823-637c105b8f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174648439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3174648439
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.994749883
Short name T60
Test name
Test status
Simulation time 361987516 ps
CPU time 11.85 seconds
Started May 19 12:25:33 PM PDT 24
Finished May 19 12:25:45 PM PDT 24
Peak memory 195352 kb
Host smart-b8e113d5-d0e8-420d-b2b1-db85bf1fe8df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994749883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.994749883
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1894085436
Short name T212
Test name
Test status
Simulation time 43995525 ps
CPU time 0.62 seconds
Started May 19 12:25:08 PM PDT 24
Finished May 19 12:25:16 PM PDT 24
Peak memory 194980 kb
Host smart-5d1cf316-9d4b-4795-9f90-18c36a959ded
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894085436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1894085436
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2712809976
Short name T254
Test name
Test status
Simulation time 71035050 ps
CPU time 0.74 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:25:25 PM PDT 24
Peak memory 196052 kb
Host smart-7c482efc-82b5-46e3-98be-6f8c4fc97ed9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712809976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2712809976
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3640492805
Short name T354
Test name
Test status
Simulation time 1501385515 ps
CPU time 2.94 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:09 PM PDT 24
Peak memory 197844 kb
Host smart-c3f1f712-aac3-4cd3-a783-6d3011061a4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640492805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3640492805
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3015548458
Short name T115
Test name
Test status
Simulation time 388509819 ps
CPU time 2.94 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:19 PM PDT 24
Peak memory 197688 kb
Host smart-3615867a-670d-41d9-9dc7-62037baa3e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015548458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3015548458
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3941512930
Short name T178
Test name
Test status
Simulation time 28133887 ps
CPU time 0.99 seconds
Started May 19 12:25:12 PM PDT 24
Finished May 19 12:25:21 PM PDT 24
Peak memory 195812 kb
Host smart-6ebed27c-e348-43f9-93cf-d4baabb5c515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941512930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3941512930
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.853096804
Short name T253
Test name
Test status
Simulation time 122625912 ps
CPU time 1.25 seconds
Started May 19 12:25:15 PM PDT 24
Finished May 19 12:25:23 PM PDT 24
Peak memory 195680 kb
Host smart-1dd51933-5727-4620-87a3-2d754f67bf22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853096804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.853096804
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2307593383
Short name T326
Test name
Test status
Simulation time 344363221 ps
CPU time 3.79 seconds
Started May 19 12:25:19 PM PDT 24
Finished May 19 12:25:29 PM PDT 24
Peak memory 197880 kb
Host smart-4a9dcedc-983e-4e85-abb5-c439e7586f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307593383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2307593383
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2799021713
Short name T125
Test name
Test status
Simulation time 30801229 ps
CPU time 0.72 seconds
Started May 19 12:25:09 PM PDT 24
Finished May 19 12:25:18 PM PDT 24
Peak memory 195812 kb
Host smart-447542b8-d9d4-4ba7-bee0-d035fa0dd582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799021713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2799021713
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1455873972
Short name T422
Test name
Test status
Simulation time 59307446 ps
CPU time 1.26 seconds
Started May 19 12:25:00 PM PDT 24
Finished May 19 12:25:04 PM PDT 24
Peak memory 196464 kb
Host smart-e9188633-5c79-4012-8299-e13d8e387530
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455873972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1455873972
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.4133684222
Short name T155
Test name
Test status
Simulation time 182921239062 ps
CPU time 180.42 seconds
Started May 19 12:25:17 PM PDT 24
Finished May 19 12:28:25 PM PDT 24
Peak memory 198112 kb
Host smart-f51b8abc-6325-439f-9f89-af9263d49c72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133684222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.4133684222
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.3066618757
Short name T216
Test name
Test status
Simulation time 13704574 ps
CPU time 0.57 seconds
Started May 19 12:23:15 PM PDT 24
Finished May 19 12:23:19 PM PDT 24
Peak memory 194400 kb
Host smart-e59892b7-9ba2-4bb9-96e3-f4bb299a7341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066618757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.3066618757
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2712318099
Short name T497
Test name
Test status
Simulation time 56960983 ps
CPU time 0.98 seconds
Started May 19 12:23:24 PM PDT 24
Finished May 19 12:23:40 PM PDT 24
Peak memory 196936 kb
Host smart-0935884d-4fbc-4259-8989-fb6f044ca9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712318099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2712318099
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2145511513
Short name T418
Test name
Test status
Simulation time 153853023 ps
CPU time 8.28 seconds
Started May 19 12:23:09 PM PDT 24
Finished May 19 12:23:20 PM PDT 24
Peak memory 195732 kb
Host smart-a6d84172-0f68-4202-812d-b966e8416bc5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145511513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2145511513
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1358888364
Short name T487
Test name
Test status
Simulation time 64490945 ps
CPU time 0.73 seconds
Started May 19 12:23:04 PM PDT 24
Finished May 19 12:23:06 PM PDT 24
Peak memory 194588 kb
Host smart-7b9173ec-4419-4026-893c-38ad0e77f971
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358888364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1358888364
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1404364573
Short name T117
Test name
Test status
Simulation time 110255406 ps
CPU time 0.98 seconds
Started May 19 12:23:16 PM PDT 24
Finished May 19 12:23:22 PM PDT 24
Peak memory 197032 kb
Host smart-9108f126-5320-4231-b6b1-8f6449102691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404364573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1404364573
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2085184695
Short name T568
Test name
Test status
Simulation time 397988233 ps
CPU time 3.02 seconds
Started May 19 12:23:30 PM PDT 24
Finished May 19 12:23:54 PM PDT 24
Peak memory 198012 kb
Host smart-b6f9f400-9e30-43ff-bb62-2eb7641d0ad2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085184695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2085184695
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1182913789
Short name T146
Test name
Test status
Simulation time 36442817 ps
CPU time 1.01 seconds
Started May 19 12:23:05 PM PDT 24
Finished May 19 12:23:08 PM PDT 24
Peak memory 195888 kb
Host smart-9bf31300-1b48-438d-9cd2-c58859f68195
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182913789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1182913789
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.631994726
Short name T197
Test name
Test status
Simulation time 98966291 ps
CPU time 1.11 seconds
Started May 19 12:23:12 PM PDT 24
Finished May 19 12:23:17 PM PDT 24
Peak memory 195548 kb
Host smart-e72d5b1a-63e6-47cc-a438-7132f656a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631994726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.631994726
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.910949547
Short name T132
Test name
Test status
Simulation time 51395411 ps
CPU time 1.13 seconds
Started May 19 12:23:16 PM PDT 24
Finished May 19 12:23:22 PM PDT 24
Peak memory 196056 kb
Host smart-8f6709b2-211b-4d9e-96da-a06dfb51fb5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910949547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup_
pulldown.910949547
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.651069415
Short name T288
Test name
Test status
Simulation time 215489474 ps
CPU time 1.39 seconds
Started May 19 12:23:36 PM PDT 24
Finished May 19 12:23:58 PM PDT 24
Peak memory 197724 kb
Host smart-b173ccfd-f572-4d8b-8e71-bac518085021
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651069415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand
om_long_reg_writes_reg_reads.651069415
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.4241829292
Short name T490
Test name
Test status
Simulation time 222593498 ps
CPU time 1.07 seconds
Started May 19 12:22:57 PM PDT 24
Finished May 19 12:22:59 PM PDT 24
Peak memory 196200 kb
Host smart-8cd5a5f6-b462-4f7d-b603-e2b535080a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241829292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.4241829292
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.453665078
Short name T506
Test name
Test status
Simulation time 226437232 ps
CPU time 1.09 seconds
Started May 19 12:23:08 PM PDT 24
Finished May 19 12:23:11 PM PDT 24
Peak memory 196448 kb
Host smart-0f6fa6b4-7263-44c0-a894-10f4af50dbaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453665078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.453665078
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3414829376
Short name T19
Test name
Test status
Simulation time 19220262241 ps
CPU time 43.24 seconds
Started May 19 12:23:16 PM PDT 24
Finished May 19 12:24:04 PM PDT 24
Peak memory 197964 kb
Host smart-86de8e29-6817-4006-bcee-8777b783b040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414829376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3414829376
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.4257867523
Short name T482
Test name
Test status
Simulation time 45513689147 ps
CPU time 973.05 seconds
Started May 19 12:23:03 PM PDT 24
Finished May 19 12:39:17 PM PDT 24
Peak memory 198488 kb
Host smart-d9506c52-901c-4e8b-bc35-9ae68f69366a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4257867523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.4257867523
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2145427650
Short name T366
Test name
Test status
Simulation time 20337312 ps
CPU time 0.56 seconds
Started May 19 12:25:03 PM PDT 24
Finished May 19 12:25:10 PM PDT 24
Peak memory 192752 kb
Host smart-0dd2a441-1ed7-4c4b-9950-248225484cad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145427650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2145427650
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1727746587
Short name T436
Test name
Test status
Simulation time 81628121 ps
CPU time 0.76 seconds
Started May 19 12:23:17 PM PDT 24
Finished May 19 12:23:22 PM PDT 24
Peak memory 195932 kb
Host smart-50e18283-aa90-4190-8a34-a851c0efe27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727746587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1727746587
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4158384236
Short name T225
Test name
Test status
Simulation time 1430533984 ps
CPU time 12.53 seconds
Started May 19 12:23:40 PM PDT 24
Finished May 19 12:24:11 PM PDT 24
Peak memory 197744 kb
Host smart-c2e00552-52ac-4439-976b-f285ac1bd9f7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158384236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4158384236
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1809010316
Short name T255
Test name
Test status
Simulation time 83903267 ps
CPU time 1.08 seconds
Started May 19 12:23:12 PM PDT 24
Finished May 19 12:23:18 PM PDT 24
Peak memory 196820 kb
Host smart-d4877a1b-b3f2-4bef-93ad-340183c2f071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809010316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1809010316
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3146762496
Short name T200
Test name
Test status
Simulation time 331659327 ps
CPU time 1.25 seconds
Started May 19 12:23:08 PM PDT 24
Finished May 19 12:23:12 PM PDT 24
Peak memory 196308 kb
Host smart-be9a22f7-f24e-4125-b71d-b9e15d3ba046
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146762496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3146762496
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.4065118618
Short name T336
Test name
Test status
Simulation time 559563673 ps
CPU time 2.72 seconds
Started May 19 12:23:10 PM PDT 24
Finished May 19 12:23:16 PM PDT 24
Peak memory 198020 kb
Host smart-e2ea2422-9ccf-4f66-b674-8e46c0c1530e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065118618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.4065118618
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1321280406
Short name T284
Test name
Test status
Simulation time 780405097 ps
CPU time 1.44 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 196276 kb
Host smart-096f88cb-0802-46bb-8f50-b9764a018f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321280406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1321280406
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.378618397
Short name T268
Test name
Test status
Simulation time 85594457 ps
CPU time 0.85 seconds
Started May 19 12:23:05 PM PDT 24
Finished May 19 12:23:08 PM PDT 24
Peak memory 196460 kb
Host smart-08b1d115-f400-406e-91f2-f7bd30829680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378618397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.378618397
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.1557338452
Short name T377
Test name
Test status
Simulation time 15058373 ps
CPU time 0.62 seconds
Started May 19 12:23:30 PM PDT 24
Finished May 19 12:23:51 PM PDT 24
Peak memory 194220 kb
Host smart-17294226-ad64-4b1f-b1b6-84df9de48bde
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557338452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.1557338452
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3574345891
Short name T169
Test name
Test status
Simulation time 416084724 ps
CPU time 4.27 seconds
Started May 19 12:24:50 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 197612 kb
Host smart-c1af997f-083c-4874-831e-fd55167827a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574345891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3574345891
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.669711316
Short name T434
Test name
Test status
Simulation time 44099870 ps
CPU time 0.93 seconds
Started May 19 12:23:07 PM PDT 24
Finished May 19 12:23:10 PM PDT 24
Peak memory 195404 kb
Host smart-442f85e1-1540-4519-8c40-dd5880ea49ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669711316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.669711316
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1633117234
Short name T308
Test name
Test status
Simulation time 72348517 ps
CPU time 1.35 seconds
Started May 19 12:23:16 PM PDT 24
Finished May 19 12:23:22 PM PDT 24
Peak memory 196540 kb
Host smart-0b60a3ba-b576-4157-9f4f-a13f4590c336
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633117234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1633117234
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.340425056
Short name T528
Test name
Test status
Simulation time 15963668790 ps
CPU time 210.45 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:27:26 PM PDT 24
Peak memory 198388 kb
Host smart-caf30483-a0fb-48b5-abb7-27c7f1bb6fd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340425056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.340425056
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3674012578
Short name T391
Test name
Test status
Simulation time 17182525 ps
CPU time 0.54 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:07 PM PDT 24
Peak memory 192332 kb
Host smart-d65eb834-7d43-40a1-9325-1323c395dffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674012578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3674012578
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.517996707
Short name T481
Test name
Test status
Simulation time 38706706 ps
CPU time 0.88 seconds
Started May 19 12:23:47 PM PDT 24
Finished May 19 12:24:02 PM PDT 24
Peak memory 196224 kb
Host smart-5822e116-a5a5-4731-823a-026f457ea208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517996707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.517996707
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1733078620
Short name T387
Test name
Test status
Simulation time 1805950130 ps
CPU time 15.84 seconds
Started May 19 12:23:16 PM PDT 24
Finished May 19 12:23:36 PM PDT 24
Peak memory 196816 kb
Host smart-67acf063-a7f9-4c56-9952-ac430ed8fe02
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733078620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1733078620
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2780243197
Short name T355
Test name
Test status
Simulation time 78748345 ps
CPU time 0.96 seconds
Started May 19 12:23:15 PM PDT 24
Finished May 19 12:23:21 PM PDT 24
Peak memory 197828 kb
Host smart-163515d9-0fdb-42ea-a4f2-2ca3c71b7a70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780243197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2780243197
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.2444786564
Short name T705
Test name
Test status
Simulation time 52854095 ps
CPU time 0.78 seconds
Started May 19 12:23:40 PM PDT 24
Finished May 19 12:23:59 PM PDT 24
Peak memory 195200 kb
Host smart-14fec3cf-563c-4951-9e55-0070aa48aef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444786564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.2444786564
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1900324747
Short name T520
Test name
Test status
Simulation time 318155084 ps
CPU time 2.14 seconds
Started May 19 12:23:10 PM PDT 24
Finished May 19 12:23:16 PM PDT 24
Peak memory 197860 kb
Host smart-7d56a8d3-6a8c-4339-95de-81afa97c1f35
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900324747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1900324747
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.569458060
Short name T670
Test name
Test status
Simulation time 439111499 ps
CPU time 2.13 seconds
Started May 19 12:24:53 PM PDT 24
Finished May 19 12:24:59 PM PDT 24
Peak memory 196572 kb
Host smart-2efcd159-25a4-44c7-874c-38114debcb51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569458060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.569458060
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3209041613
Short name T116
Test name
Test status
Simulation time 38404145 ps
CPU time 0.95 seconds
Started May 19 12:24:53 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 195144 kb
Host smart-1c7f70d7-23fb-46de-81b4-b9abe4244167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209041613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3209041613
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1383117299
Short name T130
Test name
Test status
Simulation time 25118940 ps
CPU time 0.65 seconds
Started May 19 12:23:22 PM PDT 24
Finished May 19 12:23:31 PM PDT 24
Peak memory 194152 kb
Host smart-6cf7ec00-847e-40c3-a1cc-c8df731bca13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383117299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1383117299
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3538245241
Short name T659
Test name
Test status
Simulation time 137467696 ps
CPU time 1.72 seconds
Started May 19 12:24:31 PM PDT 24
Finished May 19 12:24:41 PM PDT 24
Peak memory 197228 kb
Host smart-ae7332f7-4d32-423c-a662-bf1ce6f1d1d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538245241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3538245241
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3794515835
Short name T110
Test name
Test status
Simulation time 275584745 ps
CPU time 1.33 seconds
Started May 19 12:24:52 PM PDT 24
Finished May 19 12:24:58 PM PDT 24
Peak memory 194004 kb
Host smart-44c51d87-3768-4271-a814-53e2a67a82c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794515835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3794515835
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2626787906
Short name T420
Test name
Test status
Simulation time 84344795 ps
CPU time 1.37 seconds
Started May 19 12:23:40 PM PDT 24
Finished May 19 12:24:00 PM PDT 24
Peak memory 196288 kb
Host smart-77ee64fd-dd8d-4203-8453-c678c0b7e854
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626787906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2626787906
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.917661998
Short name T140
Test name
Test status
Simulation time 10519508946 ps
CPU time 134.27 seconds
Started May 19 12:24:32 PM PDT 24
Finished May 19 12:27:01 PM PDT 24
Peak memory 197784 kb
Host smart-7b547a67-9e13-4a84-9273-040538e49b43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917661998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.917661998
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2579246465
Short name T61
Test name
Test status
Simulation time 41065380137 ps
CPU time 617.86 seconds
Started May 19 12:23:17 PM PDT 24
Finished May 19 12:33:40 PM PDT 24
Peak memory 198068 kb
Host smart-cb0295c6-7d6b-44af-ac79-57dbc4457a0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2579246465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2579246465
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.3607904454
Short name T616
Test name
Test status
Simulation time 16871178 ps
CPU time 0.66 seconds
Started May 19 12:23:18 PM PDT 24
Finished May 19 12:23:25 PM PDT 24
Peak memory 193928 kb
Host smart-3244eac7-fe41-48e5-9c46-625b52a9bd31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607904454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.3607904454
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3553204071
Short name T323
Test name
Test status
Simulation time 54207892 ps
CPU time 0.63 seconds
Started May 19 12:23:27 PM PDT 24
Finished May 19 12:23:47 PM PDT 24
Peak memory 193876 kb
Host smart-0c57ddc5-7c60-4068-aa20-9924552bca4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553204071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3553204071
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1441739118
Short name T316
Test name
Test status
Simulation time 2735816473 ps
CPU time 6.33 seconds
Started May 19 12:23:36 PM PDT 24
Finished May 19 12:24:03 PM PDT 24
Peak memory 196864 kb
Host smart-4f1c70b0-205e-45ba-82a7-1a6c66592d88
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441739118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1441739118
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1284347664
Short name T211
Test name
Test status
Simulation time 112244322 ps
CPU time 1.47 seconds
Started May 19 12:23:33 PM PDT 24
Finished May 19 12:23:54 PM PDT 24
Peak memory 196032 kb
Host smart-20191602-0e18-459f-bb9a-9ce5ef220dc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284347664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1284347664
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3215179409
Short name T527
Test name
Test status
Simulation time 157794146 ps
CPU time 3.65 seconds
Started May 19 12:24:58 PM PDT 24
Finished May 19 12:25:05 PM PDT 24
Peak memory 195920 kb
Host smart-ab6e288e-5da9-4b15-8cd7-c852150f9ac7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215179409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3215179409
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1197051118
Short name T483
Test name
Test status
Simulation time 338418018 ps
CPU time 1.81 seconds
Started May 19 12:23:18 PM PDT 24
Finished May 19 12:23:26 PM PDT 24
Peak memory 196220 kb
Host smart-d84a863f-02c4-4bea-812b-79d0d731858e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197051118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1197051118
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3398129167
Short name T494
Test name
Test status
Simulation time 22263157 ps
CPU time 0.95 seconds
Started May 19 12:23:45 PM PDT 24
Finished May 19 12:24:01 PM PDT 24
Peak memory 196600 kb
Host smart-9d1ce318-77d0-4856-a7d6-7e2b27faddaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398129167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3398129167
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.4116257409
Short name T457
Test name
Test status
Simulation time 127709591 ps
CPU time 1.13 seconds
Started May 19 12:23:35 PM PDT 24
Finished May 19 12:23:56 PM PDT 24
Peak memory 196832 kb
Host smart-b4401b83-0ed4-4ca0-b80a-d77a4eb3c126
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116257409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.4116257409
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.827641472
Short name T126
Test name
Test status
Simulation time 130793050 ps
CPU time 2.89 seconds
Started May 19 12:23:21 PM PDT 24
Finished May 19 12:23:32 PM PDT 24
Peak memory 197792 kb
Host smart-b48d307c-f75d-4ffd-98e4-5fb1eecf3a09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827641472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.827641472
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.609665127
Short name T548
Test name
Test status
Simulation time 169167075 ps
CPU time 0.93 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:08 PM PDT 24
Peak memory 196092 kb
Host smart-9e160e61-ce15-4b2a-87c8-91ccff6cb5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609665127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.609665127
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.424087058
Short name T246
Test name
Test status
Simulation time 282824573 ps
CPU time 1.17 seconds
Started May 19 12:23:17 PM PDT 24
Finished May 19 12:23:23 PM PDT 24
Peak memory 195652 kb
Host smart-9eb52ea9-d529-4148-bb8a-f7a39d223e1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424087058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.424087058
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2630937589
Short name T675
Test name
Test status
Simulation time 971175535 ps
CPU time 24.38 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:30 PM PDT 24
Peak memory 197568 kb
Host smart-72e13946-4e9e-40d6-a920-b15e28e9acdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630937589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2630937589
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.1907737183
Short name T440
Test name
Test status
Simulation time 88099820075 ps
CPU time 931.26 seconds
Started May 19 12:23:24 PM PDT 24
Finished May 19 12:39:10 PM PDT 24
Peak memory 197980 kb
Host smart-49aacc77-ff13-4831-80a3-4e79c6b4dcfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1907737183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.1907737183
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1239976338
Short name T259
Test name
Test status
Simulation time 12727772 ps
CPU time 0.6 seconds
Started May 19 12:25:03 PM PDT 24
Finished May 19 12:25:10 PM PDT 24
Peak memory 191844 kb
Host smart-22c12305-aa9d-466b-a237-905db1669319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239976338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1239976338
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2571201469
Short name T581
Test name
Test status
Simulation time 24454803 ps
CPU time 0.72 seconds
Started May 19 12:23:25 PM PDT 24
Finished May 19 12:23:40 PM PDT 24
Peak memory 195772 kb
Host smart-372f1735-4ddc-4405-bbbe-b22683ff72b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571201469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2571201469
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.2434236746
Short name T449
Test name
Test status
Simulation time 799975526 ps
CPU time 13.4 seconds
Started May 19 12:23:26 PM PDT 24
Finished May 19 12:23:55 PM PDT 24
Peak memory 196736 kb
Host smart-c7108042-8cc7-4287-ae50-47d5e2b2dc50
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434236746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.2434236746
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1464094909
Short name T512
Test name
Test status
Simulation time 22435482 ps
CPU time 0.62 seconds
Started May 19 12:23:40 PM PDT 24
Finished May 19 12:23:59 PM PDT 24
Peak memory 194264 kb
Host smart-749df12c-53a1-4390-b10a-f761e80b6b26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464094909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1464094909
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3951191462
Short name T14
Test name
Test status
Simulation time 95312238 ps
CPU time 0.84 seconds
Started May 19 12:23:43 PM PDT 24
Finished May 19 12:24:01 PM PDT 24
Peak memory 196232 kb
Host smart-7c4410d9-77c2-4b70-9ee8-6a2e76ad1595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951191462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3951191462
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.3641161279
Short name T104
Test name
Test status
Simulation time 41253795 ps
CPU time 1.73 seconds
Started May 19 12:23:21 PM PDT 24
Finished May 19 12:23:30 PM PDT 24
Peak memory 198136 kb
Host smart-fbf577ef-ce59-483f-b649-b0679b85fac0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641161279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.3641161279
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.740609894
Short name T107
Test name
Test status
Simulation time 1292447511 ps
CPU time 2.44 seconds
Started May 19 12:25:01 PM PDT 24
Finished May 19 12:25:08 PM PDT 24
Peak memory 194400 kb
Host smart-bc5abf83-bdaf-426c-942b-b00d541a8fd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740609894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.740609894
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.2270414259
Short name T137
Test name
Test status
Simulation time 52503347 ps
CPU time 1.09 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:07 PM PDT 24
Peak memory 196108 kb
Host smart-b51c1171-a492-4369-a67f-cccbe1765fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270414259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.2270414259
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1791925529
Short name T344
Test name
Test status
Simulation time 106069544 ps
CPU time 1.19 seconds
Started May 19 12:25:01 PM PDT 24
Finished May 19 12:25:07 PM PDT 24
Peak memory 196720 kb
Host smart-0288205b-989d-49ba-958c-3b7454971223
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791925529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1791925529
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3766902798
Short name T414
Test name
Test status
Simulation time 252277737 ps
CPU time 3.95 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:11 PM PDT 24
Peak memory 197596 kb
Host smart-b8d34011-f529-4793-ab5e-cc5b8de31066
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766902798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3766902798
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.481547503
Short name T515
Test name
Test status
Simulation time 309760953 ps
CPU time 0.93 seconds
Started May 19 12:25:02 PM PDT 24
Finished May 19 12:25:07 PM PDT 24
Peak memory 195368 kb
Host smart-3e76ec5e-13c2-4f97-b400-66307adcfa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481547503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.481547503
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2634701378
Short name T230
Test name
Test status
Simulation time 90375098 ps
CPU time 0.83 seconds
Started May 19 12:23:22 PM PDT 24
Finished May 19 12:23:33 PM PDT 24
Peak memory 195464 kb
Host smart-a71c7582-7065-4dee-a2a8-406e1b48c6c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634701378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2634701378
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2105847952
Short name T20
Test name
Test status
Simulation time 13230501478 ps
CPU time 112.35 seconds
Started May 19 12:25:03 PM PDT 24
Finished May 19 12:27:02 PM PDT 24
Peak memory 196356 kb
Host smart-1a5d640d-62a1-4e4a-a501-c580e401c91f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105847952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2105847952
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.1549885538
Short name T302
Test name
Test status
Simulation time 65640568118 ps
CPU time 461.79 seconds
Started May 19 12:23:40 PM PDT 24
Finished May 19 12:31:40 PM PDT 24
Peak memory 198116 kb
Host smart-fb89d12f-de55-43d3-a383-67191a088f9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1549885538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.1549885538
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.4251668061
Short name T856
Test name
Test status
Simulation time 135616895 ps
CPU time 1.4 seconds
Started May 19 12:54:27 PM PDT 24
Finished May 19 12:54:31 PM PDT 24
Peak memory 198580 kb
Host smart-7a98f5ec-6797-48e4-94c1-fdf03801d260
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4251668061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.4251668061
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3638278759
Short name T908
Test name
Test status
Simulation time 34367905 ps
CPU time 0.78 seconds
Started May 19 12:54:32 PM PDT 24
Finished May 19 12:54:34 PM PDT 24
Peak memory 196600 kb
Host smart-7af3edf9-484c-4609-9d30-158e2c75735a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638278759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3638278759
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.38035205
Short name T849
Test name
Test status
Simulation time 199556604 ps
CPU time 1.1 seconds
Started May 19 12:54:28 PM PDT 24
Finished May 19 12:54:31 PM PDT 24
Peak memory 192224 kb
Host smart-41675390-6de9-40a0-9f68-f33db5b955fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=38035205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.38035205
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.860766237
Short name T896
Test name
Test status
Simulation time 91153206 ps
CPU time 1.37 seconds
Started May 19 12:54:23 PM PDT 24
Finished May 19 12:54:26 PM PDT 24
Peak memory 192144 kb
Host smart-69081e6b-dae6-47ac-af08-728f911752b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860766237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.860766237
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.493047788
Short name T888
Test name
Test status
Simulation time 76557381 ps
CPU time 1.39 seconds
Started May 19 12:54:41 PM PDT 24
Finished May 19 12:54:43 PM PDT 24
Peak memory 192196 kb
Host smart-15d30024-1cae-4713-a43f-33c8eced69f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=493047788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.493047788
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3402964930
Short name T939
Test name
Test status
Simulation time 232781549 ps
CPU time 1.32 seconds
Started May 19 12:54:37 PM PDT 24
Finished May 19 12:54:40 PM PDT 24
Peak memory 197136 kb
Host smart-d23d90ac-a9f6-49cb-b97c-6209724141ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402964930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3402964930
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2370621057
Short name T929
Test name
Test status
Simulation time 51712410 ps
CPU time 1.01 seconds
Started May 19 12:54:34 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 192204 kb
Host smart-f8c45f04-2458-4fe6-921c-1bc4e430c3dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2370621057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2370621057
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2308934782
Short name T857
Test name
Test status
Simulation time 129295305 ps
CPU time 1.23 seconds
Started May 19 12:54:33 PM PDT 24
Finished May 19 12:54:35 PM PDT 24
Peak memory 192172 kb
Host smart-f022cf25-f1d5-4427-9baf-577d30b6543a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308934782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2308934782
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2420788542
Short name T858
Test name
Test status
Simulation time 300535447 ps
CPU time 0.98 seconds
Started May 19 12:54:38 PM PDT 24
Finished May 19 12:54:40 PM PDT 24
Peak memory 191988 kb
Host smart-cf6b65a6-ca97-4706-89b1-4df6da5e08bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2420788542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2420788542
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3371563965
Short name T937
Test name
Test status
Simulation time 107833620 ps
CPU time 1.48 seconds
Started May 19 12:54:40 PM PDT 24
Finished May 19 12:54:43 PM PDT 24
Peak memory 192220 kb
Host smart-8a289ae3-0862-4d2c-8ed0-9cde726e1905
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371563965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3371563965
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.93081062
Short name T906
Test name
Test status
Simulation time 406116671 ps
CPU time 1.4 seconds
Started May 19 12:54:36 PM PDT 24
Finished May 19 12:54:39 PM PDT 24
Peak memory 192124 kb
Host smart-466d5466-3910-4373-b273-900dcc78bd03
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=93081062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.93081062
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4251285211
Short name T881
Test name
Test status
Simulation time 294317997 ps
CPU time 1.25 seconds
Started May 19 12:54:39 PM PDT 24
Finished May 19 12:54:41 PM PDT 24
Peak memory 192136 kb
Host smart-40670de9-1bf7-4d1b-bfe2-228642b1cf41
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251285211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4251285211
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1260559161
Short name T893
Test name
Test status
Simulation time 299972811 ps
CPU time 0.88 seconds
Started May 19 12:54:38 PM PDT 24
Finished May 19 12:54:40 PM PDT 24
Peak memory 196700 kb
Host smart-de184b95-1374-41d2-b620-267eec1d5a9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1260559161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1260559161
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1462824047
Short name T922
Test name
Test status
Simulation time 58212005 ps
CPU time 1.21 seconds
Started May 19 12:54:44 PM PDT 24
Finished May 19 12:54:46 PM PDT 24
Peak memory 192268 kb
Host smart-60d8b165-14d0-4e8c-85ce-94c1035f0b28
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462824047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1462824047
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.560747768
Short name T878
Test name
Test status
Simulation time 177437671 ps
CPU time 1.4 seconds
Started May 19 12:54:39 PM PDT 24
Finished May 19 12:54:41 PM PDT 24
Peak memory 192020 kb
Host smart-626398b0-2fa1-4181-8d64-51c792f4d7c4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=560747768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.560747768
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.598309727
Short name T910
Test name
Test status
Simulation time 337863557 ps
CPU time 1.54 seconds
Started May 19 12:54:48 PM PDT 24
Finished May 19 12:54:51 PM PDT 24
Peak memory 192292 kb
Host smart-0354d86d-7cf5-46de-8c1b-f0ef683a070f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598309727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.598309727
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2998695408
Short name T868
Test name
Test status
Simulation time 92791590 ps
CPU time 0.96 seconds
Started May 19 12:54:41 PM PDT 24
Finished May 19 12:54:43 PM PDT 24
Peak memory 192052 kb
Host smart-48f8a7af-60d4-4135-ada6-4da01cbbcb8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2998695408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2998695408
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2759415215
Short name T903
Test name
Test status
Simulation time 29593686 ps
CPU time 0.78 seconds
Started May 19 12:54:40 PM PDT 24
Finished May 19 12:54:42 PM PDT 24
Peak memory 192112 kb
Host smart-8462ee37-f15a-4a9d-8717-98e5ac6611b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759415215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2759415215
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3443555246
Short name T865
Test name
Test status
Simulation time 57535743 ps
CPU time 1.06 seconds
Started May 19 12:54:43 PM PDT 24
Finished May 19 12:54:45 PM PDT 24
Peak memory 196888 kb
Host smart-e722dc83-2d0f-49bc-8c57-cc79f6cb5d0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3443555246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3443555246
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1410558760
Short name T920
Test name
Test status
Simulation time 212884135 ps
CPU time 1.14 seconds
Started May 19 12:54:42 PM PDT 24
Finished May 19 12:54:44 PM PDT 24
Peak memory 192288 kb
Host smart-2aeabcce-62e2-430b-b3e4-4ea4aeee7216
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410558760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1410558760
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1762187345
Short name T935
Test name
Test status
Simulation time 362722512 ps
CPU time 0.95 seconds
Started May 19 12:54:46 PM PDT 24
Finished May 19 12:54:49 PM PDT 24
Peak memory 192088 kb
Host smart-833b91a2-2741-4f11-8d82-2a688d1e375c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1762187345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1762187345
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3550805886
Short name T895
Test name
Test status
Simulation time 152263303 ps
CPU time 1.4 seconds
Started May 19 12:54:45 PM PDT 24
Finished May 19 12:54:49 PM PDT 24
Peak memory 197824 kb
Host smart-04d4710c-92c2-4ca2-ae3d-1308d1b8e5fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550805886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3550805886
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1010139470
Short name T861
Test name
Test status
Simulation time 37255326 ps
CPU time 0.84 seconds
Started May 19 12:54:49 PM PDT 24
Finished May 19 12:54:52 PM PDT 24
Peak memory 196464 kb
Host smart-2b5f80a2-960d-40db-ba34-ff94ca6d84a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1010139470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1010139470
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.778019552
Short name T907
Test name
Test status
Simulation time 267934047 ps
CPU time 1.42 seconds
Started May 19 12:54:45 PM PDT 24
Finished May 19 12:54:48 PM PDT 24
Peak memory 192212 kb
Host smart-f1493613-486c-42e6-a664-4317e9d66814
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778019552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.778019552
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1257639717
Short name T846
Test name
Test status
Simulation time 66601756 ps
CPU time 1.22 seconds
Started May 19 12:54:27 PM PDT 24
Finished May 19 12:54:35 PM PDT 24
Peak memory 197228 kb
Host smart-e50e0c3e-e850-4925-973f-21475b0cae08
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1257639717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1257639717
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2707067072
Short name T877
Test name
Test status
Simulation time 46928437 ps
CPU time 0.87 seconds
Started May 19 12:54:37 PM PDT 24
Finished May 19 12:54:40 PM PDT 24
Peak memory 192084 kb
Host smart-81d82eef-e296-46d8-b6d1-d3ff7b8c01cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707067072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2707067072
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1535159143
Short name T852
Test name
Test status
Simulation time 570607823 ps
CPU time 1.61 seconds
Started May 19 12:54:49 PM PDT 24
Finished May 19 12:54:53 PM PDT 24
Peak memory 198520 kb
Host smart-d0d79726-c475-4459-af9c-0ac0620c57a0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1535159143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1535159143
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2497230023
Short name T923
Test name
Test status
Simulation time 47951986 ps
CPU time 0.81 seconds
Started May 19 12:54:49 PM PDT 24
Finished May 19 12:54:51 PM PDT 24
Peak memory 192020 kb
Host smart-87b563df-bcfb-4321-a4a3-532e34d2efed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497230023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2497230023
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2982420454
Short name T864
Test name
Test status
Simulation time 123507030 ps
CPU time 1.47 seconds
Started May 19 12:54:45 PM PDT 24
Finished May 19 12:54:48 PM PDT 24
Peak memory 192248 kb
Host smart-61ca1560-18a8-4e72-9da7-c6b94c1d4567
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2982420454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2982420454
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.570407344
Short name T940
Test name
Test status
Simulation time 238067729 ps
CPU time 1.25 seconds
Started May 19 12:54:55 PM PDT 24
Finished May 19 12:54:57 PM PDT 24
Peak memory 192152 kb
Host smart-3bbb7037-8e7f-4ffe-a2e6-f4184b00fdbe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570407344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.570407344
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3006551393
Short name T902
Test name
Test status
Simulation time 215137366 ps
CPU time 1.36 seconds
Started May 19 12:54:49 PM PDT 24
Finished May 19 12:54:52 PM PDT 24
Peak memory 192164 kb
Host smart-44e5ed8f-8e26-446c-8e47-e38dddfa1319
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3006551393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3006551393
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2145507359
Short name T866
Test name
Test status
Simulation time 156664593 ps
CPU time 1.3 seconds
Started May 19 12:54:49 PM PDT 24
Finished May 19 12:54:52 PM PDT 24
Peak memory 192308 kb
Host smart-fa7da742-a0ca-43a5-961e-22fe7b32dbc1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145507359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2145507359
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4216378715
Short name T928
Test name
Test status
Simulation time 268519570 ps
CPU time 1.41 seconds
Started May 19 12:54:47 PM PDT 24
Finished May 19 12:54:50 PM PDT 24
Peak memory 198560 kb
Host smart-b0ac68c6-5958-478f-9b76-e7a536427547
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4216378715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.4216378715
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2765001108
Short name T890
Test name
Test status
Simulation time 460093615 ps
CPU time 1.32 seconds
Started May 19 12:54:46 PM PDT 24
Finished May 19 12:54:49 PM PDT 24
Peak memory 192304 kb
Host smart-3c8ebeff-cbb4-40da-b350-86f26dc4ea35
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765001108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2765001108
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2520288327
Short name T901
Test name
Test status
Simulation time 30352761 ps
CPU time 1.01 seconds
Started May 19 12:54:48 PM PDT 24
Finished May 19 12:54:50 PM PDT 24
Peak memory 192236 kb
Host smart-72b7eb8c-761c-4085-8f43-8a6683b52638
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2520288327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2520288327
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3294999747
Short name T897
Test name
Test status
Simulation time 241208566 ps
CPU time 1.26 seconds
Started May 19 12:54:46 PM PDT 24
Finished May 19 12:54:49 PM PDT 24
Peak memory 198336 kb
Host smart-75d50a89-6566-43fd-b73f-b48cf6ec71d3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294999747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3294999747
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2618093626
Short name T931
Test name
Test status
Simulation time 934290591 ps
CPU time 1.01 seconds
Started May 19 12:54:52 PM PDT 24
Finished May 19 12:54:55 PM PDT 24
Peak memory 198508 kb
Host smart-4e8b7844-1ede-4e64-a5bc-5f58e4490e16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2618093626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2618093626
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3163181228
Short name T942
Test name
Test status
Simulation time 258391438 ps
CPU time 1.07 seconds
Started May 19 12:54:45 PM PDT 24
Finished May 19 12:54:48 PM PDT 24
Peak memory 192312 kb
Host smart-b20546e3-31a6-481c-8529-606bf43f5181
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163181228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3163181228
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2616723815
Short name T905
Test name
Test status
Simulation time 226581272 ps
CPU time 1.15 seconds
Started May 19 12:54:54 PM PDT 24
Finished May 19 12:54:56 PM PDT 24
Peak memory 192224 kb
Host smart-c90861c5-119c-43a3-bf52-c7abc8662600
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2616723815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2616723815
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3073912639
Short name T891
Test name
Test status
Simulation time 183729568 ps
CPU time 1.04 seconds
Started May 19 12:54:51 PM PDT 24
Finished May 19 12:54:54 PM PDT 24
Peak memory 192320 kb
Host smart-e5f91750-0b09-4081-8e6a-442bd2bba9eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073912639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3073912639
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3518211672
Short name T873
Test name
Test status
Simulation time 70270592 ps
CPU time 0.81 seconds
Started May 19 12:54:56 PM PDT 24
Finished May 19 12:54:58 PM PDT 24
Peak memory 192044 kb
Host smart-a3a926c3-cc33-41d1-9ccb-132ba96fb25d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3518211672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3518211672
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3719309635
Short name T938
Test name
Test status
Simulation time 84242893 ps
CPU time 1.15 seconds
Started May 19 12:54:55 PM PDT 24
Finished May 19 12:54:58 PM PDT 24
Peak memory 192276 kb
Host smart-f2da809e-f394-472a-bdb6-8e4da5effeba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719309635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3719309635
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.444348950
Short name T886
Test name
Test status
Simulation time 76855692 ps
CPU time 1.36 seconds
Started May 19 12:54:46 PM PDT 24
Finished May 19 12:54:49 PM PDT 24
Peak memory 196980 kb
Host smart-21790fbd-0013-43d9-83f6-58cdbae89a88
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=444348950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.444348950
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3345959324
Short name T933
Test name
Test status
Simulation time 96866420 ps
CPU time 0.97 seconds
Started May 19 12:54:49 PM PDT 24
Finished May 19 12:54:51 PM PDT 24
Peak memory 192532 kb
Host smart-d22ed166-4379-4472-8f3a-58242e0afbe4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345959324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3345959324
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3178115527
Short name T914
Test name
Test status
Simulation time 45385025 ps
CPU time 1.24 seconds
Started May 19 12:54:50 PM PDT 24
Finished May 19 12:54:54 PM PDT 24
Peak memory 192132 kb
Host smart-06fc60f8-d4ee-42cf-ac96-fe76c0899eb6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3178115527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3178115527
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4040053373
Short name T850
Test name
Test status
Simulation time 310644780 ps
CPU time 1.4 seconds
Started May 19 12:54:50 PM PDT 24
Finished May 19 12:54:53 PM PDT 24
Peak memory 197016 kb
Host smart-90ccf424-47ef-490a-87e9-63929e05a2e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040053373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4040053373
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.564548292
Short name T930
Test name
Test status
Simulation time 79845804 ps
CPU time 1.26 seconds
Started May 19 12:54:28 PM PDT 24
Finished May 19 12:54:31 PM PDT 24
Peak memory 192520 kb
Host smart-b4a6d76b-5874-4a53-b549-219b6efd9fec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=564548292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.564548292
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1382293089
Short name T934
Test name
Test status
Simulation time 70251599 ps
CPU time 1.14 seconds
Started May 19 12:54:34 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 192188 kb
Host smart-7490754b-e8de-4127-8908-2f14c250b5f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382293089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1382293089
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1364665562
Short name T904
Test name
Test status
Simulation time 65524316 ps
CPU time 1.17 seconds
Started May 19 12:54:59 PM PDT 24
Finished May 19 12:55:01 PM PDT 24
Peak memory 192224 kb
Host smart-5d6cd18e-bd19-4f92-bf46-b714de8370d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1364665562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1364665562
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4176714069
Short name T892
Test name
Test status
Simulation time 117565544 ps
CPU time 1.33 seconds
Started May 19 12:54:56 PM PDT 24
Finished May 19 12:54:58 PM PDT 24
Peak memory 197848 kb
Host smart-07af65bc-87b3-4ca3-9ec3-09ced51d8e2d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176714069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4176714069
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1360565645
Short name T898
Test name
Test status
Simulation time 414412520 ps
CPU time 1.25 seconds
Started May 19 12:54:51 PM PDT 24
Finished May 19 12:54:54 PM PDT 24
Peak memory 192248 kb
Host smart-a64ac9a2-51fc-4227-b216-ae3f96ff70b2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1360565645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1360565645
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3112248653
Short name T883
Test name
Test status
Simulation time 164881812 ps
CPU time 1.16 seconds
Started May 19 12:54:57 PM PDT 24
Finished May 19 12:55:00 PM PDT 24
Peak memory 192240 kb
Host smart-13c191df-9098-476d-a475-1c8251a434fc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112248653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3112248653
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.507967449
Short name T894
Test name
Test status
Simulation time 117218589 ps
CPU time 0.97 seconds
Started May 19 12:54:50 PM PDT 24
Finished May 19 12:54:53 PM PDT 24
Peak memory 198428 kb
Host smart-5d611223-be8c-4d1f-9ba2-68b377bb1d0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=507967449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.507967449
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2255251315
Short name T851
Test name
Test status
Simulation time 58431105 ps
CPU time 0.83 seconds
Started May 19 12:54:50 PM PDT 24
Finished May 19 12:54:53 PM PDT 24
Peak memory 192080 kb
Host smart-e8fb8a83-8f79-406b-b4d3-99df8327b9c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255251315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2255251315
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4013969703
Short name T913
Test name
Test status
Simulation time 284825658 ps
CPU time 1.3 seconds
Started May 19 12:55:00 PM PDT 24
Finished May 19 12:55:02 PM PDT 24
Peak memory 192232 kb
Host smart-36f13b40-3f35-4b42-80e9-142e25bfd2f7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4013969703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.4013969703
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1061557578
Short name T884
Test name
Test status
Simulation time 120519671 ps
CPU time 0.81 seconds
Started May 19 12:54:53 PM PDT 24
Finished May 19 12:54:55 PM PDT 24
Peak memory 192116 kb
Host smart-f4838a18-3c40-41c8-83bf-13f7fb32af60
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061557578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1061557578
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1540575176
Short name T915
Test name
Test status
Simulation time 228847772 ps
CPU time 0.96 seconds
Started May 19 12:54:47 PM PDT 24
Finished May 19 12:54:50 PM PDT 24
Peak memory 197944 kb
Host smart-46a5d671-ccb9-4182-8352-a6a528252511
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1540575176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1540575176
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1024723631
Short name T943
Test name
Test status
Simulation time 51480060 ps
CPU time 1.09 seconds
Started May 19 12:54:56 PM PDT 24
Finished May 19 12:54:59 PM PDT 24
Peak memory 192184 kb
Host smart-3d6c2e1f-fc5c-4029-8e86-7351dc182c2a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024723631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1024723631
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.884318166
Short name T944
Test name
Test status
Simulation time 55224607 ps
CPU time 0.99 seconds
Started May 19 12:55:02 PM PDT 24
Finished May 19 12:55:06 PM PDT 24
Peak memory 192068 kb
Host smart-b0604b83-795e-40c8-a831-cc04ee543bb5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=884318166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.884318166
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4030281426
Short name T927
Test name
Test status
Simulation time 329453419 ps
CPU time 1.01 seconds
Started May 19 12:55:00 PM PDT 24
Finished May 19 12:55:03 PM PDT 24
Peak memory 192256 kb
Host smart-1a5f8320-5b29-41bd-8ac5-efaa80bf390e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030281426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4030281426
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2916614069
Short name T900
Test name
Test status
Simulation time 237212786 ps
CPU time 1.13 seconds
Started May 19 12:55:08 PM PDT 24
Finished May 19 12:55:13 PM PDT 24
Peak memory 192156 kb
Host smart-ea603d7e-2b20-4892-bc0e-357eadfe5505
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2916614069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2916614069
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2218898296
Short name T863
Test name
Test status
Simulation time 43468116 ps
CPU time 1.09 seconds
Started May 19 12:55:03 PM PDT 24
Finished May 19 12:55:07 PM PDT 24
Peak memory 192300 kb
Host smart-8e868c01-a3b2-4268-9671-dc69a11d4e33
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218898296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2218898296
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2513279808
Short name T876
Test name
Test status
Simulation time 679793486 ps
CPU time 1.35 seconds
Started May 19 12:55:00 PM PDT 24
Finished May 19 12:55:04 PM PDT 24
Peak memory 192212 kb
Host smart-774a0711-4972-4867-985b-61e8778b53bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2513279808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2513279808
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3127121546
Short name T879
Test name
Test status
Simulation time 24206046 ps
CPU time 0.79 seconds
Started May 19 12:55:00 PM PDT 24
Finished May 19 12:55:03 PM PDT 24
Peak memory 192060 kb
Host smart-dc358918-c810-4b7e-b7a3-87af4bd8094f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127121546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3127121546
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3637327056
Short name T916
Test name
Test status
Simulation time 137064493 ps
CPU time 1.16 seconds
Started May 19 12:55:03 PM PDT 24
Finished May 19 12:55:07 PM PDT 24
Peak memory 192092 kb
Host smart-6c133453-b2fc-45fc-9670-fb69090cca83
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3637327056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3637327056
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2242238372
Short name T918
Test name
Test status
Simulation time 120843673 ps
CPU time 1.11 seconds
Started May 19 12:55:04 PM PDT 24
Finished May 19 12:55:08 PM PDT 24
Peak memory 192220 kb
Host smart-d704eade-d592-496b-8649-2e3dbd9928cd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242238372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2242238372
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2685962760
Short name T926
Test name
Test status
Simulation time 48005850 ps
CPU time 1.25 seconds
Started May 19 12:55:04 PM PDT 24
Finished May 19 12:55:09 PM PDT 24
Peak memory 196952 kb
Host smart-e699f989-dfd5-4739-a76c-8caa71b973dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2685962760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2685962760
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1802946935
Short name T911
Test name
Test status
Simulation time 46689499 ps
CPU time 1.29 seconds
Started May 19 12:55:02 PM PDT 24
Finished May 19 12:55:07 PM PDT 24
Peak memory 192332 kb
Host smart-80438867-c635-43ec-a0eb-3dfc29d7759f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802946935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1802946935
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1097962860
Short name T917
Test name
Test status
Simulation time 165784902 ps
CPU time 0.89 seconds
Started May 19 12:54:34 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 192252 kb
Host smart-07bc827b-26d9-4920-b08a-26ebcabc91ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1097962860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1097962860
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2688626635
Short name T875
Test name
Test status
Simulation time 69693593 ps
CPU time 1.44 seconds
Started May 19 12:54:40 PM PDT 24
Finished May 19 12:54:43 PM PDT 24
Peak memory 198168 kb
Host smart-5c0d8062-7b1b-4d0a-b30a-ec8bc8bc00ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688626635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2688626635
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1014107033
Short name T921
Test name
Test status
Simulation time 632914301 ps
CPU time 0.85 seconds
Started May 19 12:55:01 PM PDT 24
Finished May 19 12:55:03 PM PDT 24
Peak memory 192324 kb
Host smart-86a60839-260a-450e-a8cc-1e0ebc7ff0d1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1014107033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1014107033
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2248108821
Short name T853
Test name
Test status
Simulation time 149336183 ps
CPU time 0.9 seconds
Started May 19 12:55:07 PM PDT 24
Finished May 19 12:55:12 PM PDT 24
Peak memory 197080 kb
Host smart-2c3f5aa2-0acf-4731-a6e1-0907e31fad01
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248108821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2248108821
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.310348881
Short name T925
Test name
Test status
Simulation time 88367318 ps
CPU time 0.82 seconds
Started May 19 12:55:08 PM PDT 24
Finished May 19 12:55:13 PM PDT 24
Peak memory 191980 kb
Host smart-51ea18c7-06b1-4e30-9295-9f47110080a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=310348881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.310348881
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1452731682
Short name T848
Test name
Test status
Simulation time 116970879 ps
CPU time 1.24 seconds
Started May 19 12:55:01 PM PDT 24
Finished May 19 12:55:05 PM PDT 24
Peak memory 198616 kb
Host smart-949696e2-a1b3-43b5-bd40-0c2e18d7639b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452731682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1452731682
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3273122057
Short name T870
Test name
Test status
Simulation time 397423678 ps
CPU time 1.06 seconds
Started May 19 12:55:00 PM PDT 24
Finished May 19 12:55:03 PM PDT 24
Peak memory 192220 kb
Host smart-f1117506-1241-4188-8d85-af1c9a888364
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3273122057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3273122057
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.60878992
Short name T854
Test name
Test status
Simulation time 106449332 ps
CPU time 1.14 seconds
Started May 19 12:55:00 PM PDT 24
Finished May 19 12:55:03 PM PDT 24
Peak memory 192256 kb
Host smart-84d24bcf-7228-49ed-99c0-fc3d6c77f7b2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60878992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.60878992
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3946592824
Short name T859
Test name
Test status
Simulation time 122995545 ps
CPU time 0.78 seconds
Started May 19 12:55:02 PM PDT 24
Finished May 19 12:55:06 PM PDT 24
Peak memory 191964 kb
Host smart-e42175be-0139-49c0-b526-396ccf53ce06
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3946592824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3946592824
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.765822045
Short name T845
Test name
Test status
Simulation time 75762848 ps
CPU time 1.39 seconds
Started May 19 12:55:08 PM PDT 24
Finished May 19 12:55:13 PM PDT 24
Peak memory 198508 kb
Host smart-53c7e4e8-5629-4289-a26c-bc5d0d053515
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765822045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.765822045
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3611398432
Short name T887
Test name
Test status
Simulation time 104809343 ps
CPU time 1.09 seconds
Started May 19 12:55:00 PM PDT 24
Finished May 19 12:55:03 PM PDT 24
Peak memory 192240 kb
Host smart-aa93a7cc-170a-4c00-8395-00cebe02ac8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3611398432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3611398432
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3871844088
Short name T912
Test name
Test status
Simulation time 49151904 ps
CPU time 1.1 seconds
Started May 19 12:55:02 PM PDT 24
Finished May 19 12:55:06 PM PDT 24
Peak memory 192272 kb
Host smart-cccd1446-5b31-47a1-a2e1-0caed37d070b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871844088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3871844088
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2970457516
Short name T889
Test name
Test status
Simulation time 510089509 ps
CPU time 1.01 seconds
Started May 19 12:55:02 PM PDT 24
Finished May 19 12:55:05 PM PDT 24
Peak memory 192056 kb
Host smart-273e9923-682a-4059-b209-41c293801577
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2970457516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2970457516
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2090088120
Short name T860
Test name
Test status
Simulation time 167844254 ps
CPU time 0.89 seconds
Started May 19 12:54:59 PM PDT 24
Finished May 19 12:55:01 PM PDT 24
Peak memory 192096 kb
Host smart-84caaba3-0a9a-4646-94cf-ef0befdd6787
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090088120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2090088120
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1826507108
Short name T885
Test name
Test status
Simulation time 38470075 ps
CPU time 1.18 seconds
Started May 19 12:55:02 PM PDT 24
Finished May 19 12:55:06 PM PDT 24
Peak memory 192248 kb
Host smart-c4cd7f5b-051b-497a-b307-3104e977a671
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1826507108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1826507108
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2150121350
Short name T936
Test name
Test status
Simulation time 70641603 ps
CPU time 0.75 seconds
Started May 19 12:55:05 PM PDT 24
Finished May 19 12:55:10 PM PDT 24
Peak memory 192096 kb
Host smart-ab392af5-53e6-475a-82c0-a200e730da0d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150121350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2150121350
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3331390110
Short name T869
Test name
Test status
Simulation time 68084914 ps
CPU time 1.01 seconds
Started May 19 12:55:06 PM PDT 24
Finished May 19 12:55:12 PM PDT 24
Peak memory 198868 kb
Host smart-6a1818a6-01d2-4d75-a57a-f9352a8c4db4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3331390110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3331390110
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4026264508
Short name T862
Test name
Test status
Simulation time 102520533 ps
CPU time 1.18 seconds
Started May 19 12:55:04 PM PDT 24
Finished May 19 12:55:08 PM PDT 24
Peak memory 192148 kb
Host smart-e79a8ba6-dda3-4a19-a7a9-4a76eae8cac8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026264508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4026264508
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.633668983
Short name T919
Test name
Test status
Simulation time 166135472 ps
CPU time 1.13 seconds
Started May 19 12:55:06 PM PDT 24
Finished May 19 12:55:12 PM PDT 24
Peak memory 192516 kb
Host smart-898d964b-408c-4dc8-b9b2-0255862c6acb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=633668983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.633668983
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2470562733
Short name T847
Test name
Test status
Simulation time 67489991 ps
CPU time 1.11 seconds
Started May 19 12:55:04 PM PDT 24
Finished May 19 12:55:08 PM PDT 24
Peak memory 192188 kb
Host smart-a61876bc-89c1-4ab8-b736-600a4370d8ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470562733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2470562733
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.465161835
Short name T882
Test name
Test status
Simulation time 278258757 ps
CPU time 1.45 seconds
Started May 19 12:55:00 PM PDT 24
Finished May 19 12:55:04 PM PDT 24
Peak memory 198516 kb
Host smart-2a077eaa-f284-4dc6-b7a0-ef4ac5fe7dd1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=465161835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.465161835
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1615217353
Short name T855
Test name
Test status
Simulation time 254699628 ps
CPU time 1.18 seconds
Started May 19 12:55:06 PM PDT 24
Finished May 19 12:55:11 PM PDT 24
Peak memory 192300 kb
Host smart-ae00241f-9ba3-4191-b187-2aa8f9397221
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615217353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1615217353
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2601519335
Short name T924
Test name
Test status
Simulation time 99614176 ps
CPU time 1.4 seconds
Started May 19 12:54:37 PM PDT 24
Finished May 19 12:54:41 PM PDT 24
Peak memory 192104 kb
Host smart-09118b4f-c41c-470d-b776-713998d6adc4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2601519335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2601519335
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2482866863
Short name T874
Test name
Test status
Simulation time 33981592 ps
CPU time 0.77 seconds
Started May 19 12:54:36 PM PDT 24
Finished May 19 12:54:38 PM PDT 24
Peak memory 191972 kb
Host smart-52f31a5a-39b1-42c7-82fa-a47c4be7aac4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482866863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2482866863
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2027249910
Short name T872
Test name
Test status
Simulation time 386537143 ps
CPU time 1.55 seconds
Started May 19 12:54:33 PM PDT 24
Finished May 19 12:54:37 PM PDT 24
Peak memory 192240 kb
Host smart-16cef386-06c0-4bcf-abd5-dc341504df16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2027249910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2027249910
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1753790885
Short name T941
Test name
Test status
Simulation time 44006126 ps
CPU time 1.18 seconds
Started May 19 12:54:38 PM PDT 24
Finished May 19 12:54:41 PM PDT 24
Peak memory 197080 kb
Host smart-f72daae9-3df1-446a-bbea-67956037e423
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753790885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1753790885
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.148345858
Short name T932
Test name
Test status
Simulation time 157527517 ps
CPU time 1.17 seconds
Started May 19 12:54:31 PM PDT 24
Finished May 19 12:54:34 PM PDT 24
Peak memory 192268 kb
Host smart-df190947-1ad4-40e8-b573-93133024dad1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=148345858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.148345858
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4121412395
Short name T871
Test name
Test status
Simulation time 74405774 ps
CPU time 0.94 seconds
Started May 19 12:54:43 PM PDT 24
Finished May 19 12:54:45 PM PDT 24
Peak memory 198604 kb
Host smart-5b353285-7ea5-4c61-acd0-5363e3e4bb49
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121412395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4121412395
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1494717681
Short name T880
Test name
Test status
Simulation time 139520835 ps
CPU time 1.14 seconds
Started May 19 12:54:40 PM PDT 24
Finished May 19 12:54:43 PM PDT 24
Peak memory 192272 kb
Host smart-1fbb9911-c549-4001-9a5d-2a1ed615f22b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1494717681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1494717681
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3116473568
Short name T867
Test name
Test status
Simulation time 114958803 ps
CPU time 1.02 seconds
Started May 19 12:54:32 PM PDT 24
Finished May 19 12:54:34 PM PDT 24
Peak memory 192236 kb
Host smart-2eb22cfe-e4ca-42de-93ef-20830852b812
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116473568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3116473568
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1614285981
Short name T899
Test name
Test status
Simulation time 302202415 ps
CPU time 1.17 seconds
Started May 19 12:54:46 PM PDT 24
Finished May 19 12:54:49 PM PDT 24
Peak memory 192316 kb
Host smart-d65f57e8-ef2b-433d-bd1e-65a8059f8a8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1614285981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1614285981
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3883001333
Short name T909
Test name
Test status
Simulation time 74832862 ps
CPU time 0.8 seconds
Started May 19 12:54:44 PM PDT 24
Finished May 19 12:54:46 PM PDT 24
Peak memory 192076 kb
Host smart-7cb0646d-2b28-4c94-b8db-2a5a5ce7adba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883001333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3883001333
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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