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Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1758181 1 T32 59 T35 294 T36 68
auto[1] 1529100 1 T32 39 T35 340 T36 18


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2062616 1 T32 87 T35 343 T36 81
auto[1] 1224665 1 T32 11 T35 291 T36 5


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1141392 1 T32 59 T35 170 T36 64
auto[0] auto[1] 616789 1 T35 124 T36 4 T37 18
auto[1] auto[0] 921224 1 T32 28 T35 173 T36 17
auto[1] auto[1] 607876 1 T32 11 T35 167 T36 1


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1756638 1 T32 75 T35 276 T36 26
auto[1] 1530643 1 T32 23 T35 358 T36 60


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2064698 1 T32 80 T35 305 T36 81
auto[1] 1222583 1 T32 18 T35 329 T36 5


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1141582 1 T32 59 T35 139 T36 24
auto[0] auto[1] 615056 1 T32 16 T35 137 T36 2
auto[1] auto[0] 923116 1 T32 21 T35 166 T36 57
auto[1] auto[1] 607527 1 T32 2 T35 192 T36 3


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1758885 1 T32 76 T35 273 T36 30
auto[1] 1528396 1 T32 22 T35 361 T36 56


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2065416 1 T32 86 T35 343 T36 82
auto[1] 1221865 1 T32 12 T35 291 T36 4


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1143709 1 T32 70 T35 160 T36 28
auto[0] auto[1] 615176 1 T32 6 T35 113 T36 2
auto[1] auto[0] 921707 1 T32 16 T35 183 T36 54
auto[1] auto[1] 606689 1 T32 6 T35 178 T36 2


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1757756 1 T32 65 T35 333 T36 36
auto[1] 1529525 1 T32 33 T35 301 T36 50


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2065202 1 T32 93 T35 366 T36 85
auto[1] 1222079 1 T32 5 T35 268 T36 1


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1142284 1 T32 64 T35 189 T36 35
auto[0] auto[1] 615472 1 T32 1 T35 144 T36 1
auto[1] auto[0] 922918 1 T32 29 T35 177 T36 50
auto[1] auto[1] 606607 1 T32 4 T35 124 T37 18


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1755676 1 T32 83 T35 299 T36 27
auto[1] 1531605 1 T32 15 T35 335 T36 59


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2063551 1 T32 81 T35 306 T36 84
auto[1] 1223730 1 T32 17 T35 328 T36 2


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1139873 1 T32 69 T35 145 T36 26
auto[0] auto[1] 615803 1 T32 14 T35 154 T36 1
auto[1] auto[0] 923678 1 T32 12 T35 161 T36 58
auto[1] auto[1] 607927 1 T32 3 T35 174 T36 1


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1756631 1 T32 69 T35 344 T36 50
auto[1] 1530650 1 T32 29 T35 290 T36 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2065887 1 T32 84 T35 324 T36 79
auto[1] 1221394 1 T32 14 T35 310 T36 7


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1142364 1 T32 60 T35 158 T36 45
auto[0] auto[1] 614267 1 T32 9 T35 186 T36 5
auto[1] auto[0] 923523 1 T32 24 T35 166 T36 34
auto[1] auto[1] 607127 1 T32 5 T35 124 T36 2


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1753444 1 T32 70 T35 289 T36 49
auto[1] 1533837 1 T32 28 T35 345 T36 37


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2064971 1 T32 86 T35 360 T36 81
auto[1] 1222310 1 T32 12 T35 274 T36 5


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1138933 1 T32 64 T35 175 T36 45
auto[0] auto[1] 614511 1 T32 6 T35 114 T36 4
auto[1] auto[0] 926038 1 T32 22 T35 185 T36 36
auto[1] auto[1] 607799 1 T32 6 T35 160 T36 1


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1753580 1 T32 93 T35 303 T36 58
auto[1] 1533701 1 T32 5 T35 331 T36 28


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2062522 1 T32 86 T35 409 T36 82
auto[1] 1224759 1 T32 12 T35 225 T36 4


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1138981 1 T32 81 T35 183 T36 56
auto[0] auto[1] 614599 1 T32 12 T35 120 T36 2
auto[1] auto[0] 923541 1 T32 5 T35 226 T36 26
auto[1] auto[1] 610160 1 T35 105 T36 2 T37 16


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1755806 1 T32 61 T35 360 T36 44
auto[1] 1531475 1 T32 37 T35 274 T36 42


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2070344 1 T32 78 T35 379 T36 80
auto[1] 1216937 1 T32 20 T35 255 T36 6


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1143354 1 T32 57 T35 218 T36 40
auto[0] auto[1] 612452 1 T32 4 T35 142 T36 4
auto[1] auto[0] 926990 1 T32 21 T35 161 T36 40
auto[1] auto[1] 604485 1 T32 16 T35 113 T36 2


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1753314 1 T32 77 T35 339 T36 45
auto[1] 1533967 1 T32 21 T35 295 T36 41


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2070353 1 T32 79 T35 394 T36 83
auto[1] 1216928 1 T32 19 T35 240 T36 3


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1141841 1 T32 68 T35 208 T36 45
auto[0] auto[1] 611473 1 T32 9 T35 131 T37 4
auto[1] auto[0] 928512 1 T32 11 T35 186 T36 38
auto[1] auto[1] 605455 1 T32 10 T35 109 T36 3


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1756016 1 T32 78 T35 345 T36 86
auto[1] 1531265 1 T32 20 T35 289 T37 18


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2073275 1 T32 89 T35 409 T36 80
auto[1] 1214006 1 T32 9 T35 225 T36 6


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1145582 1 T32 73 T35 216 T36 80
auto[0] auto[1] 610434 1 T32 5 T35 129 T36 6
auto[1] auto[0] 927693 1 T32 16 T35 193 T37 9
auto[1] auto[1] 603572 1 T32 4 T35 96 T37 9


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1760343 1 T32 80 T35 320 T36 40
auto[1] 1526938 1 T32 18 T35 314 T36 46


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2071049 1 T32 90 T35 353 T36 85
auto[1] 1216232 1 T32 8 T35 281 T36 1


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1146815 1 T32 78 T35 178 T36 40
auto[0] auto[1] 613528 1 T32 2 T35 142 T37 13
auto[1] auto[0] 924234 1 T32 12 T35 175 T36 45
auto[1] auto[1] 602704 1 T32 6 T35 139 T36 1


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1759756 1 T32 74 T35 321 T36 74
auto[1] 1527525 1 T32 24 T35 313 T36 12


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2065962 1 T32 89 T35 299 T36 81
auto[1] 1221319 1 T32 9 T35 335 T36 5


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1144911 1 T32 74 T35 150 T36 69
auto[0] auto[1] 614845 1 T35 171 T36 5 T37 14
auto[1] auto[0] 921051 1 T32 15 T35 149 T36 12
auto[1] auto[1] 606474 1 T32 9 T35 164 T37 11


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1753529 1 T32 76 T35 294 T36 53
auto[1] 1533752 1 T32 22 T35 340 T36 33


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2073293 1 T32 86 T35 371 T36 80
auto[1] 1213988 1 T32 12 T35 263 T36 6


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1143222 1 T32 73 T35 157 T36 52
auto[0] auto[1] 610307 1 T32 3 T35 137 T36 1
auto[1] auto[0] 930071 1 T32 13 T35 214 T36 28
auto[1] auto[1] 603681 1 T32 9 T35 126 T36 5


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1754037 1 T32 87 T35 329 T36 61
auto[1] 1533244 1 T32 11 T35 305 T36 25


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2072603 1 T32 92 T35 390 T36 84
auto[1] 1214678 1 T32 6 T35 244 T36 2


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1142577 1 T32 81 T35 199 T36 59
auto[0] auto[1] 611460 1 T32 6 T35 130 T36 2
auto[1] auto[0] 930026 1 T32 11 T35 191 T36 25
auto[1] auto[1] 603218 1 T35 114 T37 7 T40 2765


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1760982 1 T32 70 T35 373 T36 43
auto[1] 1526299 1 T32 28 T35 261 T36 43


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2072031 1 T32 92 T35 368 T36 76
auto[1] 1215250 1 T32 6 T35 266 T36 10


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1148598 1 T32 70 T35 216 T36 38
auto[0] auto[1] 612384 1 T35 157 T36 5 T37 11
auto[1] auto[0] 923433 1 T32 22 T35 152 T36 38
auto[1] auto[1] 602866 1 T32 6 T35 109 T36 5


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1761995 1 T32 69 T35 329 T36 55
auto[1] 1525286 1 T32 29 T35 305 T36 31


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2069769 1 T32 78 T35 336 T36 78
auto[1] 1217512 1 T32 20 T35 298 T36 8


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1147158 1 T32 65 T35 162 T36 48
auto[0] auto[1] 614837 1 T32 4 T35 167 T36 7
auto[1] auto[0] 922611 1 T32 13 T35 174 T36 30
auto[1] auto[1] 602675 1 T32 16 T35 131 T36 1


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1758859 1 T32 82 T35 285 T36 65
auto[1] 1528422 1 T32 16 T35 349 T36 21


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2074478 1 T32 96 T35 338 T36 84
auto[1] 1212803 1 T32 2 T35 296 T36 2


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1146517 1 T32 82 T35 144 T36 63
auto[0] auto[1] 612342 1 T35 141 T36 2 T37 5
auto[1] auto[0] 927961 1 T32 14 T35 194 T36 21
auto[1] auto[1] 600461 1 T32 2 T35 155 T37 4


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1761179 1 T32 91 T35 283 T36 27
auto[1] 1526102 1 T32 7 T35 351 T36 59


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2070795 1 T32 87 T35 362 T36 83
auto[1] 1216486 1 T32 11 T35 272 T36 3


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1148086 1 T32 82 T35 162 T36 27
auto[0] auto[1] 613093 1 T32 9 T35 121 T37 7
auto[1] auto[0] 922709 1 T32 5 T35 200 T36 56
auto[1] auto[1] 603393 1 T32 2 T35 151 T36 3


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1755793 1 T32 83 T35 271 T36 56
auto[1] 1531488 1 T32 15 T35 363 T36 30


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2073825 1 T32 91 T35 373 T36 82
auto[1] 1213456 1 T32 7 T35 261 T36 4


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1145146 1 T32 78 T35 162 T36 52
auto[0] auto[1] 610647 1 T32 5 T35 109 T36 4
auto[1] auto[0] 928679 1 T32 13 T35 211 T36 30
auto[1] auto[1] 602809 1 T32 2 T35 152 T37 9


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1757130 1 T32 80 T35 329 T36 50
auto[1] 1530151 1 T32 18 T35 305 T36 36


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2070408 1 T32 83 T35 318 T36 81
auto[1] 1216873 1 T32 15 T35 316 T36 5


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1144975 1 T32 67 T35 174 T36 48
auto[0] auto[1] 612155 1 T32 13 T35 155 T36 2
auto[1] auto[0] 925433 1 T32 16 T35 144 T36 33
auto[1] auto[1] 604718 1 T32 2 T35 161 T36 3


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1757315 1 T32 85 T35 274 T36 57
auto[1] 1529966 1 T32 13 T35 360 T36 29


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2067716 1 T32 87 T35 342 T36 84
auto[1] 1219565 1 T32 11 T35 292 T36 2


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1142920 1 T32 74 T35 159 T36 57
auto[0] auto[1] 614395 1 T32 11 T35 115 T37 12
auto[1] auto[0] 924796 1 T32 13 T35 183 T36 27
auto[1] auto[1] 605170 1 T35 177 T36 2 T37 1


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1757753 1 T32 66 T35 334 T36 67
auto[1] 1529528 1 T32 32 T35 300 T36 19


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2072835 1 T32 88 T35 345 T36 78
auto[1] 1214446 1 T32 10 T35 289 T36 8


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1145378 1 T32 63 T35 183 T36 60
auto[0] auto[1] 612375 1 T32 3 T35 151 T36 7
auto[1] auto[0] 927457 1 T32 25 T35 162 T36 18
auto[1] auto[1] 602071 1 T32 7 T35 138 T36 1


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1756179 1 T32 57 T35 288 T36 33
auto[1] 1531102 1 T32 41 T35 346 T36 53


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2062622 1 T32 84 T35 328 T36 80
auto[1] 1224659 1 T32 14 T35 306 T36 6


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1140353 1 T32 56 T35 155 T36 31
auto[0] auto[1] 615826 1 T32 1 T35 133 T36 2
auto[1] auto[0] 922269 1 T32 28 T35 173 T36 49
auto[1] auto[1] 608833 1 T32 13 T35 173 T36 4


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1758598 1 T32 89 T35 313 T36 48
auto[1] 1528683 1 T32 9 T35 321 T36 38


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2069604 1 T32 93 T35 395 T36 80
auto[1] 1217677 1 T32 5 T35 239 T36 6


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1144906 1 T32 87 T35 188 T36 45
auto[0] auto[1] 613692 1 T32 2 T35 125 T36 3
auto[1] auto[0] 924698 1 T32 6 T35 207 T36 35
auto[1] auto[1] 603985 1 T32 3 T35 114 T36 3


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1757603 1 T32 87 T35 340 T36 34
auto[1] 1529678 1 T32 11 T35 294 T36 52


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2071232 1 T32 87 T35 418 T36 79
auto[1] 1216049 1 T32 11 T35 216 T36 7


Summary for Cross cp_var1_var2_cross

Samples crossed: cp_var1 cp_var2
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cp_var1_var2_cross

Bins
cp_var1cp_var2COUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 1145762 1 T32 78 T35 237 T36 32
auto[0] auto[1] 611841 1 T32 9 T35 103 T36 2
auto[1] auto[0] 925470 1 T32 9 T35 181 T36 47
auto[1] auto[1] 604208 1 T32 2 T35 113 T36 5


Summary for Variable cp_var1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var1

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1757728 1 T32 80 T35 333 T36 64
auto[1] 1529553 1 T32 18 T35 301 T36 22


Summary for Variable cp_var2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_var2

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2063402 1 T32 80 T35 360 T36 83
auto[1] 1223879 1 T32 18 T35 274 T36 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%