Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3635420	1			T30	236		T31	94		T32	91
all_pins[1]	3635420	1			T30	236		T31	94		T32	91
all_pins[2]	3635420	1			T30	236		T31	94		T32	91
all_pins[3]	3635420	1			T30	236		T31	94		T32	91
all_pins[4]	3635420	1			T30	236		T31	94		T32	91
all_pins[5]	3635420	1			T30	236		T31	94		T32	91
all_pins[6]	3635420	1			T30	236		T31	94		T32	91
all_pins[7]	3635420	1			T30	236		T31	94		T32	91
all_pins[8]	3635420	1			T30	236		T31	94		T32	91
all_pins[9]	3635420	1			T30	236		T31	94		T32	91
all_pins[10]	3635420	1			T30	236		T31	94		T32	91
all_pins[11]	3635420	1			T30	236		T31	94		T32	91
all_pins[12]	3635420	1			T30	236		T31	94		T32	91
all_pins[13]	3635420	1			T30	236		T31	94		T32	91
all_pins[14]	3635420	1			T30	236		T31	94		T32	91
all_pins[15]	3635420	1			T30	236		T31	94		T32	91
all_pins[16]	3635420	1			T30	236		T31	94		T32	91
all_pins[17]	3635420	1			T30	236		T31	94		T32	91
all_pins[18]	3635420	1			T30	236		T31	94		T32	91
all_pins[19]	3635420	1			T30	236		T31	94		T32	91
all_pins[20]	3635420	1			T30	236		T31	94		T32	91
all_pins[21]	3635420	1			T30	236		T31	94		T32	91
all_pins[22]	3635420	1			T30	236		T31	94		T32	91
all_pins[23]	3635420	1			T30	236		T31	94		T32	91
all_pins[24]	3635420	1			T30	236		T31	94		T32	91
all_pins[25]	3635420	1			T30	236		T31	94		T32	91
all_pins[26]	3635420	1			T30	236		T31	94		T32	91
all_pins[27]	3635420	1			T30	236		T31	94		T32	91
all_pins[28]	3635420	1			T30	236		T31	94		T32	91
all_pins[29]	3635420	1			T30	236		T31	94		T32	91
all_pins[30]	3635420	1			T30	236		T31	94		T32	91
all_pins[31]	3635420	1			T30	236		T31	94		T32	91

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	72267617	1			T30	4490		T31	1554		T32	2375
values[0x1]	44065823	1			T30	3062		T31	1454		T32	537
transitions[0x0=>0x1]	26418051	1			T30	1770		T31	736		T32	355
transitions[0x1=>0x0]	26417888	1			T30	1770		T31	735		T32	355

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2256360	1			T30	141		T31	42		T32	77
all_pins[0]	values[0x1]	1379060	1			T30	95		T31	52		T32	14
all_pins[0]	transitions[0x0=>0x1]	853049	1			T30	90		T31	27		T32	7
all_pins[0]	transitions[0x1=>0x0]	857008	1			T30	33		T31	18		T32	12
all_pins[1]	values[0x0]	2258288	1			T30	130		T31	49		T32	77
all_pins[1]	values[0x1]	1377132	1			T30	106		T31	45		T32	14
all_pins[1]	transitions[0x0=>0x1]	822263	1			T30	67		T31	21		T32	14
all_pins[1]	transitions[0x1=>0x0]	824191	1			T30	56		T31	28		T32	14
all_pins[2]	values[0x0]	2255812	1			T30	191		T31	52		T32	70
all_pins[2]	values[0x1]	1379608	1			T30	45		T31	42		T32	21
all_pins[2]	transitions[0x0=>0x1]	825448	1			T30	10		T31	19		T32	21
all_pins[2]	transitions[0x1=>0x0]	822972	1			T30	71		T31	22		T32	14
all_pins[3]	values[0x0]	2256748	1			T30	162		T31	47		T32	78
all_pins[3]	values[0x1]	1378672	1			T30	74		T31	47		T32	13
all_pins[3]	transitions[0x0=>0x1]	824669	1			T30	44		T31	30		T32	7
all_pins[3]	transitions[0x1=>0x0]	825605	1			T30	15		T31	25		T32	15
all_pins[4]	values[0x0]	2257742	1			T30	175		T31	52		T32	76
all_pins[4]	values[0x1]	1377678	1			T30	61		T31	42		T32	15
all_pins[4]	transitions[0x0=>0x1]	824481	1			T30	50		T31	21		T32	9
all_pins[4]	transitions[0x1=>0x0]	825475	1			T30	63		T31	26		T32	7
all_pins[5]	values[0x0]	2259030	1			T30	170		T31	48		T32	71
all_pins[5]	values[0x1]	1376390	1			T30	66		T31	46		T32	20
all_pins[5]	transitions[0x0=>0x1]	823220	1			T30	40		T31	26		T32	11
all_pins[5]	transitions[0x1=>0x0]	824508	1			T30	35		T31	22		T32	6
all_pins[6]	values[0x0]	2257583	1			T30	132		T31	53		T32	65
all_pins[6]	values[0x1]	1377837	1			T30	104		T31	41		T32	26
all_pins[6]	transitions[0x0=>0x1]	823134	1			T30	68		T31	28		T32	14
all_pins[6]	transitions[0x1=>0x0]	821687	1			T30	30		T31	33		T32	8
all_pins[7]	values[0x0]	2258731	1			T30	134		T31	41		T32	75
all_pins[7]	values[0x1]	1376689	1			T30	102		T31	53		T32	16
all_pins[7]	transitions[0x0=>0x1]	824969	1			T30	58		T31	30		T32	11
all_pins[7]	transitions[0x1=>0x0]	826117	1			T30	60		T31	18		T32	21
all_pins[8]	values[0x0]	2255511	1			T30	149		T31	45		T32	69
all_pins[8]	values[0x1]	1379909	1			T30	87		T31	49		T32	22
all_pins[8]	transitions[0x0=>0x1]	826309	1			T30	27		T31	23		T32	14
all_pins[8]	transitions[0x1=>0x0]	823089	1			T30	42		T31	27		T32	8
all_pins[9]	values[0x0]	2256297	1			T30	143		T31	52		T32	74
all_pins[9]	values[0x1]	1379123	1			T30	93		T31	42		T32	17
all_pins[9]	transitions[0x0=>0x1]	824796	1			T30	87		T31	20		T32	8
all_pins[9]	transitions[0x1=>0x0]	825582	1			T30	81		T31	27		T32	13
all_pins[10]	values[0x0]	2260394	1			T30	125		T31	57		T32	81
all_pins[10]	values[0x1]	1375026	1			T30	111		T31	37		T32	10
all_pins[10]	transitions[0x0=>0x1]	821717	1			T30	69		T31	22		T32	2
all_pins[10]	transitions[0x1=>0x0]	825814	1			T30	51		T31	27		T32	9
all_pins[11]	values[0x0]	2255964	1			T30	116		T31	46		T32	77
all_pins[11]	values[0x1]	1379456	1			T30	120		T31	48		T32	14
all_pins[11]	transitions[0x0=>0x1]	824927	1			T30	94		T31	24		T32	14
all_pins[11]	transitions[0x1=>0x0]	820497	1			T30	85		T31	13		T32	10
all_pins[12]	values[0x0]	2249095	1			T30	152		T31	48		T32	84
all_pins[12]	values[0x1]	1386325	1			T30	84		T31	46		T32	7
all_pins[12]	transitions[0x0=>0x1]	830669	1			T30	15		T31	24		T32	7
all_pins[12]	transitions[0x1=>0x0]	823800	1			T30	51		T31	26		T32	14
all_pins[13]	values[0x0]	2258536	1			T30	145		T31	49		T32	76
all_pins[13]	values[0x1]	1376884	1			T30	91		T31	45		T32	15
all_pins[13]	transitions[0x0=>0x1]	822886	1			T30	49		T31	23		T32	12
all_pins[13]	transitions[0x1=>0x0]	832327	1			T30	42		T31	24		T32	4
all_pins[14]	values[0x0]	2257701	1			T30	74		T31	54		T32	62
all_pins[14]	values[0x1]	1377719	1			T30	162		T31	40		T32	29
all_pins[14]	transitions[0x0=>0x1]	827021	1			T30	100		T31	20		T32	21
all_pins[14]	transitions[0x1=>0x0]	826186	1			T30	29		T31	25		T32	7
all_pins[15]	values[0x0]	2259645	1			T30	156		T31	52		T32	71
all_pins[15]	values[0x1]	1375775	1			T30	80		T31	42		T32	20
all_pins[15]	transitions[0x0=>0x1]	825395	1			T30	37		T31	23		T32	5
all_pins[15]	transitions[0x1=>0x0]	827339	1			T30	119		T31	21		T32	14
all_pins[16]	values[0x0]	2260528	1			T30	144		T31	49		T32	84
all_pins[16]	values[0x1]	1374892	1			T30	92		T31	45		T32	7
all_pins[16]	transitions[0x0=>0x1]	823146	1			T30	72		T31	23		T32	1
all_pins[16]	transitions[0x1=>0x0]	824029	1			T30	60		T31	20		T32	14
all_pins[17]	values[0x0]	2257908	1			T30	118		T31	52		T32	80
all_pins[17]	values[0x1]	1377512	1			T30	118		T31	42		T32	11
all_pins[17]	transitions[0x0=>0x1]	826162	1			T30	56		T31	18		T32	11
all_pins[17]	transitions[0x1=>0x0]	823542	1			T30	30		T31	21		T32	7
all_pins[18]	values[0x0]	2258244	1			T30	104		T31	41		T32	66
all_pins[18]	values[0x1]	1377176	1			T30	132		T31	53		T32	25
all_pins[18]	transitions[0x0=>0x1]	826879	1			T30	53		T31	30		T32	19
all_pins[18]	transitions[0x1=>0x0]	827215	1			T30	39		T31	19		T32	5
all_pins[19]	values[0x0]	2263474	1			T30	128		T31	40		T32	81
all_pins[19]	values[0x1]	1371946	1			T30	108		T31	54		T32	10
all_pins[19]	transitions[0x0=>0x1]	821809	1			T30	56		T31	24		T32	7
all_pins[19]	transitions[0x1=>0x0]	827039	1			T30	80		T31	23		T32	22
all_pins[20]	values[0x0]	2257984	1			T30	138		T31	39		T32	64
all_pins[20]	values[0x1]	1377436	1			T30	98		T31	55		T32	27
all_pins[20]	transitions[0x0=>0x1]	824591	1			T30	80		T31	25		T32	21
all_pins[20]	transitions[0x1=>0x0]	819101	1			T30	90		T31	24		T32	4
all_pins[21]	values[0x0]	2264283	1			T30	126		T31	53		T32	74
all_pins[21]	values[0x1]	1371137	1			T30	110		T31	41		T32	17
all_pins[21]	transitions[0x0=>0x1]	819795	1			T30	43		T31	16		T32	4
all_pins[21]	transitions[0x1=>0x0]	826094	1			T30	31		T31	30		T32	14
all_pins[22]	values[0x0]	2257479	1			T30	195		T31	58		T32	73
all_pins[22]	values[0x1]	1377941	1			T30	41		T31	36		T32	18
all_pins[22]	transitions[0x0=>0x1]	827903	1			T30	6		T31	18		T32	13
all_pins[22]	transitions[0x1=>0x0]	821099	1			T30	75		T31	23		T32	12
all_pins[23]	values[0x0]	2260007	1			T30	88		T31	54		T32	69
all_pins[23]	values[0x1]	1375413	1			T30	148		T31	40		T32	22
all_pins[23]	transitions[0x0=>0x1]	821925	1			T30	122		T31	21		T32	17
all_pins[23]	transitions[0x1=>0x0]	824453	1			T30	15		T31	17		T32	13
all_pins[24]	values[0x0]	2256879	1			T30	126		T31	46		T32	73
all_pins[24]	values[0x1]	1378541	1			T30	110		T31	48		T32	18
all_pins[24]	transitions[0x0=>0x1]	827466	1			T30	49		T31	24		T32	4
all_pins[24]	transitions[0x1=>0x0]	824338	1			T30	87		T31	16		T32	8
all_pins[25]	values[0x0]	2259622	1			T30	93		T31	47		T32	73
all_pins[25]	values[0x1]	1375798	1			T30	143		T31	47		T32	18
all_pins[25]	transitions[0x0=>0x1]	825208	1			T30	74		T31	25		T32	13
all_pins[25]	transitions[0x1=>0x0]	827951	1			T30	41		T31	26		T32	13
all_pins[26]	values[0x0]	2260910	1			T30	126		T31	44		T32	77
all_pins[26]	values[0x1]	1374510	1			T30	110		T31	50		T32	14
all_pins[26]	transitions[0x0=>0x1]	823865	1			T30	30		T31	22		T32	11
all_pins[26]	transitions[0x1=>0x0]	825153	1			T30	63		T31	19		T32	15
all_pins[27]	values[0x0]	2263164	1			T30	190		T31	45		T32	83
all_pins[27]	values[0x1]	1372256	1			T30	46		T31	49		T32	8
all_pins[27]	transitions[0x0=>0x1]	822397	1			T30	22		T31	25		T32	7
all_pins[27]	transitions[0x1=>0x0]	824651	1			T30	86		T31	26		T32	13
all_pins[28]	values[0x0]	2263038	1			T30	109		T31	49		T32	69
all_pins[28]	values[0x1]	1372382	1			T30	127		T31	45		T32	22
all_pins[28]	transitions[0x0=>0x1]	824210	1			T30	90		T31	21		T32	22
all_pins[28]	transitions[0x1=>0x0]	824084	1			T30	9		T31	25		T32	8
all_pins[29]	values[0x0]	2262810	1			T30	141		T31	59		T32	83
all_pins[29]	values[0x1]	1372610	1			T30	95		T31	35		T32	8
all_pins[29]	transitions[0x0=>0x1]	823102	1			T30	56		T31	18		T32	2
all_pins[29]	transitions[0x1=>0x0]	822874	1			T30	88		T31	28		T32	16
all_pins[30]	values[0x0]	2255612	1			T30	171		T31	41		T32	71
all_pins[30]	values[0x1]	1379808	1			T30	65		T31	53		T32	20
all_pins[30]	transitions[0x0=>0x1]	826382	1			T30	40		T31	32		T32	14
all_pins[30]	transitions[0x1=>0x0]	819184	1			T30	70		T31	14		T32	2
all_pins[31]	values[0x0]	2252238	1			T30	198		T31	50		T32	72
all_pins[31]	values[0x1]	1383182	1			T30	38		T31	44		T32	19
all_pins[31]	transitions[0x0=>0x1]	828258	1			T30	16		T31	13		T32	12
all_pins[31]	transitions[0x1=>0x0]	824884	1			T30	43		T31	22		T32	13