Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12320992	1			T30	701		T31	1549		T32	144
all_values[1]	12320992	1			T30	701		T31	1549		T32	144
all_values[2]	12320992	1			T30	701		T31	1549		T32	144
all_values[3]	12320992	1			T30	701		T31	1549		T32	144
all_values[4]	12320992	1			T30	701		T31	1549		T32	144
all_values[5]	12320992	1			T30	701		T31	1549		T32	144
all_values[6]	12320992	1			T30	701		T31	1549		T32	144
all_values[7]	12320992	1			T30	701		T31	1549		T32	144
all_values[8]	12320992	1			T30	701		T31	1549		T32	144
all_values[9]	12320992	1			T30	701		T31	1549		T32	144
all_values[10]	12320992	1			T30	701		T31	1549		T32	144
all_values[11]	12320992	1			T30	701		T31	1549		T32	144
all_values[12]	12320992	1			T30	701		T31	1549		T32	144
all_values[13]	12320992	1			T30	701		T31	1549		T32	144
all_values[14]	12320992	1			T30	701		T31	1549		T32	144
all_values[15]	12320992	1			T30	701		T31	1549		T32	144
all_values[16]	12320992	1			T30	701		T31	1549		T32	144
all_values[17]	12320992	1			T30	701		T31	1549		T32	144
all_values[18]	12320992	1			T30	701		T31	1549		T32	144
all_values[19]	12320992	1			T30	701		T31	1549		T32	144
all_values[20]	12320992	1			T30	701		T31	1549		T32	144
all_values[21]	12320992	1			T30	701		T31	1549		T32	144
all_values[22]	12320992	1			T30	701		T31	1549		T32	144
all_values[23]	12320992	1			T30	701		T31	1549		T32	144
all_values[24]	12320992	1			T30	701		T31	1549		T32	144
all_values[25]	12320992	1			T30	701		T31	1549		T32	144
all_values[26]	12320992	1			T30	701		T31	1549		T32	144
all_values[27]	12320992	1			T30	701		T31	1549		T32	144
all_values[28]	12320992	1			T30	701		T31	1549		T32	144
all_values[29]	12320992	1			T30	701		T31	1549		T32	144
all_values[30]	12320992	1			T30	701		T31	1549		T32	144
all_values[31]	12320992	1			T30	701		T31	1549		T32	144

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230203291

1

T30

10686

T31

49568

T32

3275

auto[1]

164068453

1

T30

11746

T32

1333

T33

12887

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97559181

1

T30

1897

T31

49568

T32

2597

auto[1]

296712563

1

T30

20535

T32

2011

T33

24613

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

390085640

1

T30

22432

T31

49568

T32

4359

auto[1]

4186104

1

T32

249

T35

1439

T40

19985

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2547965	1			T30	61		T31	1549		T32	70
all_values[0]	auto[0]	auto[0]	auto[1]	4587296	1			T30	227		T32	42		T33	470
all_values[0]	auto[0]	auto[1]	auto[0]	498223	1			T30	81		T32	8		T33	12
all_values[0]	auto[0]	auto[1]	auto[1]	4556621	1			T30	332		T32	16		T33	315
all_values[0]	auto[1]	auto[0]	auto[1]	65218	1			T32	7		T35	18		T40	296
all_values[0]	auto[1]	auto[1]	auto[1]	65669	1			T32	1		T35	18		T40	323
all_values[1]	auto[0]	auto[0]	auto[0]	2550800	1			T30	13		T31	1549		T32	43
all_values[1]	auto[0]	auto[0]	auto[1]	4572596	1			T30	190		T32	56		T33	422
all_values[1]	auto[0]	auto[1]	auto[0]	497731	1			T30	69		T32	17		T33	9
all_values[1]	auto[0]	auto[1]	auto[1]	4569071	1			T30	429		T32	19		T33	384
all_values[1]	auto[1]	auto[0]	auto[1]	65319	1			T32	8		T35	17		T40	304
all_values[1]	auto[1]	auto[1]	auto[1]	65475	1			T32	1		T35	26		T40	322
all_values[2]	auto[0]	auto[0]	auto[0]	2545116	1			T30	15		T31	1549		T32	63
all_values[2]	auto[0]	auto[0]	auto[1]	4562199	1			T30	506		T32	41		T33	476
all_values[2]	auto[0]	auto[1]	auto[0]	494784	1			T30	14		T32	11		T33	10
all_values[2]	auto[0]	auto[1]	auto[1]	4588290	1			T30	166		T32	20		T33	333
all_values[2]	auto[1]	auto[0]	auto[1]	65344	1			T32	7		T35	18		T40	350
all_values[2]	auto[1]	auto[1]	auto[1]	65259	1			T32	2		T35	22		T40	299
all_values[3]	auto[0]	auto[0]	auto[0]	2549468	1			T30	40		T31	1549		T32	63
all_values[3]	auto[0]	auto[0]	auto[1]	4566584	1			T30	386		T32	38		T33	456
all_values[3]	auto[0]	auto[1]	auto[0]	498528	1			T30	36		T32	23		T33	29
all_values[3]	auto[0]	auto[1]	auto[1]	4575706	1			T30	239		T32	12		T33	323
all_values[3]	auto[1]	auto[0]	auto[1]	65652	1			T32	6		T35	28		T40	322
all_values[3]	auto[1]	auto[1]	auto[1]	65054	1			T32	2		T35	13		T40	307
all_values[4]	auto[0]	auto[0]	auto[0]	2547328	1			T30	24		T31	1549		T32	57
all_values[4]	auto[0]	auto[0]	auto[1]	4601481	1			T30	425		T32	35		T33	441
all_values[4]	auto[0]	auto[1]	auto[0]	497278	1			T30	26		T32	26		T33	22
all_values[4]	auto[0]	auto[1]	auto[1]	4544735	1			T30	226		T32	14		T33	326
all_values[4]	auto[1]	auto[0]	auto[1]	65515	1			T32	11		T35	19		T40	304
all_values[4]	auto[1]	auto[1]	auto[1]	64655	1			T32	1		T35	21		T40	321
all_values[5]	auto[0]	auto[0]	auto[0]	2548833	1			T30	88		T31	1549		T32	65
all_values[5]	auto[0]	auto[0]	auto[1]	4566359	1			T30	309		T32	37		T33	512
all_values[5]	auto[0]	auto[1]	auto[0]	500028	1			T30	82		T32	13		T33	34
all_values[5]	auto[0]	auto[1]	auto[1]	4574357	1			T30	222		T32	22		T33	197
all_values[5]	auto[1]	auto[0]	auto[1]	66004	1			T32	4		T35	18		T40	321
all_values[5]	auto[1]	auto[1]	auto[1]	65411	1			T32	3		T35	21		T40	335
all_values[6]	auto[0]	auto[0]	auto[0]	2545791	1			T30	25		T31	1549		T32	63
all_values[6]	auto[0]	auto[0]	auto[1]	4579859	1			T30	245		T32	33		T33	459
all_values[6]	auto[0]	auto[1]	auto[0]	495802	1			T30	44		T32	18		T33	19
all_values[6]	auto[0]	auto[1]	auto[1]	4568739	1			T30	387		T32	22		T33	359
all_values[6]	auto[1]	auto[0]	auto[1]	65985	1			T32	3		T35	28		T40	320
all_values[6]	auto[1]	auto[1]	auto[1]	64816	1			T32	5		T35	23		T40	295
all_values[7]	auto[0]	auto[0]	auto[0]	2555426	1			T30	23		T31	1549		T32	47
all_values[7]	auto[0]	auto[0]	auto[1]	4555893	1			T30	325		T32	50		T33	484
all_values[7]	auto[0]	auto[1]	auto[0]	503829	1			T30	21		T32	22		T33	20
all_values[7]	auto[0]	auto[1]	auto[1]	4575129	1			T30	332		T32	17		T33	320
all_values[7]	auto[1]	auto[0]	auto[1]	65521	1			T32	4		T35	16		T40	293
all_values[7]	auto[1]	auto[1]	auto[1]	65194	1			T32	4		T35	26		T40	343
all_values[8]	auto[0]	auto[0]	auto[0]	2551920	1			T30	28		T31	1549		T32	61
all_values[8]	auto[0]	auto[0]	auto[1]	4571866	1			T30	331		T32	29		T33	166
all_values[8]	auto[0]	auto[1]	auto[0]	497666	1			T30	30		T32	13		T33	81
all_values[8]	auto[0]	auto[1]	auto[1]	4568229	1			T30	312		T32	33		T33	592
all_values[8]	auto[1]	auto[0]	auto[1]	66095	1			T32	8		T35	26		T40	296
all_values[8]	auto[1]	auto[1]	auto[1]	65216	1			T35	25		T40	326		T113	30
all_values[9]	auto[0]	auto[0]	auto[0]	2551589	1			T30	10		T31	1549		T32	41
all_values[9]	auto[0]	auto[0]	auto[1]	4569025	1			T30	352		T32	51		T33	280
all_values[9]	auto[0]	auto[1]	auto[0]	499998	1			T30	56		T32	24		T33	33
all_values[9]	auto[0]	auto[1]	auto[1]	4569736	1			T30	283		T32	20		T33	529
all_values[9]	auto[1]	auto[0]	auto[1]	66130	1			T32	8		T35	24		T40	319
all_values[9]	auto[1]	auto[1]	auto[1]	64514	1			T35	19		T40	285		T113	35
all_values[10]	auto[0]	auto[0]	auto[0]	2552160	1			T30	40		T31	1549		T32	65
all_values[10]	auto[0]	auto[0]	auto[1]	4576731	1			T30	290		T32	56		T33	331
all_values[10]	auto[0]	auto[1]	auto[0]	499916	1			T30	10		T32	2		T33	44
all_values[10]	auto[0]	auto[1]	auto[1]	4561351	1			T30	361		T32	10		T33	440
all_values[10]	auto[1]	auto[0]	auto[1]	65494	1			T32	9		T35	27		T40	296
all_values[10]	auto[1]	auto[1]	auto[1]	65340	1			T32	2		T35	17		T40	314
all_values[11]	auto[0]	auto[0]	auto[0]	2547057	1			T30	2		T31	1549		T32	62
all_values[11]	auto[0]	auto[0]	auto[1]	4596277	1			T30	224		T32	29		T33	448
all_values[11]	auto[0]	auto[1]	auto[0]	489417	1			T30	43		T32	29		T33	55
all_values[11]	auto[0]	auto[1]	auto[1]	4557229	1			T30	432		T32	15		T33	296
all_values[11]	auto[1]	auto[0]	auto[1]	65959	1			T32	7		T35	19		T40	323
all_values[11]	auto[1]	auto[1]	auto[1]	65053	1			T32	2		T35	20		T40	303
all_values[12]	auto[0]	auto[0]	auto[0]	2561054	1			T30	27		T31	1549		T32	61
all_values[12]	auto[0]	auto[0]	auto[1]	4551033	1			T30	357		T32	43		T33	318
all_values[12]	auto[0]	auto[1]	auto[0]	508684	1			T30	21		T32	24		T33	39
all_values[12]	auto[0]	auto[1]	auto[1]	4569365	1			T30	296		T32	5		T33	422
all_values[12]	auto[1]	auto[0]	auto[1]	65182	1			T32	7		T35	30		T40	309
all_values[12]	auto[1]	auto[1]	auto[1]	65674	1			T32	4		T35	15		T40	324
all_values[13]	auto[0]	auto[0]	auto[0]	2552672	1			T30	26		T31	1549		T32	69
all_values[13]	auto[0]	auto[0]	auto[1]	4577876	1			T30	339		T32	20		T33	541
all_values[13]	auto[0]	auto[1]	auto[0]	494081	1			T30	13		T32	33		T33	17
all_values[13]	auto[0]	auto[1]	auto[1]	4565784	1			T30	323		T32	17		T33	275
all_values[13]	auto[1]	auto[0]	auto[1]	65496	1			T32	3		T35	18		T40	313
all_values[13]	auto[1]	auto[1]	auto[1]	65083	1			T32	2		T35	30		T40	326
all_values[14]	auto[0]	auto[0]	auto[0]	2551955	1			T30	5		T31	1549		T32	61
all_values[14]	auto[0]	auto[0]	auto[1]	4578192	1			T30	174		T32	23		T33	315
all_values[14]	auto[0]	auto[1]	auto[0]	502729	1			T30	9		T32	17		T33	7
all_values[14]	auto[0]	auto[1]	auto[1]	4557060	1			T30	513		T32	37		T33	483
all_values[14]	auto[1]	auto[0]	auto[1]	65588	1			T32	3		T35	20		T40	303
all_values[14]	auto[1]	auto[1]	auto[1]	65468	1			T32	3		T35	24		T40	326
all_values[15]	auto[0]	auto[0]	auto[0]	2550568	1			T30	45		T31	1549		T32	77
all_values[15]	auto[0]	auto[0]	auto[1]	4583045	1			T30	285		T32	25		T33	350
all_values[15]	auto[0]	auto[1]	auto[0]	506418	1			T30	44		T32	12		T33	35
all_values[15]	auto[0]	auto[1]	auto[1]	4550080	1			T30	327		T32	23		T33	407
all_values[15]	auto[1]	auto[0]	auto[1]	65472	1			T32	4		T35	20		T40	290
all_values[15]	auto[1]	auto[1]	auto[1]	65409	1			T32	3		T35	19		T40	321
all_values[16]	auto[0]	auto[0]	auto[0]	2545978	1			T30	26		T31	1549		T32	72
all_values[16]	auto[0]	auto[0]	auto[1]	4577454	1			T30	312		T32	31		T33	487
all_values[16]	auto[0]	auto[1]	auto[0]	499594	1			T30	28		T32	28		T33	24
all_values[16]	auto[0]	auto[1]	auto[1]	4567340	1			T30	335		T32	9		T33	290
all_values[16]	auto[1]	auto[0]	auto[1]	65717	1			T32	3		T35	25		T40	299
all_values[16]	auto[1]	auto[1]	auto[1]	64909	1			T32	1		T35	20		T40	320
all_values[17]	auto[0]	auto[0]	auto[0]	2552967	1			T30	10		T31	1549		T32	67
all_values[17]	auto[0]	auto[0]	auto[1]	4567697	1			T30	253		T32	45		T33	434
all_values[17]	auto[0]	auto[1]	auto[0]	495117	1			T30	38		T32	9		T33	24
all_values[17]	auto[0]	auto[1]	auto[1]	4574756	1			T30	400		T32	17		T33	335
all_values[17]	auto[1]	auto[0]	auto[1]	65509	1			T32	5		T35	21		T40	298
all_values[17]	auto[1]	auto[1]	auto[1]	64946	1			T32	1		T35	14		T40	337
all_values[18]	auto[0]	auto[0]	auto[0]	2554708	1			T30	16		T31	1549		T32	56
all_values[18]	auto[0]	auto[0]	auto[1]	4556201	1			T30	228		T32	35		T33	430
all_values[18]	auto[0]	auto[1]	auto[0]	495264	1			T30	12		T32	19		T33	26
all_values[18]	auto[0]	auto[1]	auto[1]	4583887	1			T30	445		T32	29		T33	365
all_values[18]	auto[1]	auto[0]	auto[1]	65660	1			T32	2		T35	24		T40	307
all_values[18]	auto[1]	auto[1]	auto[1]	65272	1			T32	3		T35	25		T40	321
all_values[19]	auto[0]	auto[0]	auto[0]	2552238	1			T30	5		T31	1549		T32	60
all_values[19]	auto[0]	auto[0]	auto[1]	4557022	1			T30	262		T32	42		T33	304
all_values[19]	auto[0]	auto[1]	auto[0]	498717	1			T30	28		T32	18		T33	82
all_values[19]	auto[0]	auto[1]	auto[1]	4582179	1			T30	406		T32	17		T33	448
all_values[19]	auto[1]	auto[0]	auto[1]	65754	1			T32	7		T35	24		T40	307
all_values[19]	auto[1]	auto[1]	auto[1]	65082	1			T35	19		T40	300		T113	45
all_values[20]	auto[0]	auto[0]	auto[0]	2551868	1			T30	16		T31	1549		T32	68
all_values[20]	auto[0]	auto[0]	auto[1]	4615372	1			T30	356		T32	10		T33	433
all_values[20]	auto[0]	auto[1]	auto[0]	495194	1			T30	12		T32	26		T33	49
all_values[20]	auto[0]	auto[1]	auto[1]	4527647	1			T30	317		T32	30		T33	312
all_values[20]	auto[1]	auto[0]	auto[1]	65800	1			T32	4		T35	27		T40	311
all_values[20]	auto[1]	auto[1]	auto[1]	65111	1			T32	6		T35	26		T40	314
all_values[21]	auto[0]	auto[0]	auto[0]	2552303	1			T30	11		T31	1549		T32	64
all_values[21]	auto[0]	auto[0]	auto[1]	4593538	1			T30	295		T32	30		T33	455
all_values[21]	auto[0]	auto[1]	auto[0]	498774	1			T30	13		T32	22		T33	20
all_values[21]	auto[0]	auto[1]	auto[1]	4545563	1			T30	382		T32	23		T33	326
all_values[21]	auto[1]	auto[0]	auto[1]	65536	1			T32	4		T35	22		T40	321
all_values[21]	auto[1]	auto[1]	auto[1]	65278	1			T32	1		T35	20		T40	322
all_values[22]	auto[0]	auto[0]	auto[0]	2552457	1			T30	35		T31	1549		T32	56
all_values[22]	auto[0]	auto[0]	auto[1]	4584918	1			T30	501		T32	28		T33	381
all_values[22]	auto[0]	auto[1]	auto[0]	498254	1			T30	14		T32	32		T33	41
all_values[22]	auto[0]	auto[1]	auto[1]	4554613	1			T30	151		T32	19		T33	361
all_values[22]	auto[1]	auto[0]	auto[1]	65610	1			T32	5		T35	30		T40	322
all_values[22]	auto[1]	auto[1]	auto[1]	65140	1			T32	4		T35	20		T40	317
all_values[23]	auto[0]	auto[0]	auto[0]	2550598	1			T30	7		T31	1549		T32	46
all_values[23]	auto[0]	auto[0]	auto[1]	4582288	1			T30	187		T32	39		T33	332
all_values[23]	auto[0]	auto[1]	auto[0]	492738	1			T30	37		T32	29		T33	45
all_values[23]	auto[0]	auto[1]	auto[1]	4564862	1			T30	470		T32	18		T33	423
all_values[23]	auto[1]	auto[0]	auto[1]	65708	1			T32	8		T35	34		T40	305
all_values[23]	auto[1]	auto[1]	auto[1]	64798	1			T32	4		T35	19		T40	300
all_values[24]	auto[0]	auto[0]	auto[0]	2552330	1			T30	21		T31	1549		T32	53
all_values[24]	auto[0]	auto[0]	auto[1]	4570061	1			T30	260		T32	32		T33	195
all_values[24]	auto[0]	auto[1]	auto[0]	498381	1			T30	34		T32	28		T33	71
all_values[24]	auto[0]	auto[1]	auto[1]	4568834	1			T30	386		T32	22		T33	576
all_values[24]	auto[1]	auto[0]	auto[1]	65531	1			T32	6		T35	22		T40	315
all_values[24]	auto[1]	auto[1]	auto[1]	65855	1			T32	3		T35	20		T40	280
all_values[25]	auto[0]	auto[0]	auto[0]	2553577	1			T30	18		T31	1549		T32	82
all_values[25]	auto[0]	auto[0]	auto[1]	4564070	1			T30	163		T32	25		T33	458
all_values[25]	auto[0]	auto[1]	auto[0]	496942	1			T30	34		T32	11		T33	29
all_values[25]	auto[0]	auto[1]	auto[1]	4576082	1			T30	486		T32	24		T33	252
all_values[25]	auto[1]	auto[0]	auto[1]	65405	1			T32	1		T35	19		T40	328
all_values[25]	auto[1]	auto[1]	auto[1]	64916	1			T32	1		T35	23		T40	276
all_values[26]	auto[0]	auto[0]	auto[0]	2541391	1			T30	44		T31	1549		T32	45
all_values[26]	auto[0]	auto[0]	auto[1]	4573523	1			T30	212		T32	51		T33	365
all_values[26]	auto[0]	auto[1]	auto[0]	494100	1			T30	34		T32	24		T33	33
all_values[26]	auto[0]	auto[1]	auto[1]	4580845	1			T30	411		T32	16		T33	403
all_values[26]	auto[1]	auto[0]	auto[1]	65519	1			T32	5		T35	24		T40	284
all_values[26]	auto[1]	auto[1]	auto[1]	65614	1			T32	3		T35	23		T40	341
all_values[27]	auto[0]	auto[0]	auto[0]	2546833	1			T30	40		T31	1549		T32	63
all_values[27]	auto[0]	auto[0]	auto[1]	4617559	1			T30	454		T32	46		T33	421
all_values[27]	auto[0]	auto[1]	auto[0]	500138	1			T30	28		T32	26		T33	47
all_values[27]	auto[0]	auto[1]	auto[1]	4525932	1			T30	179		T32	5		T33	344
all_values[27]	auto[1]	auto[0]	auto[1]	65561	1			T32	2		T35	34		T40	295
all_values[27]	auto[1]	auto[1]	auto[1]	64969	1			T32	2		T35	19		T40	333
all_values[28]	auto[0]	auto[0]	auto[0]	2550121	1			T30	19		T31	1549		T32	73
all_values[28]	auto[0]	auto[0]	auto[1]	4600978	1			T30	183		T32	22		T33	507
all_values[28]	auto[0]	auto[1]	auto[0]	497064	1			T30	58		T32	18		T33	35
all_values[28]	auto[0]	auto[1]	auto[1]	4541644	1			T30	441		T32	24		T33	219
all_values[28]	auto[1]	auto[0]	auto[1]	65871	1			T32	4		T35	15		T40	366
all_values[28]	auto[1]	auto[1]	auto[1]	65314	1			T32	3		T35	27		T40	263
all_values[29]	auto[0]	auto[0]	auto[0]	2557599	1			T30	19		T31	1549		T32	52
all_values[29]	auto[0]	auto[0]	auto[1]	4563053	1			T30	331		T32	45		T33	331
all_values[29]	auto[0]	auto[1]	auto[0]	501061	1			T30	27		T32	28		T33	47
all_values[29]	auto[0]	auto[1]	auto[1]	4568390	1			T30	324		T32	9		T33	395
all_values[29]	auto[1]	auto[0]	auto[1]	65627	1			T32	9		T35	24		T40	342
all_values[29]	auto[1]	auto[1]	auto[1]	65262	1			T32	1		T35	24		T40	283
all_values[30]	auto[0]	auto[0]	auto[0]	2553996	1			T30	30		T31	1549		T32	62
all_values[30]	auto[0]	auto[0]	auto[1]	4566075	1			T30	386		T32	27		T33	272
all_values[30]	auto[0]	auto[1]	auto[0]	497282	1			T30	47		T32	24		T33	62
all_values[30]	auto[0]	auto[1]	auto[1]	4572985	1			T30	238		T32	22		T33	482
all_values[30]	auto[1]	auto[0]	auto[1]	65688	1			T32	6		T35	34		T40	329
all_values[30]	auto[1]	auto[1]	auto[1]	64966	1			T32	3		T35	26		T40	290
all_values[31]	auto[0]	auto[0]	auto[0]	2544112	1			T30	58		T31	1549		T32	57
all_values[31]	auto[0]	auto[0]	auto[1]	4594340	1			T30	491		T32	39		T33	568
all_values[31]	auto[0]	auto[1]	auto[0]	492671	1			T30	7		T32	19		T33	15
all_values[31]	auto[0]	auto[1]	auto[1]	4558957	1			T30	145		T32	21		T33	239
all_values[31]	auto[1]	auto[0]	auto[1]	65582	1			T32	6		T35	16		T40	289
all_values[31]	auto[1]	auto[1]	auto[1]	65330	1			T32	2		T35	34		T40	341

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal